WO2004031981A3 - Multilevel hierarchical circuit - Google Patents

Multilevel hierarchical circuit Download PDF

Info

Publication number
WO2004031981A3
WO2004031981A3 PCT/IB2003/004120 IB0304120W WO2004031981A3 WO 2004031981 A3 WO2004031981 A3 WO 2004031981A3 IB 0304120 W IB0304120 W IB 0304120W WO 2004031981 A3 WO2004031981 A3 WO 2004031981A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing unit
controller
hierarchical circuit
multilevel hierarchical
circuit
Prior art date
Application number
PCT/IB2003/004120
Other languages
French (fr)
Other versions
WO2004031981A2 (en
Inventor
Marc Duranton
Laurent Pasquier
Valerie Rivierre
Qin Zhao
Original Assignee
Koninkl Philips Electronics Nv
Marc Duranton
Laurent Pasquier
Valerie Rivierre
Qin Zhao
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Marc Duranton, Laurent Pasquier, Valerie Rivierre, Qin Zhao filed Critical Koninkl Philips Electronics Nv
Priority to AU2003260887A priority Critical patent/AU2003260887A1/en
Publication of WO2004031981A2 publication Critical patent/WO2004031981A2/en
Publication of WO2004031981A3 publication Critical patent/WO2004031981A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G06F9/4486—Formation of subprogram jump address

Abstract

The invention relates to a circuit comprising a first processing unit (111) for carrying out a program that includes subroutine calls, and a second processing unit (112) for performing subroutine calls. The circuit comprises a first controller (101) for controlling the first processing unit and a second controller (102) for controlling the second processing unit. The first controller sends instructions to the second controller to trigger the subroutine call.
PCT/IB2003/004120 2002-10-04 2003-09-18 Multilevel hierarchical circuit WO2004031981A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003260887A AU2003260887A1 (en) 2002-10-04 2003-09-18 Multilevel hierarchical circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02292462 2002-10-04
EP02292462.5 2002-10-04

Publications (2)

Publication Number Publication Date
WO2004031981A2 WO2004031981A2 (en) 2004-04-15
WO2004031981A3 true WO2004031981A3 (en) 2005-02-03

Family

ID=32050106

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/004120 WO2004031981A2 (en) 2002-10-04 2003-09-18 Multilevel hierarchical circuit

Country Status (2)

Country Link
AU (1) AU2003260887A1 (en)
WO (1) WO2004031981A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0726529A2 (en) * 1994-12-29 1996-08-14 International Business Machines Corporation Array processor topology reconfiguration system and method
US5862397A (en) * 1995-12-19 1999-01-19 Commissariat A L'energie Atomique Array system architecture of multiple parallel structure processors
WO2000039689A1 (en) * 1997-10-15 2000-07-06 Fifth Generation Computer Corporation Parallel computing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0726529A2 (en) * 1994-12-29 1996-08-14 International Business Machines Corporation Array processor topology reconfiguration system and method
US5862397A (en) * 1995-12-19 1999-01-19 Commissariat A L'energie Atomique Array system architecture of multiple parallel structure processors
WO2000039689A1 (en) * 1997-10-15 2000-07-06 Fifth Generation Computer Corporation Parallel computing system

Also Published As

Publication number Publication date
AU2003260887A1 (en) 2004-04-23
AU2003260887A8 (en) 2004-04-23
WO2004031981A2 (en) 2004-04-15

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