WO2004025849A1

WO2004025849A1 - Semiconductor integrated circuit for communication and radio communication system

Info

Publication number: WO2004025849A1
Application number: PCT/JP2002/009394
Authority: WO
Inventors: Nobuyuki Tsujimoto; Noriyuki Kurakami; Hirotaka Oosawa; Fumiaki Matsuzaki
Original assignee: Renesas Technology Corp.
Priority date: 2002-09-13
Filing date: 2002-09-13
Publication date: 2004-03-25
Also published as: JPWO2004025849A1; JP3831908B2; TWI227968B

Abstract

A semiconductor integrated circuit for communication having at least one of reception VCO (250), transmission VCO (240a, 240b), and intermediate frequency VCO (230) formed together with a modulation/demodulation circuit on a single semiconductor chip. The on-chip VCO is constituted so as to be operable in a plurality of frequency bands. There are provided a circuit (22) for measuring an oscillation frequency of the VCO, a storage circuit (18) for storing the measured value, and a circuit (19) for comparing the measured value stored in the storage circuit to an external preset value so as to determine the usable frequency band of the VCO. Data stored in the storage circuit can be read out and data can be written from outside.

Description

Description Semiconductor integrated circuits for communication and wireless communication systems

Technical field

The present invention relates to a technology that is effective when applied to a method of measuring characteristics of a VCO (voltage controlled oscillation circuit) and a method of storing a measured value when a power supply is turned off. The present invention relates to a high frequency semiconductor integrated circuit that modulates and demodulates a transmission / reception signal in a wireless communication system, and a technology effective for use in a mobile phone using the same. Background art

In a wireless communication system such as a mobile phone, a VCO is used to generate an oscillation signal of a predetermined frequency combined with a reception signal and a transmission signal. The mobile phones that are proposed traditional, for example 8 8 0~9 1 5MH _Z band of GSM (Global System for Mobile Communication) and 1 7 1 0~ 1 785 MH z band of DCS (Digital Cellular System) like There are dual-panel mobile phones that can handle signals in two different frequency bands. In addition, in such a dual-panel type mobile phone, by switching the frequency of VCO in a PLL circuit (phase-locked loop), one PLL circuit can support two bands. There is something.

In recent years, however, there has been a demand for triple-band type mobile phones capable of handling PCS (Personal Communication System) signals in the 1850 to 1915 MHz band in addition to 031 ^ 3. In addition, it is expected that mobile phones that can handle even more bands will be required in the future.

A high-frequency semiconductor integrated circuit (hereinafter, referred to as a high-frequency IC) that modulates a transmission signal and demodulates a reception signal used in a mobile phone that can handle such multiple bands has a low component count. The direct conversion method is effective. However, the direct conversion method requires multiple bands. Although it is relatively easy to deal with this, it is necessary to widen the frequency range in which the VCO can oscillate. Here, if one VCO attempts to support all frequencies, the sensitivity of the control voltage of the VCO becomes high, and it becomes vulnerable to external noise and power supply voltage fluctuation.

On the other hand, it is effective to reduce the number of components by forming a VCO, which is generally configured as a separate module from the high-frequency IC, on the same semiconductor chip as the high-frequency IC. However, with the current manufacturing technology, when VCO is on-chip, the variation in the absolute value of the oscillation frequency increases, so a function to correct the oscillation frequency after manufacturing is indispensable. If the correction of this parameter is attempted by trimming with a general mask option or bonding wire option used in a conventional semiconductor integrated circuit, cost increases cannot be avoided.

Therefore, the present inventors have set up an oscillation circuit (RFVCO) that generates a high-frequency signal used for transmission and reception so that it can operate in a plurality of bands, and fix a control voltage of the oscillation circuit at a predetermined value. Measures the oscillation frequency of the oscillation circuit in each band and stores it in the storage circuit, and compares the set value for frequency designation given at PLL startup with the measured value of the frequency stored above Then, it is configured so that the band actually used in the oscillation circuit is determined from the comparison result. As a result, even if the frequency range in which the VCO can oscillate is widened to support multiple communication methods, the sensitivity of the VCO control voltage will not increase, and it will not be affected by external noise and power supply voltage fluctuations. Has developed a communication semiconductor integrated circuit (high-frequency IC) equipped with a PLL circuit that can automatically correct the variation in the oscillation frequency of the VCO using an internal circuit, and filed an application for it (Japanese Patent Application No. 2002-1 1050). ).

In the prior application, the oscillation frequency of the VCO is measured, the measurement result is stored in a volatile storage circuit such as a register, and the characteristic variation of the VCO is automatically corrected by an internal circuit using the measurement result. It is configured to Therefore, when the power is turned off, the measurement result is lost.When the power is turned on again, it is necessary to measure and correct the VCO frequency again. And the power consumption increases.

Here, it is conceivable to configure the storage circuit with a nonvolatile memory so that the measurement result is not lost even when the power is turned off. However, current technology requires a non-volatile memory inside the chip, which complicates the process and significantly increases the cost of the chip, and requires a high voltage to write the nonvolatile memory. Therefore, a booster circuit must be provided, which increases the chip size and increases the power consumption of the booster circuit.Even if the power consumption is reduced by omitting the measurement of the VCO, the total power consumption is not so large. There is a defect that it may not decrease or may increase.

By the way, in order to extend the time that a mobile phone driven by a battery can be driven by one charge, it is desired that the semiconductor chips constituting the system consume as little power as possible. At the same time, mobile phones are often controlled to operate only the control CPU (microprocessor) and baseband LSI and turn off the power of the high frequency IC during standby. If the oscillation frequency of the VCO is measured and the measurement result is stored in a volatile storage circuit such as a register as in the above-mentioned prior invention, when the power of the high-frequency IC is turned off, When the power is turned on again, it is necessary to measure the oscillation frequency of the VCO again and perform an operation to correct the variation in characteristics based on the measurement result. In addition, it is desirable to configure the VCO so that it can oscillate in multiple frequency bands for the high-frequency Ic that constitutes a mobile phone that can transmit and receive multiple band signals. In such a case, the frequency of each frequency band is measured. And the measurement time is longer than that of a VCO operating in a single frequency band.

An object of the present invention is to provide a communication semiconductor integrated circuit suitable for configuring a mobile phone capable of transmitting and receiving a plurality of band signals and having low power consumption. Another object of the present invention is to provide a built-in oscillation circuit (VCO) and a communication semiconductor integrated circuit having a mechanism capable of measuring a characteristic variation thereof and correcting based on the measured value, and modulating a transmission signal and demodulating a reception signal. (High frequency IC), it is not necessary to measure the VCO oscillation frequency when the power is turned off and on again. To provide a communication semiconductor integrated circuit capable of reducing power consumption.

Another object of the present invention is to provide a built-in oscillation circuit (VCO) and a communication semiconductor integrated circuit having a mechanism capable of measuring a characteristic variation thereof and correcting based on the measured value, and modulating a transmission signal and demodulating a reception signal. It is an object of the present invention to provide a semiconductor integrated circuit for communication (high frequency IC) that can quickly shift the system to a normal operation state when the power is turned off and on again.

Yet another object of the present invention is to provide a mobile phone having a long battery life and a long operating time with one charge.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The following is a brief description of an outline of a typical invention disclosed in the present application.

At least one of the receiving VCO (voltage controlled oscillator), transmitting VCO, and intermediate frequency VCO, together with the modulation and demodulation circuit, is mounted on a single semiconductor chip. A circuit for measuring the oscillation frequency of the VCO, a storage circuit for storing the measured value, a measured value stored in the storage circuit, and an external set value. And a circuit for determining the use band of the VCO is provided, and the data stored in the storage circuit can be read out or written from the outside.

According to the above means, the oscillation frequency measurement value of the VCO stored in the storage circuit is saved in the external memory when the power of the communication semiconductor integrated circuit is turned off, and the saved data is saved when the power is turned on again. By restoring to the above, it is not necessary to measure the VCO oscillation frequency every time the power is turned on, and the power consumption of the semiconductor integrated circuit can be reduced. In addition, the rise time of the system, that is, The time required to reach the normal operation mode that can be started can be reduced, and the power consumption of the entire system can be reduced by turning off the power supply of the communication semiconductor integrated circuit.

Here, as a method that allows the storage data in the storage circuit to be read out and written out to the outside, a method of providing an external terminal and a function of transmitting and receiving data originally provided in the communication semiconductor integrated circuit are used. The power supply line that supplies the power supply voltage to the storage circuit that stores the measured frequency value of the VCO is provided separately from the power supply lines of circuits other than the storage circuit, so that the data in the storage circuit is not lost when the power is turned off. There is a method of backing up.

When an external terminal that can read and write the data stored in the storage circuit to the outside is provided, it may be provided as a dedicated terminal.However, it is possible to use a terminal for other existing signals. it can. In the case of a back-up system in which the power supply line of the storage circuit is provided separately from the power supply lines of circuits other than the storage circuit, the operation port of another semiconductor chip is externally provided based on the oscillation signal of the VCO in the communication semiconductor integrated circuit. It is preferable to provide a circuit for generating and outputting a chip on the same chip, and supply the power supply voltage to the circuit through the same power supply line as the storage circuit. As a result, even if the power supply of the semiconductor integrated circuit for communication is turned off, the loss of data in the storage circuit can be prevented, and the operation clock can be continuously supplied to other chips. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram illustrating a configuration example of a multi-band communication semiconductor integrated circuit (high frequency IC) to which the present invention is applied and a main part of a wireless communication system using the same.

FIG. 2 is a block diagram showing an embodiment of a PLL circuit including FVCO in a multi-band communication semiconductor integrated circuit (high frequency IC) to which the present invention is applied.

Figure 3 is a circuit diagram showing an embodiment of a communication semiconductor integrated circuit of a multi-Pando method according to the present invention a voltage-controlled oscillator in the (high-frequency IC) (VCO) _£ FIG. 4 is a graph showing a relationship between the control voltage Vc and the oscillation frequency f RF when the frequency variable range of the RFVCO is continuously changed and when the RFVCO is changed over a plurality of bands.

FIG. 5 is a block diagram showing an example of a schematic configuration of an RFPLL circuit and an example of a mechanism for reading out data of a storage circuit that stores a measured frequency value of RFPCO to the outside.

FIG. 6 is a flowchart showing a procedure of power-off / return operation of the high-frequency IC at the time of waiting for frequency measurement of each VCO in the wireless communication system of FIG. 5 using the high-frequency IC of the embodiment of FIG.

FIG. 7 is a timing chart showing the timing of the frequency measurement of each VCO in the wireless communication system using the high frequency IC of the embodiment of FIG. 2 and the correction of the frequency characteristic based on the measurement result (determination of the band to be used).

FIG. 8 is a block diagram showing a configuration example of a communication semiconductor integrated circuit (high frequency I C) of the second embodiment of the present invention and a main part of a wireless communication system using the same.

FIG. 9 is a block diagram showing a configuration example of a communication semiconductor integrated circuit (high-frequency IC) according to a third embodiment of the present invention and a main part of a wireless communication system using the same.

FIG. 10 is a flowchart illustrating a procedure of a power recovery of the high frequency Ic and a Z return operation in a wireless communication system using the high frequency IC of the embodiment of FIG. BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of a multi-band communication semiconductor integrated circuit (high frequency IC) to which the present invention is applied and a wireless communication system using the same. In FIG. 1, 100 is an antenna for transmitting and receiving signal radio waves, 110 is a switch for switching between transmission and reception, and 120 a to l 20 c are high-frequency waves such as a SAW filter that removes unnecessary waves from a received signal. A filter, 130 is a high-frequency power amplifier that amplifies the transmission signal, 200 is a high-frequency IC that demodulates the reception signal and modulates the transmission signal, and 300 is an I and Q signal that converts the transmission data. Convert or control high frequency IC 200 The control is a baseband circuit (LSI). The high-frequency IC 200 is configured as a semiconductor integrated circuit on one semiconductor chip.

Although not particularly limited, the high-frequency IC 200 of this embodiment is configured to be able to modulate and demodulate signals using four communication systems, GSM850 and GSM900, DCS1800, and PCS1900. In response to this, the high-frequency filter includes a filter 120a that passes a reception signal in the GSM frequency band, a filter 120b that passes a reception signal in the DCS 1800 frequency band, and a PCS 1 There is provided a filter 120c for passing a reception signal of 900 frequency bands. Since the frequency bands of GSM850 and GSM900 are close to each other, a common filter 120a is used in this embodiment.

The high-frequency IC 200 of the present embodiment is roughly divided into a reception system circuit RXC, a transmission system circuit TXC, and a control system circuit CTC including other circuits common to the transmission and reception systems such as a control circuit and a clock generation circuit. It consists of.

RX circuit RXC divides oscillation signal RF generated by low-noise amplifiers 210 a, 210 b, and 210 c that amplify received signals, and high-frequency oscillation circuit (RF VCO) 250 A phase shift divider 211 that generates quadrature signals that are 90 degrees out of phase with each other, and a phase shift divider 211 that converts the received signal amplified by the row noise amplifiers 210a, 210b, 210c. A demodulation circuit composed of a mixer that demodulates by combining the quadrature signals divided by 1 and a demodulation circuit that amplifies the demodulated I and Q signals, respectively. It comprises high gain amplifiers 22 OA and 22 OB to be output to the band circuit 300, and an offset canceller circuit 213 for canceling the input DC offset of the amplifier in the high gain amplifiers 220A and 220B.

The high-gain amplifier 220 A has a plurality of aperture filters LPF ll, LPF 12, LPF 13, LPF 14 and gain control amplifiers PGA 11, PGA 1, PGA 13 connected alternately in series The amplifier has a configuration in which an amplifier AMP 1 having a fixed gain is connected to the last stage, and amplifies the I signal and outputs the amplified signal to the baseband circuit 300. Similarly, the high-gain amplifier 220B includes a plurality of low-pass filters LPF 21, LPF 22, LPF 23, LPF 24 and gain control amplifiers: PGA 21, PGA 22, The PGA 23 is alternately connected in series, and the amplifier AMP2 having a fixed gain is connected to the last stage. The amplifier AMP2 amplifies the Q signal and outputs it to the baseband circuit 300.

The offset cancel circuit 213 is provided in correspondence with each of the gain control amplifiers PGA11 to PGA23, and is an AD conversion circuit (ADC) for converting the output potential difference between input terminals into a digital signal when the input terminals are short-circuited. And a D / A conversion circuit that generates an input offset voltage that sets the DC offset of the output of the corresponding gain control amplifier PGA1 1 to 23 to “0” based on the conversion result of these A / D conversion circuits, and gives it to the differential input. (DAC), and a control circuit that controls the AD conversion circuit (ADC) and DA conversion circuit (DAC) to perform offset cancellation.

The transmission circuit TXC includes an oscillation circuit (IFVCO) 230 that generates an oscillation signal φ IF having an intermediate frequency such as 64 OMHz, and divides the oscillation signal φ IF generated by the oscillation circuit 230 by 1Z4. A frequency dividing circuit 231 for generating a signal such as 160 MHz; and a phase shifting frequency dividing circuit for further dividing the signal divided by the frequency dividing circuit 231 and generating quadrature signals 90 ° out of phase with each other. 232, a modulation circuit 233a, 233b for modulating the generated quadrature signal with an I signal and a Q signal supplied from the baseband circuit 300, an adder 234 for synthesizing the modulated signal, A transmission oscillation circuit (TXVCO) 240 that generates a transmission signal ΦΤΧ of a frequency, a feedpack signal obtained by extracting a transmission signal から output from the transmission oscillation circuit (TXVCO) 240 with a power brush or the like, and a high-frequency oscillation circuit ( RFVCO) 250 Oscillation signal generated by the signal < RF 'And a signal having a frequency corresponding to the frequency difference between the offset mixer 236 and the output of the offset mixer 236 and the signal TXIF synthesized by the adder 234. 237a and a digital phase comparator 237b for detecting the phase difference, and a loop filter 238 for generating a voltage corresponding to the output of the phase detection circuits 237a and 237b.

Note that the resistance and capacitance of the loop filter 238 are external elements. To the external terminal of the high-frequency IC of the embodiment. The transmission oscillation circuit (TXVC O) 240 generates the GSM 850 and GMS 900 transmission signal generation circuit 240 a, and the DCS 180 0 and PCS 190 0 transmission signal. Oscillation circuit to generate 240 b. The reason for providing two oscillation circuits in this way is that the transmission oscillation circuit has a wider variable frequency range than the high-frequency oscillation circuit 250 and the intermediate frequency oscillation circuit 230. This is because it is not easy to design circuits that can be powerful.

The reason why the analog phase comparator 237a and the digital phase comparator 237b are provided is to speed up the pull-in operation at the start of the operation of the PLL circuit. Specifically, at the start of transmission, the phase is first compared by the digital phase comparator 237, and then switched to the analog phase comparator 237a, so that the phase loop can be quickly closed. Is to be.

Further, on the chip of the high-frequency IC 200 of this embodiment, a control circuit 260 for controlling the entire chip, and an RF PLL circuit that constitutes an RF PLL circuit together with the high-frequency oscillation circuit (RFVCO) 250 Synthesizer 261, IF synthesizer 262 that constitutes an IF PLL circuit together with the intermediate frequency oscillation circuit (IFVCO) 230, and reference signals for these synthesizers 261 and 262 a reference oscillator (VCXO) 264 which generates a clock signal "i> r _e f is provided. Each of the synthesizers 26 1 and 26 2 includes a phase comparison circuit, a charge pump, a loop filter, and the like.

In addition, since the reference oscillation signal (i ^ ref is required to have high frequency accuracy, an external crystal oscillator is connected to the reference oscillation circuit 264. As the reference oscillation signal φι · _Θ £, Frequencies such as 26ΜΗ or 13 選択 are selected because quartz oscillators with such frequencies are relatively inexpensive.

In FIG. 1, blocks with fractions such as 1/2 and 1Z4 are frequency divider circuits, respectively, and a buffer circuit is denoted by BFF. SW1, SW2, and SW3 are connected in GSM mode for transmitting and receiving in accordance with GSM and DC SZP CS mode for transmitting and receiving in accordance with DCS or PCS. This switch switches the state and selects the frequency division ratio of the transmitted signal.

SW4 is a switch that is turned on and off so as to supply the I and Q signals from the baseband circuit 300 to the modulation mixers 233a and 233b during transmission. These switches SW1 to SW4 are controlled by a signal from the control circuit 260. The control circuit 260 is provided with a control register CRG. The register CRG is set based on a signal from the baseband circuit 300. More specifically, a clock signal CLK for synchronization, a data signal SDATA, and a load enable signal LEN as a control signal are supplied from the baseband circuit 300 to the high-frequency IC 200. When the load enable signal LEN is asserted to a valid level, the 260 sequentially captures the data signal SDATA transmitted from the baseband circuit 300 in synchronization with the clock signal CLK and sets it in the control register CRG. I do. Although not particularly limited, the data signal SDATA is transmitted serially. The base band circuit 300 includes a microprocessor and the like.

The control register CRG includes, but is not limited to, a control bit for starting the VCO frequency measurement in the high-frequency oscillation circuit (RFVCO) 250 and the intermediate frequency oscillation circuit (IF VCO) 230, a reception mode, and a transmission mode. There are provided bit fields for specifying modes such as mode, idle mode, and warm-up mode. Here, the idle mode is a mode in which only a small part of the circuit, such as a standby mode, operates and at least most circuits including the oscillation circuit are stopped, and the warm-up mode is a PLL circuit immediately before transmission or reception. This is a mode for starting up.

In this embodiment, a transmission PLL circuit that performs frequency conversion by a phase detection circuit 237a, 237b, a loop filter 238, a transmission oscillation circuit (TXVCO) 240a, 240b, and an offset mixer 236 (TXPLL) is configured. In the multi-band wireless communication system of the present embodiment, for example, the control circuit 260 responds to a channel using the frequency RF of the oscillation signal of the high-frequency oscillation circuit 250 at the time of transmission / reception according to a command from the base span circuit 300. Change In addition, by switching the switch SW2 according to the GSM mode or the DCS / PCS mode, the frequency of the signal supplied to the offset mixer 236 is changed, thereby switching the transmission frequency.

Table 1 shows the oscillation circuit for intermediate frequency (IFVCO) 230, the oscillation circuit for transmission (TXVCO) 240, and the oscillation circuit for high frequency (RFVCO) 250 in the quad-band high-frequency IC of this embodiment. An example of setting the frequency of the oscillation signal 0 ^, φΤΧ, «i» RF is shown below.

【table 1】

As shown in Table 1, in this embodiment, the oscillation frequency of the intermediate frequency oscillation circuit (IFVC O) 230 is 640 MHz in any of the GSM, DCS, and PCS. This is set, and this is frequency-divided into 1Z8 by the frequency dividing circuit 2 31 and the phase shifting frequency dividing circuit 2 32 to generate a carrier wave (TXIF) of 8 MHZ and modulation is performed.

On the other hand, the oscillation frequency of the high-frequency oscillation circuit (RFVCO) 250 is set to different values in the reception mode and the transmission mode. The oscillation frequency f RF of the high-frequency oscillator (RFVCO) 250 is, for example, 36 16 to 37 16 MHz for GSM 850 in the transmission mode, and 3 8 40 to 3 for GSM 900 in the transmission mode. It is set to 980 MHz, and for DCS, it is set to 3610 to 3730 MHz, and for PCS, it is set to 386 MHz to 380 MHz. In the case of, the frequency is divided by 1/4. In the case of DCS and PCS, the frequency is divided by 1 and offset as 0RF. Supplied to mixer 236.

The offset mixer 236 outputs a signal corresponding to the frequency difference (f RF '-f TX) between the frequency of this << i »RF and the transmission oscillation signal ΦΤΧ from the transmission oscillation circuit 130, and the frequency of this difference signal The transmission PLL (TXP LL) operates so that the frequency matches the frequency of the modulation signal TXIF. In other words, the TXVCO 240 is controlled to oscillate at a frequency corresponding to the difference between the frequency (f RFZ ^ :) of the oscillation signal RF, from the RFVCO 250 and the frequency (f TX) of the modulation signal TXIF. This is the transmission operation in a so-called offset PLL system.

FIG. 2 shows a specific example of a PLL circuit having a frequency measurement function of VCO and a function of correcting the frequency characteristic of VCO based on the measurement result.

In FIG. 2, 250 is a high-frequency oscillation circuit (RFVCO), 12 is a variable frequency divider that divides the oscillation signal φΚΡ of the scale VCO 250, 13 is a reference oscillation signal from the reference oscillation circuit 2 64 The fixed frequency divider divides ref to 1 Z 65.14 is a voltage divider that compares the phases of the signals divided by the variable frequency divider 12 and the fixed frequency divider 13 to increase the voltage according to the phase difference. A phase comparator that outputs DOW, 15 is a charge pump, and 16 is a loop filter.The capacitive element of the loop filter 16 is charged up by the charge pump 15 and is output as the control voltage Vc of the RFVCO 250. A PLL loop in which 250 oscillates at a predetermined frequency is configured. The capacitance and the resistance constituting the loop filter 16 are connected as external elements.

As shown in FIG. 2, the PLL circuit of this embodiment provides a voltage Vc from the charge pump 15 between the charge pump 15 and the loop filter 16 at the time of frequency measurement or PLL pull-in. Instead, a switch SW0 that can supply a predetermined DC voltage VDC to the loop filter 16 and a DC voltage source 17 that generates a DC voltage VDC applied to the charge pump 15 are provided. Also, a storage circuit 18 including a register for storing the value counted by the variable frequency dividing circuit 12, a frequency value stored in the storage circuit 18 and a setting externally set in the counter 22. Compare the values N8 to N0 and A5, A with the RFVCO 250 pan switching signal A use band determination circuit 19 for generating VB3 to VB0 is provided. The use band determination circuit 19 may be configured as a part of the control circuit 260. A switch SWO capable of supplying a DC voltage VDC for measurement may be provided between the loop filter 16 and the RFVCO 250.

At the time of frequency measurement, the DC voltage VDC supplied by the switch SW0 may be any voltage value within the effective variable range of the control voltage Vc. In this embodiment, the upper limit (Vcp-max) of the variable range of the control voltage Vc is selected. During frequency measurement, the DC voltage VDC remains the same even when the band is switched. The switch SW0, the variable frequency dividing circuit 12, the memory circuit 18, and the band determining circuit 19 are controlled by the control circuit 260. The variable frequency divider 12 and the fixed frequency divider 13, the phase comparator 14, the charge pump 15, the storage circuit 18, and the band determination circuit 19 use the RF synthesizer 26 1 shown in FIG. Be composed.

The RFVCO 250 is composed of, for example, an oscillation circuit shown in FIG. 3 using an LC resonance circuit, for example. In the RFVCO 250 shown in FIG. 3, a plurality of capacitance elements C ll, C 12 to C 41 and C 42 constituting an LC resonance circuit are provided in parallel via switch elements SW 11 to SW 14, respectively. By selectively turning on the switch elements SW11 to SW14 with the above-described band switching signals VB3 to VB0, the oscillation frequency is switched stepwise by switching the value of C of the connected capacitive element, that is, the LC resonance circuit. It is configured to be able to.

More specifically, the RFVCO 250 includes a pair of bipolar transistors Q 1, Q 2 whose bases and collectors are cross-coupled via capacitors C 1, C 2 of a DC cut, and the transistors Q 1, Q 1, A constant current source Ic connected between the common emitter of Q2 and the ground point GND, and inductors (coils) connected between the collectors of the transistors Q1 and Q2 and the power supply voltage terminal Vcc, respectively. LI and L2, and Paris-cap diodes Dv1 and Dv2 as variable capacitance elements connected in series between the collector terminals of the transistors Ql and Q2. The control value Vc changes the capacitance value of this paricap diode, and the oscillation frequency is continuously changed. If it is desired to widen the frequency range in which the VCO should increase the power, it is necessary to change only the capacitance value of the parasitic diode due to the control voltage Vc. As shown by the broken line A in FIG. The steepness increases, and the sensitivity of the VCO, that is, the ratio (A f ZAV c) between the amount of change in frequency and the amount of change in control voltage increases, and the noise becomes weaker. In other words, even a slight noise on the control voltage Vc greatly changes the oscillation frequency fRF of VCO.

Therefore, in the RFVCO 250 of this embodiment, a plurality of capacitance elements constituting the LC resonance circuit are provided in parallel, and the capacitance elements used by the band switching signals VB3 to VB0 are switched to set the value of C to 16 levels, for example. By changing it, oscillation is controlled according to multiple Vc-fRF characteristic lines, as shown by the solid line in Fig. 4. In addition, in this embodiment, since the storage circuit 18 and the use band determination circuit 19 are provided, the adjustment work of frequency adjustment performed in the conventional PLL circuit becomes unnecessary.

That is, in the conventional PLL circuit, for example, when configuring a VCO having a plurality of Vc-fRF characteristic lines as shown in Fig. 4, the VCO is operated to measure the frequency, and each of the plurality of Vc-fRF characteristics is measured. The frequency was adjusted so that the line had a predetermined initial value and a predetermined slope. On the other hand, in the PLL circuit of this embodiment, the switch SW0 is switched in advance, a predetermined DC voltage VDC is applied to the RFVCO 250, the frequency in each band is measured, and stored in the storage circuit 18; When using, the setting values N8 to NO and A5, A4 according to the designated band given from the outside to the counter 22 are compared with the measured values stored in the storage circuit 18 and the designation is made. The RFVCO is selected so that the frequency range of the band can be improved by selecting only one of the 16 (16) Vc-f RF characteristic lines as shown in Fig. 4 and performing oscillation control according to that characteristic line. (Capacitance element switching).

According to such a method, the power range is set slightly wider than the frequency range in which the power is to be adjusted in advance by considering the variation, and the 16 Vc-fRF characteristic lines are adjacent to each other as shown in Fig. 4. Little by little (preferably half by one) If the RFV CO is designed to overlap several ranges, there will always be characteristic lines that can cover the specified frequency range. Therefore, it is only necessary to select the one corresponding to each designated band based on the actual characteristics separated by the measurement, and it is not necessary to adjust the frequency, and the switching state of the band to be used and the RF VCO must be determined in advance. There is no need to make one-to-one correspondence.

The variable frequency dividing circuit 12 includes a prescaler 21 for dividing the frequency of the oscillation signal of the RFVC0250, a modulo counter 22 including a first counter 22N and a second counter 22A for further dividing the signal divided by the prescaler 21. It is composed of

The method of frequency division by the prescaler 21 and the modulo counter 22 is a known technique. The prescaler 21 is configured to be able to perform two types of frequency divisions having different frequency division ratios, such as 1/64 frequency division and 1Z65 frequency division, and is switched by the count end signal of the second counter 22A. . The first counter 22N and the second counter 22A are programmable counters. The first counter 22N uses a desired frequency (the oscillation frequency fRF of the VCO to be obtained as an output) as a reference oscillation signal φι · β: Τ The integer part when dividing by the frequency fref ′ of the prescaler 21 and the first division ratio (64 in the embodiment) of the prescaler 21, and the remainder (MOD) are set in the second counter 22A. When the set value is counted, the counting ends and the set value is counted again.

Specifically, for example, when the frequency fref 'of the reference oscillation signal ref' is 400 kHz and the oscillation frequency fRF of the desired VCO is 378.6 MHz, it is assumed that 37 899.6 ÷ 0.4. 64 Since the value of the second counter 22N is “148”, the value N set to the second counter 22A is “2”. When the prescaler 21 and the modulo counter 22 operate with such a value set, the prescaler 21 first divides the frequency by 1/64, and the output is counted by the second counter 22A to the set value of `` 2 ''. Then, a count end signal MC is output from the second counter 22A, and the operation of the prescaler 21 is switched by this signal MC, and the second counter 22A counts the set value “2”. Until the prescaler 21 operates at 1/65 division.

By performing such an operation, the modulo counter 22 can perform the frequency division not by the integer ratio but by the ratio having a decimal part. The PLL circuit of the embodiment is fed-packed so that the output frequency of the first counter 22 N matches the frequency f ref (400 kHz) of the reference oscillation signal ref ′, and the RFVCO 250 In the case of the above specific example, the value N set to the first counter 22 N is “1 4 8” and the value A set to the second counter 22 A is “2” because the oscillation is controlled. The oscillation frequency f RF of RFVCO 250 is

From f RF = (64 X 1 4 8 + 2) X f ref = 9474 X 400 = 3 789.600, it is 3 789.6 MHz.

Note that the first counter 22N and the second counter 22A are actually configured as binary counters, so the value N set to the first counter 22N and the second counter 22A are set. The value A is given in binary code. In this embodiment, although not particularly limited, the first counter 22N operates as a 9-bit counter and the second counter 22A operates as a 6-bit counter during PLL operation. The value to be set to is set by the 9-bit code N8 to N0, and the value to be set to the second counter 22A is set to be given by the 6-bit code A5 to A0.

Further, in this embodiment, the first counter 22N is configured to operate as an 11-bit counter when measuring the frequency. The RFVCO 250 is configured so that the oscillation frequency can be switched in 16 bands, that is, in 16 steps. The storage circuit 18 stores 16 frequencies to store the frequency measured for each of these 16 bands. the _c register REG 0～REG 1 5 of is provided, using Pando decision circuit 1 9, the register of the memory circuit 1 8: EG 0~REG 1 the value stored in the 5 and the first counter 2 2 N 9-bit code N8 to N0 set in the second counter 22 Compares the upper 2 bits A5 and A4 of the 6-bit code A5 to A0 set in the second counter 22 A 1 1-bit comparator And a 4-bit code VB 3 as a band switching signal for RF VCO 250 To VB0.

At the time of frequency measurement, the control circuit 260 generates and outputs switching signals VB3 to VB0 so as to sequentially select 16 bands for the RFVC0250. Further, when measuring the frequency, the control circuit 260 operates the first counter 22N as an 11-bit counter and counts the number of clocks in a long period such as, for example, four cycles instead of one cycle of the reference oscillation signal ref '. The first counter 22N is controlled to perform the operation. Further, the control circuit 260 stops the operation of the second counter 22A during the frequency measurement, and controls so that the division ratio of the prescaler 22 is not switched. Thus, at the time of frequency measurement, the prescaler 22 performs a 1/64 frequency division operation.

In this embodiment, the counting operation is performed not for one cycle of the reference oscillation signal Φ 発振 ′ but for four cycles at the time of frequency measurement in order to increase the measurement accuracy. That is, due to the provision of the prescaler 21, the maximum error that occurs in the counter 22N in the measurement of one cycle of つまり ref, that is, the counter 22N generates one pulse count error in the measurement of one cycle of ref ' If so, the error at that time is enlarged to 64 times, which is the dividing ratio of the prescaler 21. Therefore, when the reference oscillation signal f »ref 'is 400 kHz, the maximum error of the counter 22N is 25, 6 MHz (= 400 kHz X 64). The error is reduced by a factor of 4 to about 6.4 MHz. The 11-bit count value counted by the first counter 22N at the time of frequency measurement is stored in any register of the storage circuit 18. The stored value is compared with the setting code N8 to NO of the first counter 22N supplied from the outside in the use band determination circuit 19 while the upper 8 bits are regarded as an integer part during the PLL operation. You. The lower 2 bits of the value stored in the register of the storage circuit 18 are regarded as a decimal part, and the used band determination circuit 19 sets the setting codes A5 to A2 of the second counter 22A supplied from outside. It is compared with the upper two bits A5 and A4 of A0.

The use determination circuit 19 is composed of a comparator and an exclusive OR gate. The RFVCO 250 used band is determined based on the comparison between the stored values of the registers REG0 to REG15 of the storage circuit 18 and the setting codes N8 to N0 and A5 and A4. Are generated and supplied to the RF VCO 250. : In the case of a PLL circuit used in a communication system such as GSM, each of the FVCOs 250 is set to an interval such as 400 kHz according to the channel interval of the GSM.

Hereinafter, the procedure of frequency measurement and frequency characteristic correction by the control circuit 260 in the PLL circuit of this embodiment will be described. The frequency measurement of the RF VCO and the correction of the frequency characteristic based on the measurement result are performed, for example, every time a predetermined command is input from the baseband circuit 300 during the idle mode.

When the frequency measurement of the RFVCO 250 is started, the control circuit 260 first switches the switch SW0 to supply the DC voltage VDC to the loop filter 16. Then, it waits until the voltage Vc of the loop filter 16 is stabilized and the oscillation frequency of the RFVC0250 is stabilized. Next, the frequency division ratio of the prescaler 21 is fixed at 1Z64, and the first counter 22N is set to operate as an 11-bit counter. Then, referring to the pointer indicating the selected band, the codes VB3 to VB0 for selecting the band of the RFVCO 250 are output. Here, the band selected first is, for example, BAND 0 having the lowest frequency range.

Next, the first counter 22N performs a counting operation over four cycles of the reference oscillation signal <f »ref ', and stores the count value of the counter in any register of the storage circuit 18. The first stored register is the first register: REG 0. Then, determine whether the frequency measurement of all bands has been completed. If not completed, the value of the pointer indicating the selected band is added (+1), and the above operation is repeated.

After that, when the baseband circuit supplies a frequency setting value corresponding to the channel used in the stamped state with the start of transmission / reception, the band determination circuit 19 uses the registers REG of the storage circuit 18 based on the frequency setting value. From the comparison between the stored values of 0 to REG15 and the setting codes N8 to NO and A5 and A4, RFVC The use band of the O 250 is determined, and the band selection signals VB 3 to VB 0 are supplied to the RFVCO 250 to correct the frequency characteristics.

In the high-frequency IC 200 of the embodiment of FIG. 1, the intermediate frequency VCO (IFVCO) 230 and the transmission VCO (TXVCO) 240 are also provided with a frequency measurement function and a frequency characteristic correction function based on the measurement result. Moreover, by configuring these functions so that they can be executed by a common circuit, an increase in circuit size is suppressed. The configuration for realizing the frequency measurement function of the I FVCO 230 and the TXVCO 240 and the function of correcting the frequency characteristics based on the measurement results is almost the same as the frequency measurement function and the correction function of the RFVCO 250, and therefore, the description thereof is omitted. The present invention is also effective for a high-frequency IC provided with a frequency measurement function and a correction function only for the RFVC0250.

The high-frequency IC according to the present embodiment has a value stored in the storage circuit 18 for storing the frequency measurement value of each band of the RFVCO 250, an intermediate frequency VCO (IF VCO) 230 and a transmission ¥ 00 ( (TXVCO) The value stored in the storage circuit (not shown) that stores the frequency measurement value of each band of 240 is read out to the outside of the chip when the power is turned off, etc. The measurement value saved in the external memory can be returned to the storage circuit 18.

Is it for] ^ to enable reading of measured values from storage circuit 18 etc.? The RF synthesizer 26 1 that constitutes the 1 ^ 1 ^ circuit has a counter 31 that generates a signal to select the registers REG 0 to REG 15 of the storage circuit 18 in order, and a measurement value that is read in parallel. There is provided a serial Z-parallel conversion circuit 32 for converting data input from the outside into serial data and converting the data into parallel data and supplying the parallel data to the register. Although not particularly limited, the counter 31 and the serial Z-parallel conversion circuit 32 are operated by the reference oscillation signal φref generated by the reference oscillation circuit 264.

The high-frequency IC 200 according to the present embodiment is in an idle mode in which neither transmission nor reception is performed as in a standby mode. A plurality of operation modes are provided, such as an up mode, a reception mode in which a reception system circuit is operated to receive a signal, and a transmission mode in which a transmission system circuit is operated to transmit a signal. These modes are started by a command supplied from the baseband IC 300 to the control circuit 260 of the high-frequency IC 200. The command is composed of a code having a predetermined bit length such as 8 bits or 16 bits (hereinafter referred to as Word), and a plurality of types of command codes are prepared in advance.

FIG. 5 shows the high-frequency IC 200 of the present embodiment and the base band L S for controlling it.

The relationship between the semiconductor chip 400 and another semiconductor chip 400 having a memory for storing data read from the high frequency IC is shown. In the embodiment of FIG. 5, a single-chip microcomputer having an internal memory 410 as a semiconductor chip 400 that provides a stack memory that saves the value stored in the storage circuit 18 when power is turned off or the like A high-frequency IC 200 is provided with a terminal 272 for transmitting and receiving data to and from the CPU 400 by serial communication.

This data input / output terminal 2 7 2 is connected to another existing terminal (for example, a terminal for connecting an external resistor that generates a voltage to make the RF-PLL open at high speed: terminal “3 9” in Fig. 8). See). Reference numeral 500 denotes a switching regulator such as a DC-DC converter that generates a power supply voltage Vcc of the high-frequency IC 200. Reference numeral 281 denotes a crystal oscillator constituting a part of the reference oscillation circuit 264. An external circuit composed of elements such as a capacitive element, and 271, an external terminal for outputting the oscillation signal generated by the reference oscillation circuit 264 as an external synchronization clock.

In this embodiment, when the CPU 400 sends a command to the baseband IC 300 to turn off the power of the high-frequency IC 200, the baseband IC 300 The control circuit 260 of the IC 200 is instructed to output the measured value stored in the storage circuit 18 to the outside. Then, the control circuit

The counter 31 sequentially generates a register designation signal according to the control signal from 260 and reads data from the storage circuit 18, and the read data is converted to serial data by the serial Z-parallel conversion circuit 32 Output to external terminal 2 7 2 CPU 400 fetches the data internally via a serial port or the like, and stores it in internal memory (rewritable nonvolatile memory such as RAM or flash memory) 410 or the like. When the power of the high-frequency IC 200 is turned on again, the data saved in the external memory is restored to the original storage circuit 18 and the like.

In this embodiment, the power supply of the high-frequency IC 200 is turned off by a command from the CPU 400 to the baseband IC 300. Data from the CPU 400 and no command or control signal needs to be sent from the CPU 400 to the high-frequency IC 200. The same applies when returning data saved in external memory.

In the following, the procedure of measuring the frequency of each VCO in the wireless communication system of FIG. 5 using the high-frequency IC of this embodiment and correcting the frequency characteristics based on the measurement results (deciding the band to be used) and the high-frequency I c during standby, etc. The procedure of the power-off Z return operation will be described in detail with reference to FIG. 6 and FIG.

When the system is turned on, the regulator 500 is activated and the high frequency I C

Power supply to 200 is started. Baseband I C after power up

For example, when a command “Word 1” in which bits B 1 and B 0 are set to [00] is supplied from 300 to the high-frequency IC 200, the control circuit 260 controls the register inside the high-frequency IC 200. The high-frequency IC 200 enters the idle mode (command waiting state) (step Sl in FIG. 6, timing 1 in FIG. 7). In this idle mode, the oscillation operation of each VCO is stopped. Thereafter, when a command (Word 7) consisting of a predetermined bit code instructing the measurement of the VCO from the baseband IC 300 is received, the frequency measurement processing of each VCO in the high-frequency IC 200 is performed (Steps S2 and S2). Figure 7 Timing In the high-frequency IC 200 of the embodiment, the frequency measurement of each band of the RFVCO 250 and the IFVC0230 is performed in parallel. Is 16 bands and IF VCO 230 has 8 bands, so the frequency measurement of IF VCO 230 ends earlier (Fig. 7, timing t3). Then, the frequency of the TXVCO 240a for transmission is measured using the counter used for the frequency measurement of IFVC0230, and when that is completed, the frequency of the TXVCO 240b is measured (timing t4 in FIG. 7). As for IF VCO 230, the band to be used is immediately selected at the end of the frequency measurement.

After sending "Word 7", the baseband IC 300 sends "Word 5, 6" to command the initial setting after an appropriate time has elapsed. When the frequency measurement of the TXVCO 240b is completed, the completion is notified to the control circuit 260. After the measurement is completed, the control circuit 260 initializes the inside of the high-frequency IC 200 for transmission and reception operations (step S 3, Figure 7 timing t5).

When this initial setting is completed, the command “Word 1” including the value to be set in the counter 22 (frequency information of the used channel) is supplied from the baseband IC 300 to the high-frequency IC 200, and the control circuit 260 (Step S4, Figure 7 Timing 1: 6, t8) o This command also includes a bit [TR] to indicate transmission or reception. At the time of reception, based on the frequency information from the base band and the frequency measurement result stored in the storage circuit 18 (registers: EG0 to REG14): Select the use band of the RFV CO 250 and set the counter 22 Set the frequency value to. Then, the RF VCO 250 is oscillated to lock the receiving PLL loop.

At the time of transmission, based on the frequency information from the base band IC 300 and the frequency measurement results stored in the storage circuit 18 etc., the band to use the RFVCO 250 and TXVCO 240 is selected, and the frequency value is sent to the counter 22 etc. Set. Then, the RF VCO 250 and the IF VCO 230 are oscillated, and the RFPLL and the IFPLL loop are locked. Whether to use the TXVCO 240a or 240b is determined by a predetermined code included in a command supplied from the baseband IC 300. In addition, this warm-up In the mode, the control circuit 260 activates the offset cancel circuit 213 to perform the input DC offset cancel of the amplifier in the high gain width section 22OA, 220B.

After that, according to the bit [TR] in the command “Word 1,”, the baseband IC 300 instructs the high-frequency IC 200 to “Word 2” for instructing the reception operation or “Word 2” for instructing the transmission operation. When "Word 2" is received, the control circuit 260 enters the reception mode, and operates the reception circuit RXC to amplify and demodulate the received signal (step S5, timing in FIG. 7). t7) The control circuit 260 also controls switching of the switch SW1 and the like according to GSM or DCSZPCS.

On the other hand, when "Word 3" is received, the control circuit 260 enters the transmission mode and modulates and amplifies the transmission signal (step S6, timing t9 in FIG. 7). Further, the control circuit 260 turns on the transmission switching switch SW4, and also controls switching of the switch SW2 and the like according to GSM or DC S / PCS. The reception mode and the transmission mode are executed in time units called time slots (for example, 577 μsec).

Normally, the reception mode using “Word 1” and “Word 2” or the transmission mode using “Wordl” and “Word 3” is repeatedly executed. When the baseband IC 300 sends a command to turn off the power to the 200, the baseband IC 300 sends a command “Word 0” to command the data read / write to the high-frequency IC 200 (Fig. 7, timing t10 ).

The command “World 0” includes a bit [wr] indicating read / write of the measured value stored in the storage circuit 18 (registers REG 0 to REG 14) and the like. See bit [wr] of "Wo rd 0"

If it is [0], it shifts to the turn-off state. If it is [wr] force S [1], it reads out the measured value stored in the memory circuit 18 (registers REG0 to REG14) and outputs it from the external terminal 271 ( Steps S7, S8). The output data is The data is stored in the internal memory 410 of the CPU by the CPU 400.

Subsequently, the baseband IC 300 sends a signal P-0FF to the switching regulator 500 to stop its operation (step S9). Then, the regulator 500 stops operating, the supply of the power supply voltage V cc to the high frequency IC 200 is stopped, and the high frequency IC 200 shifts to a turn-off state (step S10). Note that even if the high-frequency IC 200 is turned off, the basebands IC 300 and CPU 400 continue to operate.

Thereafter, when the baseband IC 300 sends an operation start signal P-ON to the switching regulator 500 (step S11), the regulator 500 starts operation and supplies the power supply voltage Vcc to the high-frequency IC 200. And the high frequency IC 200 is turned on (step S12). Then, the baseband IC 300 sends a command “Word 0 ,,” including a bit [wr] indicating the data read / write Z to the high-frequency IC 200. In addition, the command “Word 0 ,, When [wr] is set to [1] to indicate "read", a command "Wo rd 1" for instructing transition to the idle mode is sent. On the other hand, when the bit [wr] is set to [0] indicating "write" by the command "Word 0", the command "Word 5, 6" for commanding the initial setting is continuously transmitted.

Then, the control circuit 260 refers to the bit [wr] of the command “Word 0” in step S 13 and if it is [0], saves the saved data read from the internal memory 410 by the CPU 400 to the external terminal 27. The data is read from 1 and stored in a memory circuit 18 (registers REG0 to REG14) and the like (step S14). Thereafter, the process proceeds to step S3, and receives the command "Word 5, 6" for instructing the initial setting from the baseband IC 300, and initializes the inside of the high-frequency IC 200 for the transmission / reception operation.

On the other hand, if the control circuit 260 of the high-frequency IC 200 determines that [wr] is [1] in step S13, it receives the following command "Word 1" and shifts to the idle mode of step S1. The frequency is measured in response to the command "Word 7" instructing the frequency measurement of each VCO (step S2). Usually a bit [wr] is set to [0], and it is considered that the data saved in the external memory is restored to the memory circuit 18 etc., but the presence of bit [wr] makes it possible to use The high-frequency IC 200 can measure the frequency of the VCO, thereby improving the reliability of the high-frequency IC 200.

In FIG. 6, when the power of the high-frequency IC 200 is turned on again, first, the data saved in the external memory is restored to the storage circuit 18 or the like (steps S14, S15). Although the initial setting (step S3) is performed after the initial setting, the return processing (steps S14 and S15) may be performed after the initial setting (step S3). In addition, return processing (steps S14 and S15) is performed during warm-up by referring to the bit [TR] indicating transmission or reception included in the command "Word 1" for instructing PLL activation. It is also possible to do it. In this case, only the measurement data corresponding to each VCO may be returned to the storage circuit 18 or the like in response to reception or transmission.

FIG. 8 shows another embodiment of the high frequency IC 200 to which the present invention is applied. In FIG. 8, the circuits and signals shown in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description will be omitted. Although not particularly limited, the high-frequency IC 200 of this embodiment is provided with a plurality of power pins (VCC) and a ground pin (GND) in order to prevent noise from flowing through the power line between the circuits. ing.

The high-frequency IC 200 of this embodiment uses the frequency measurement value stored in the storage circuit 18 (registers REG0 to EG14) or the like without using a dedicated external terminal (corresponding to the terminal 271 in FIG. 6). In addition, a terminal (terminal "32" in FIG. 8) provided for transmitting and receiving serial data S DATA of commands and the like to and from the baseband IC 300 is read out to the outside. Things.

Although not shown in FIG. 8, a signal line for transferring data is provided between the control circuit 260 and each of the storage circuits 18 of the PLL circuit. This signal line may be a single signal line, or may be a signal line group (bus) of a number corresponding to the bit number of the registers REG0 to REG15. In FIG. 8, reference numeral 281 denotes an external circuit including an element such as a crystal unit and a capacitor, which constitutes a part of the reference oscillation circuit 264. Reference numeral 282 denotes an IF nap-flop, which constitutes an IF PLL circuit together with the IF synthesizer 262.

If the baseband IC 300 has an internal memory, the data read from the high-frequency IC 200 may be stored in the internal memory 310 of the baseband IC 300, or the baseband IC 300 may store the internal memory. If not, or if the internal memory is available but the storage capacity is not sufficient, the data may be transferred to the CPU 400 via the basic IC 300 and stored in the CPU's internal memory 410. good. In a system in which the function of the baseband IC is performed by the CPU, the data read from the high-frequency IC200 when the high-frequency IC200 is turned off is stored in the internal memory 310 of the baseband IC300.

The frequency measurement value saved in the external memory when the power of the high-frequency IC 200 is turned off as described above is restored to the original storage circuit 18 and the like by the reverse route when the power of the high-frequency IC 200 is turned on again. . Only the data (measured value) route is different from that of the first embodiment, and the procedure for saving and restoring data is the same as the flow chart shown in FIG. Reading and writing of the measured frequency value stored in the storage circuit 18 (registers REG0 to REG15) are performed, for example, in the data storage field provided in the command “Word 0” indicating the data read / write Z. Can be put in the box.

In FIG. 8, the terminal “42” with the symbol DI VON is used to control whether the clock generated by the reference oscillation circuit 264 and output to the external terminal 27 1 is output as it is or is output by dividing by 1Z2. a terminal to which a signal or voltage to be applied, thereby making it possible to set the frequency of the clock output to the external terminal 27 to any of 1 3MH _Z or 26MH z.

FIG. 9 shows a third embodiment of a high-frequency IC 200 to which the present invention is applied. In FIG. 9, the same circuits and signals as the circuits and signals shown in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted. The high-frequency IC 200 of this embodiment includes a storage circuit such as a storage circuit 18 (registers REG0 to REG15) storing data to be protected when the power is turned off, a reference oscillation circuit 264, and other circuits. When The power line and the power terminal are separated.

Accordingly, in the communication system using the high-frequency IC 200, in addition to the first regulator 500 that supplies the power supply voltage V cc1 for the storage circuit, the storage circuit And a second regulator 510 for supplying the power supply voltage V cc 2 to other circuits. The power supply voltage Vcc1 generated by the first regulator 500 for the storage circuit is supplied to the baseband Ic300. When it is desired to reduce the power consumption during standby or the like, an off signal P-OFF is given only from the baseband IC 300 to the second regulator 5110, and the second regulator 510 operates. Stop and stop supply of power supply voltage Vcc2.

In this embodiment, since the power supply voltage of the storage circuit 18 and the like is supplied even when the power of the chip is turned off and is backed up, it is necessary to save the frequency measurement value stored in the storage circuit to the outside of the chip when the power is turned off. There is no. Therefore, a counter 31 for generating a signal for sequentially reading data from the storage circuit 18, a serial / parallel conversion circuit 32, and an external terminal 272 for inputting / outputting data are not required.

Further, the high-frequency IC 200 of this embodiment is supplied with the same power supply voltage V cc 1 as that of the circuit to be backed up, such as the storage circuit 18, to the reference oscillation circuit 264. When the power supply is turned off, a clock signal is generated and output from an external terminal 271 as an operation clock of an external chip. Therefore, by using the clock (13 MHz or 26 MHz) output from the external terminal 27 1 as the operating clock of the baseband IC 300 or CPU 400, the baseband IC 3 There is an advantage that there is no need to provide a circuit for generating the operation results of the CPU 400 and the CPU 400.

FIG. 10 shows the frequency measurement procedure of each VCO in the wireless communication system using the high-frequency IC of the embodiment of FIG. The procedure of power-off of high-frequency IC and Z return operation is shown. The procedure of FIG. 10 is for measuring the frequency of each VCO and measuring the high frequency in the wireless communication system using the high-frequency IC of the first embodiment shown in FIG. It is almost the same as the procedure of the power supply cutoff / return operation of the wave IC.

The difference between the procedure of FIG. 10 and the procedure of FIG. 6 is that the step of reading data stored in the storage circuit 18 (registers REG0 to REG15) immediately before the power of the high-frequency IC is turned off S8 Steps S14 and S15 to restore saved data from external memory to storage circuit 18 (registers REG0 to REG15) after power-cycle of high-frequency IC In step 9, only the regulator 5 10 is turned off, and then in step S 11 of turning on the power again, the regulator 5 10 is turned on. In this embodiment, the determination of [wr] in step S7 can be omitted.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor.

For example, in the first embodiment, the terminal 272 for reading data stored in the storage circuit 18 and the like and for writing from the outside is provided, but this terminal is used only for reading data. It may be configured as possible. In this case, writing of the save data to the storage circuit 18 or the like can be performed, for example, by using the serial data SDATA, the clock CLK, and the control signal LE from the baseband IC 300. Even if the terminal 272 is a high-frequency IC 200 configured so that only data can be read, there is an advantage that the read data can be used to analyze the characteristics of the built-in VCO.

Further, in the above-described embodiment, the high-frequency IC in which the three VCOs of the reception VCO, the transmission VCO, and the intermediate frequency VCO are formed on one semiconductor chip together with the modulation / demodulation circuit has been described. One VCO can be applied to a high-frequency IC formed on one semiconductor chip together with a modulation / demodulation circuit.

Further, in the above embodiment, the storage circuit 18 is provided with 16 registers REG0 to REG15 for storing the frequency measured for each of the 16 bands of the RF VCO 250. , 15 registers REG 0 ~ RE G14 is provided to measure and store only 15 bands B and 0 to B and 14, and if the measured value corresponding to the external frequency setting value does not exist in registers REG0 to REG14, It may be configured such that the 16th band B and 15 is automatically selected. The same applies to IF VCO and TXVCO. By reducing the number of registers in this way, the chip size can be reduced, and the time required to read and write measured values can be reduced. Industrial applicability

In the above description, the wireless communication of the mobile phone capable of performing communication by the four communication methods of GSM850 and GSM900, DCS1800, and PCS1900, which are the fields of application, which is mainly based on the invention made by the present inventors. Although the description has been given of the case where the present invention is applied to a high-frequency IC used in a system, the present invention is not limited to this, and a communication system called EDGE having a QPSK modulation mode in which amplitude modulation is added to phase modulation in GSM. The present invention can also be applied to a high-frequency IC used for a mobile phone capable of supporting the above, a CDMA type mobile phone, a wireless communication system called a wireless LAN network, and a high-frequency IC constituting the same.

Claims

The scope of the claims

1. A communication semiconductor integrated circuit in which at least one oscillation circuit among a reception oscillation circuit, a transmission oscillation circuit, and an intermediate frequency oscillation circuit is formed on one semiconductor chip together with a modulation / demodulation circuit,

The oscillation circuit formed on the semiconductor chip is configured to be operable in a plurality of frequency bands, a circuit for measuring an oscillation frequency of the oscillation circuit, a storage circuit for storing a measured value, and a storage circuit for storing the measured value. A circuit for comparing the measured value with an externally set value to determine a frequency band to be used by the oscillation circuit, so that data stored in the storage circuit can be read out to the outside. A communication semiconductor integrated circuit characterized in that:

2. The communication semiconductor integrated circuit according to claim 1, wherein the communication circuit is configured to be able to externally store data in the storage circuit.

3. The communication semiconductor integrated circuit according to claim 2, wherein a path for externally reading data stored in the storage circuit and a path for externally storing data in the storage circuit are the same.

4. A control circuit that decodes a command input from the outside and generates an internal control signal is provided, and the control circuit reads data stored in the storage circuit in response to a predetermined command input from the outside. 4. The communication semiconductor integrated circuit according to claim 1, wherein the communication semiconductor integrated circuit is configured to output to the outside.

5. The communication device according to claim 4, wherein the data stored in the storage circuit from the outside is configured to be input via the same path as the path to which the command is input. Semiconductor integrated circuit.

6. The communication semiconductor integrated circuit according to claim 1, further comprising a dedicated path for outputting data stored in the storage circuit to the outside.

7. A communication semiconductor integrated circuit according to any one of claims 1 to 6,

A base node circuit for extracting data from a reception signal down-compartmented to a desired frequency by the communication semiconductor integrated circuit and converting transmission data into I and Q signals;

A microprocessor that has an internal memory and controls the entire system; a voltage generation circuit that generates a power supply voltage of the communication semiconductor integrated circuit;

A wireless communication system comprising:

After the data stored in the storage circuit is output to the outside and saved in the internal memory of the microprocessor, the operation of the voltage generation circuit is stopped by a command from the base fold circuit or the microprocessor. A wireless communication system characterized by being constituted.

8. A communication semiconductor integrated circuit according to any one of claims 1 to 6,

A base-band circuit that includes an internal memory and extracts data from a received signal down-converted to a desired frequency by the communication semiconductor integrated circuit and converts transmission data into I and Q signals;

A microprocessor that controls the entire system;

A voltage generation circuit for generating a power supply voltage of the communication semiconductor integrated circuit, a wireless communication system including:

After the data stored in the storage circuit is output to the outside and saved in the internal memory of the base band circuit, the operation of the voltage generation circuit is stopped by a command from the base band circuit or the microprocessor. A wireless communication system characterized by being configured as described above.

9. In response to a command from the baseband circuit or microprocessor The transmission / reception operation is enabled after the voltage generation circuit is restarted and after the data saved in the internal memory is restored to the storage circuit. 7. The wireless communication system according to 7 or 8.

10. A communication semiconductor integrated circuit in which at least one of the reception oscillation circuit, the transmission oscillation circuit, and the intermediate frequency oscillation circuit is formed on one semiconductor chip together with the modulation / demodulation circuit,

The oscillation circuit formed on the semiconductor chip is configured to be operable in a plurality of frequency bands, a circuit for measuring an oscillation frequency of the oscillation circuit, a storage circuit for storing a measured value, and a storage circuit for storing the measured value. A circuit for comparing the measured value measured with an external set value to determine a frequency band used by the oscillation circuit, wherein a power supply line for supplying a power supply voltage to the storage circuit is a circuit other than the storage circuit. A communication semiconductor integrated circuit, which is separated from a power supply line for supplying a power supply voltage to the semiconductor integrated circuit.

11. A reference oscillation circuit for generating a reference oscillation signal and a clock generation circuit for generating and outputting a clock signal of a predetermined frequency based on the oscillation signal of the reference oscillation circuit, 10. The communication semiconductor integrated circuit according to claim 10, wherein the circuit and the clock generation circuit are configured to operate with a power supply voltage supplied by the same power supply line as the storage circuit.

12. The communication semiconductor integrated circuit according to claim 10 or 11,

A base band circuit for extracting data from a received signal down-compartmented to a desired frequency by the communication semiconductor integrated circuit and converting transmission data into I and Q signals;

A microprocessor that controls the entire system;

A first voltage generation circuit that generates a power supply voltage of the storage circuit;

A second voltage generation circuit for generating a power supply voltage of a circuit other than the storage circuit, a wireless communication system including: The second voltage generation circuit is configured to be able to stop operation by a command from the base band circuit or the microprocessor even during operation of the first voltage generation circuit. system.