WO2004025659A1 - Programming a phase-change material memory - Google Patents
Programming a phase-change material memory Download PDFInfo
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- WO2004025659A1 WO2004025659A1 PCT/US2002/028811 US0228811W WO2004025659A1 WO 2004025659 A1 WO2004025659 A1 WO 2004025659A1 US 0228811 W US0228811 W US 0228811W WO 2004025659 A1 WO2004025659 A1 WO 2004025659A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0078—Write using current through the cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
Definitions
- This invention is related to techniques for programming a structural phase-change material solid state memory device such as those that use a chalcogenide material which can be programmed into different resistivity states to store data.
- phase-change memory devices that use a structural phase-change material as the data storage mechanism (referred to here simply as 'phase-change memories') offer significant advantages in both cost and performance over conventional charge storage based memories.
- the phase-change memory is made of an array of constituent cells where each cell has some structural phase-change material to store the cell's data.
- This material may be, for instance, a chalcogenide alloy that exhibits a reversible structural phase change from amorphous to crystalline.
- a small volume of the chalcogenide alloy is integrated into a circuit that allows the cell to act as a fast switching programmable resistor.
- This programmable resistor can exhibit greater than 40 times dynamic range of resistivity between the crystalline state (low resistivity) and the amorphous state (high resistivity), and is also capable of exhibiting multiple, intermediate states that allow multi-bit storage in each cell.
- the data stored in the cell is read by measuring the cell's resistance.
- the chalcogenide alloy cell is also nonvolatile.
- a conventional technique for programming a phase-change memory cell is to apply a rectangular pulse of current (having a constant magnitude) to the cell, at a voltage greater than a switching threshold for the phase-change material, which leaves the material in the reset state (amorphous and high resistivity). This may be followed by the application of a subsequent rectangular pulse, also at a voltage greater than the switching threshold, which changes the material to a set state (crystalline and low resistivity).
- the reset pulse has a higher magnitude of current than the set pulse so that the temperature of the phase change material is raised to T m , the amorphizing temperature, before the material is rapidly cooled down and is left in the amorphous state.
- the material can be heated back up to an optimum temperature T opt , wliich is lower than T m .
- the temperature T 0pt is that which allows the material in the cell to be crystallized in a relatively short time interval and yielding a relatively low resistance. Ideally, this could be accomplished by having the magnitude of the set pulse be smaller than that of the reset pulse to prevent the phase-change material from reaching the amorphizing temperature, but large enough to cause the material to reach T opt .
- phase change memories Because of fabrication process and material variations in phase change memories, the actual temperature of the phase-change material in the cells of a manufactured device varies significantly from cell to cell, for a given programming current/voltage level obtained by a set pulse. This variation can cause the material in one or more cells of a device to inadvertently reach T m during application of the conventional rectangular set pulse, and thereby cause those cells to erroneously remain in the reset state rather than change to the set state. To avoid this problem, conventional programming techniques use a rectangular set pulse (applied to every cell in the device) that has a reduced magnitude, as shown in Fig. 1.
- the magnitude of the set current is sufficiently low, in view of the expected variation in cell temperature at that magnitude, to guarantee that no cell in the device reaches Tm while the set pulse is applied to it.
- This solution may slow down the programming of the memory device, since a longer rectangular set pulse is needed due to the less than optimal temperatures being generated by the lower magnitude of the set pulse.
- many cells in the memory are subjected to significantly less than the optimum crystallization temperature which reduces the dynamic range in resistivity between the set and reset states in those cells.
- Fig. 1 shows a conventional sequence of pulses for programming a phase-change memory.
- Fig. 2 illustrates a sequence of phase-change memory programming pulses including a set sweep, according to an embodiment of the invention.
- Fig. 3 illustrates a plot of crystallization time in a phase-change material memory cell as a function of the temperature of the phase-change material.
- Fig. 4 depicts another sequence of phase-change memory programming pulses, including a set sweep.
- Fig. 5 shows the variation in the temperature of phase-change material in a memory cell versus time, while a set sweep according to an embodiment of the invention is being applied to the cell.
- Fig. 6 illustrates a plot of memory cell resistance versus programming current level, for a particular phase-change memory device.
- Fig. 7 depicts a plot of memory cell resistance versus programming current for a large population of memory cells, showing an example of a relatively wide variation in the population.
- Fig. 8 illustrates a block diagram of a phase-change material memory device, including waveshaping and driving circuitry that are designed to provide the voltage and current levels needed to program the constituent cells of the device.
- Fig. 9 depicts a block diagram of an embodiment of a portable application of a phase- change memory that incorporates the programming process.
- the set pulse for programming a phase- change memory is shaped to be generally triangular, rather than rectangular.
- a pulse is also referred to here as a 'set sweep'.
- the magnitude of the set pulse current can be increased, so that the phase-change material in all cells of a device can reach temperatures of at least T opt during the set pulse yet still change to the set state, due to the downward slope in the trailing portion of the pulse.
- Better crystallization takes place in the memory, despite fabrication process and material variations. With better crystallization, the resistivity differences between the set and reset states are more pronounced. This means that the tolerance for variations in the memory has increased, therefore lowering manufacturing costs by allowing greater yields from the fabrication and testing flows.
- the memory device may reach temperatures as high as T m when the magnitude of the triangular set pulse is greater than the conventional set current magnitude, the triangular shaped pulse has a decaying or downward sloping trailing portion such that even those cells that reach T m will have a chance to cool down to and crystallize at or near T 0pt -
- the decay during the trailing portion is slow enough to ensure that those cells spend the minimum required time interval at approximately T opt , to yield better crystallization even in those cells.
- the time of the current transition from its maximum value to its minimum value for the slope of the trailing portion may need to be longer than for devices that are expected to show relatively small variations.
- Fig. 2 illustrates a sequence of phase-change memory programming pulses, according to an embodiment of the invention.
- a first pulse 204 is applied to a constituent cell of a phase-change memory.
- This pulse may be of any conventional type.
- a typical shape is rectangular as shown, with a constant, current magnitude. Rectangular pulses are relatively easy to generate, using only a single switching transistor (not shown).
- the first pulse 204 may, as mentioned above in the background, be a reset or amorphizing pulse having a magnitude I reset that is sufficiently high such that the phase-change material in the cell reaches T m , the amorphizing temperature of the material.
- the current magnitude may be different so long as the first pulse 204 leaves the cell in a predefined state.
- the pulse width of the first pulse 204 is also selected to be long enough to achieve the predefined state.
- Application of the first pulse 204 is followed by a second pulse 208 which is generally triangular in shape, as shown.
- the second pulse 208 has a leading portion that peaks at the magnitude or maximum, I 2 ( ma ⁇ ), and a trailing portion that decays to a minimum value I 2(m i n ).
- the leading portion may have a much greater slope than the trailing portion.
- the shape of the second pulse 208 can be selected, in view of fabrication process and material variations across the phase-change materials and the circuitry in the constituent cells of the memory device, such that every cell of the memory device changes from the first state to a second, different state if the second pulse 208 were applied to each of them.
- the first and second states may be the reset and set states mentioned above in the background.
- the shaping of the second pulse 208 involves setting a number of parameters that include the maximum and minimum values, and the decay rate/pulse width, in view of the structure and type of phase-change material used, as well as the operating thermal environment of the memory device.
- I 2(max) and I 2(m i n) may assume a wide range of values.
- I 2(max) may be substantially greater than I reS et , or it may be substantially smaller so long as the pulse width is long enough to insure that the phase-change materials in the cells to which the pulse is to be applied crystallize.
- Crystallization is a function of both the temperature and the amount of time the material spends at that temperature. This may be explained by Fig. 3 which illustrates an exemplary plot of crystallization time (in a phase-change material memory cell) as a function of the temperature of the phase-change material. The plot shows that at temperatures below T opt , the material needs a longer time interval to crystallize.
- a set pulse should have a current magnitude that yields T op t , for as many cells as possible in a memory device, so as to provide the shortest set programming interval, T mln , as well the lowest set state resistance for those cells.
- the level of I 2 ( m m) may also vary over a wide range of values, including as low as zero.
- an upper bound on I 2(m i n ) for a set pulse may be one wliich insures that the temperature of the phase-change material in all cells to which the pulse will be applied is below T m at the end of the pulse (when I 2(m i n) has been reached).
- Fig. 4 depicts another sequence of phase-change memory programming pulses.
- the second pulse (set sweep) 308 in this example although still referred to as generally triangular, has a relatively short intermediate portion between the leading and trailing portions, wherein the intermediate portion has essentially zero slope relative to the leading and trailing portions.
- the trailing portion in Fig. 4 has a nonlinear slope.
- the decay rate in the trailing portion may be of a wide range, including polynomial, logarithmic, and exponential, so long as the trailing portions cause all relevant cells in the device to sweep through a rapid crystallization temperature interval.
- Fig. 5 The effect of the triangular set pulse on cell temperatures in a phase-change memory are illustrated in the exemplary plot of Fig. 5. It can be seen that even with large variation in temperature (depicted by the shaded band) for a given magnitude and decay rate in the triangular set pulse, the entire memory device is swept through a rapid crystallization temperature interval, so that optimum, i.e. lowest, set resistance is obtained for all cells in the device. This is also illustrated in Fig. 6 which is a plot of memory cell resistance versus set current for a particular phase-change memory device. The resistance is plotted as the memory cell, beginning in the reset state, responds to the various levels of programming current.
- the sequence for applying the various levels of programming current is indicated by the arrows, starting from the left and then moving to the right and then coming back to the left.
- the lowest set resistance may be obtained at a value of set current just prior to its rapid rise towards the reset level.
- the triangular nature of the set pulse allows this lowest set resistance to be 'locked in' as the set sweep pulse sweeps back down from its peak value. Assuring the lowest set resistance for each cell in the memory device provides superior margin for memory read operations, higher manufacturing yields, as well as better product reliability.
- Fig. 7 depicts a plot of memory cell resistance versus programming current for a large population of memory cells in a memory device.
- This device suffers from a relatively wide variation in the population of its constituent memory cells.
- the application (to each cell) of the conventional rectangular pulse of magnitude I r eset will work.
- the conventional programming technique of applying the same rectangular set pulse would be unable to return every cell in the device to the set state. That's because to do so the current magnitude needs to be at least as high as I conv But at that magnitude some of the cells, namely those falling within region 704, will stay at the reset state when the pulse has abruptly ended.
- Fig. 8 what is shown is a block diagram of a phase-change material memory device, including waveshaping and driving circuitry that are designed to provide the voltage and current levels needed to program the constituent cells of the device.
- the device features an array of memory cells 604 where each cell 604 can be accessed by a unique pair of vertical conductors 614 and horizontal conductors 610.
- the horizontal conductors 610 allow a control signal from timing logic 620 to be provided to each cell 604 to close or open a solid state switch therein.
- This solid state switch is in series with a volume of the phase-change material whose other terminal is connected to a power supply or power return node. Current is thus sourced or sunk through the phase-change material when the switch is closed.
- This programming current is provided through the vertical conductors 614.
- the sourcing or sinking of the programming current is performed by either the read circuitry 618 or waveshaping and driving circuitry 608, depending upon whether a write or read operation is being performed.
- the read circuitry 618 may be entirely conventional.
- the waveshaping and driving circuitry 608 will be designed so as to provide the voltage and current levels that are needed to program the cells 604 according to the first and second pulses described above, wherein the second pulse has a generally triangular shape.
- the waveshaping circuitry can be implemented using conventional analog waveshaping circuits such as integrator/ramp circuits, exponential and logarithmic circuits, as well as others.
- the shaped pulses are then driven by conventional fanout circuitry so that each cell 604 that is connected to a vertical conductor 614 is assured of receiving the desired levels of current and voltage to achieve the set sweep.
- Timing logic 620 provides digital control signals to the waveshaping and driving circuitry 608 and the read circuitry 618 so that the latter circuits either measure the resistance of the memory cell 604 (read operation) or provide the reset and set pulses at the correct timing and to the selected memory cell 604. Accesses to the cell 604 may be in random fashion where each cell can be accessed individually, or it may be orchestrated according to a row by row basis, depending upon the higher level requirements of the memory system.
- the memory device depicted in Fig. 8 may be built using a wide range of different fabrication processes, including a slightly modified version of a conventional complimentary metal oxide semiconductor (CMOS) logic fabrication process.
- CMOS complimentary metal oxide semiconductor
- Fig. 9 illustrates a block diagram of a portable application 904 of the phase-change memory programming process described above.
- a phase-change memory 908 is operated according to an embodiment of the programming process described above.
- the phase- change memory 908 may include one or more integrated circuit dies where each die has a memory array that is programmed according to the various embodiments of the programming techniques described above in Figs. 1-8. These IC dies may be separate, stand alone memory devices that are arranged in modules such as conventional dynamic random access memory (DRAM) modules, or they may be integrated with other on-chip functionalities, hi the latter embodiments, the phase-change memory 908 may be part of an I/O processor or a microcontroller.
- DRAM dynamic random access memory
- the application 904 may be for instance a portable notebook computer, a digital still and or video camera, a personal digital assistant, or a mobile (cellular) hand-held telephone unit.
- an electronic system includes a processor 910 that uses the phase-change memory 908 as program memory to store code and data for its execution.
- the phase-change memory 908 may be used as a mass storage device for nonvolatile storage of code and data.
- the portable application 904 communicates with other devices, such as a personal computer or a network of computers via an I/O interface 914.
- This I/O interface 914 may provide access to a computer peripheral bus, a high speed digital communication transmission line, or an antenna for unguided transmissions. Communications between the processor and the phase-change memory 908 and between the processor and the I/O interface 914 may be accomplished using conventional computer bus architectures.
- the above-described components of the portable application 904 are powered by a battery 918 via a power supply bus 916. Since the application 904 is normally battery powered, its functional components including the phase-change memory 908 should be designed to provide the desired performance at low power consumption levels. In addition, due to the restricted size of portable applications, the various components shown in Fig. 9 including the phase-change memory 908 should provide a relatively high density of functionality. Of course, there are other non-portable applications for the phase-change memory 908 that are not shown. These include, for instance, large network servers or other computing devices which may benefit from a non- volatile memory device such as the phase- change memory.
- the phase-change material may be Ge2Sb2Te5.
- An exemplary pulse may have a peak current magnitude of Ireset, where Ireset is sufficiently high to allow the cells of the array to be programmed into the reset state.
- the exemplary pulse may also have a falling edge that decreases from Ireset to zero current in about 200 nsec.
- phase-change material memory programming technique referred to as a set sweep
- set sweep various embodiment of a phase-change material memory programming technique
- the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims.
- the phase-change material may be a chalcogenide alloy or other suitable structural phase-change material that acts as a programmable resistor.
- the specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
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Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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AU2002326868A AU2002326868A1 (en) | 2002-09-11 | 2002-09-11 | Programming a phase-change material memory |
GB0501972A GB2407707A (en) | 2002-09-11 | 2002-09-11 | Programming a phase-change material memory |
PCT/US2002/028811 WO2004025659A1 (en) | 2002-09-11 | 2002-09-11 | Programming a phase-change material memory |
JP2004535362A JP4094006B2 (en) | 2002-09-11 | 2002-09-11 | How to program phase change material memory |
CNB028295781A CN100449647C (en) | 2002-09-11 | 2002-09-11 | Programming a phase-change material memory |
DE10297786T DE10297786B4 (en) | 2002-09-11 | 2002-09-11 | Programming a phase change material memory |
EP02761617.6A EP1537584B1 (en) | 2002-09-11 | 2002-09-11 | Programming a phase-change material memory |
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PCT/US2002/028811 WO2004025659A1 (en) | 2002-09-11 | 2002-09-11 | Programming a phase-change material memory |
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WO2004025659A1 true WO2004025659A1 (en) | 2004-03-25 |
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PCT/US2002/028811 WO2004025659A1 (en) | 2002-09-11 | 2002-09-11 | Programming a phase-change material memory |
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EP (1) | EP1537584B1 (en) |
JP (1) | JP4094006B2 (en) |
CN (1) | CN100449647C (en) |
AU (1) | AU2002326868A1 (en) |
DE (1) | DE10297786B4 (en) |
GB (1) | GB2407707A (en) |
WO (1) | WO2004025659A1 (en) |
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JP2006004614A (en) * | 2004-06-19 | 2006-01-05 | Samsung Electronics Co Ltd | Method of programming, phase change memory device, and driving circuit of phase change memory write operation |
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US7457146B2 (en) | 2006-06-19 | 2008-11-25 | Qimonda North America Corp. | Memory cell programmed using a temperature controlled set pulse |
JP2008310960A (en) | 2002-12-13 | 2008-12-25 | Ovonyx Inc | Method for programming phase-change substance |
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- 2002-09-11 JP JP2004535362A patent/JP4094006B2/en not_active Expired - Fee Related
- 2002-09-11 DE DE10297786T patent/DE10297786B4/en not_active Expired - Lifetime
- 2002-09-11 WO PCT/US2002/028811 patent/WO2004025659A1/en active Application Filing
- 2002-09-11 GB GB0501972A patent/GB2407707A/en not_active Withdrawn
- 2002-09-11 EP EP02761617.6A patent/EP1537584B1/en not_active Expired - Lifetime
- 2002-09-11 AU AU2002326868A patent/AU2002326868A1/en not_active Abandoned
- 2002-09-11 CN CNB028295781A patent/CN100449647C/en not_active Expired - Lifetime
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JP2008310960A (en) | 2002-12-13 | 2008-12-25 | Ovonyx Inc | Method for programming phase-change substance |
JP2006004614A (en) * | 2004-06-19 | 2006-01-05 | Samsung Electronics Co Ltd | Method of programming, phase change memory device, and driving circuit of phase change memory write operation |
US8335103B2 (en) | 2004-09-30 | 2012-12-18 | Nxp B.V. | Integrated circuit with memory cells comprising a programmable resistor and method for addressing memory cells comprising a programmable resistor |
US7911822B2 (en) | 2004-10-21 | 2011-03-22 | Nxp B.V. | Integrated circuit with phase-change memory cells and method for addressing phase-change memory cells |
US7800940B2 (en) | 2005-02-08 | 2010-09-21 | Elpida Memory, Inc. | Semiconductor memory device and writing method thereof |
KR100699837B1 (en) | 2005-04-04 | 2007-03-27 | 삼성전자주식회사 | Semiconductor memory device and programming method thereof |
US7993962B2 (en) | 2005-11-15 | 2011-08-09 | Macronix International Co., Ltd. | I-shaped phase change memory cell |
US8110430B2 (en) | 2005-11-21 | 2012-02-07 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7580278B2 (en) | 2005-12-09 | 2009-08-25 | Samsung Electronics Co., Ltd. | Variable resistance memory device |
US7457146B2 (en) | 2006-06-19 | 2008-11-25 | Qimonda North America Corp. | Memory cell programmed using a temperature controlled set pulse |
US8178405B2 (en) | 2006-12-28 | 2012-05-15 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US7920415B2 (en) | 2007-02-05 | 2011-04-05 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US7701759B2 (en) | 2007-02-05 | 2010-04-20 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US7978509B2 (en) | 2007-08-02 | 2011-07-12 | Macronix International Co., Ltd. | Phase change memory with dual word lines and source lines and method of operating same |
WO2009062799A1 (en) * | 2007-11-13 | 2009-05-22 | Igor Anatolievitch Popov | An exchange for telecommunications, a switch and switch board therefore, and a method of switching |
US8064247B2 (en) | 2009-01-14 | 2011-11-22 | Macronix International Co., Ltd. | Rewritable memory device based on segregation/re-absorption |
US7968876B2 (en) | 2009-05-22 | 2011-06-28 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US8624236B2 (en) | 2009-05-22 | 2014-01-07 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
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US8809829B2 (en) | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8406033B2 (en) | 2009-06-22 | 2013-03-26 | Macronix International Co., Ltd. | Memory device and method for sensing and fixing margin cells |
US8238149B2 (en) | 2009-06-25 | 2012-08-07 | Macronix International Co., Ltd. | Methods and apparatus for reducing defect bits in phase change memory |
US8363463B2 (en) | 2009-06-25 | 2013-01-29 | Macronix International Co., Ltd. | Phase change memory having one or more non-constant doping profiles |
US8779408B2 (en) | 2009-07-15 | 2014-07-15 | Macronix International Co., Ltd. | Phase change memory cell structure |
US8228721B2 (en) | 2009-07-15 | 2012-07-24 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US8198619B2 (en) | 2009-07-15 | 2012-06-12 | Macronix International Co., Ltd. | Phase change memory cell structure |
US8110822B2 (en) | 2009-07-15 | 2012-02-07 | Macronix International Co., Ltd. | Thermal protect PCRAM structure and methods for making |
US7894254B2 (en) | 2009-07-15 | 2011-02-22 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US8064248B2 (en) | 2009-09-17 | 2011-11-22 | Macronix International Co., Ltd. | 2T2R-1T1R mix mode phase change memory array |
US8178387B2 (en) | 2009-10-23 | 2012-05-15 | Macronix International Co., Ltd. | Methods for reducing recrystallization time for a phase change material |
US8853047B2 (en) | 2010-05-12 | 2014-10-07 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8729521B2 (en) | 2010-05-12 | 2014-05-20 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8310864B2 (en) | 2010-06-15 | 2012-11-13 | Macronix International Co., Ltd. | Self-aligned bit line under word line memory array |
US8395935B2 (en) | 2010-10-06 | 2013-03-12 | Macronix International Co., Ltd. | Cross-point self-aligned reduced cell size phase change memory |
US8497705B2 (en) | 2010-11-09 | 2013-07-30 | Macronix International Co., Ltd. | Phase change device for interconnection of programmable logic device |
US8467238B2 (en) | 2010-11-15 | 2013-06-18 | Macronix International Co., Ltd. | Dynamic pulse operation for phase change memory |
US10388720B2 (en) | 2011-03-16 | 2019-08-20 | Macronix International Co., Ltd. | Capacitor with 3D NAND memory |
US9716137B1 (en) | 2011-05-24 | 2017-07-25 | Macronix International Co., Ltd. | 3D capacitor with 3D memory |
US9336878B2 (en) | 2014-06-18 | 2016-05-10 | Macronix International Co., Ltd. | Method and apparatus for healing phase change memory devices |
US9620210B2 (en) | 2014-06-18 | 2017-04-11 | Macronix International Co., Ltd. | Method and apparatus for healing phase change memory devices |
US9159412B1 (en) | 2014-07-15 | 2015-10-13 | Macronix International Co., Ltd. | Staggered write and verify for phase change memory |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
US10593403B2 (en) | 2016-02-23 | 2020-03-17 | Hewlett Packard Enterprise Development Lp | Memristive arrays with a waveform generation device |
Also Published As
Publication number | Publication date |
---|---|
JP2005536828A (en) | 2005-12-02 |
DE10297786T5 (en) | 2005-08-18 |
AU2002326868A1 (en) | 2004-04-30 |
GB2407707A (en) | 2005-05-04 |
CN1669091A (en) | 2005-09-14 |
DE10297786B4 (en) | 2012-11-08 |
JP4094006B2 (en) | 2008-06-04 |
EP1537584A1 (en) | 2005-06-08 |
GB0501972D0 (en) | 2005-03-09 |
CN100449647C (en) | 2009-01-07 |
EP1537584B1 (en) | 2017-10-25 |
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