WO2004023552A1 - Multichp semiconductor device, test method, and system board - Google Patents

Multichp semiconductor device, test method, and system board Download PDF

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Publication number
WO2004023552A1
WO2004023552A1 PCT/JP2002/009052 JP0209052W WO2004023552A1 WO 2004023552 A1 WO2004023552 A1 WO 2004023552A1 JP 0209052 W JP0209052 W JP 0209052W WO 2004023552 A1 WO2004023552 A1 WO 2004023552A1
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WO
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Patent type
Prior art keywords
wiring
chip
semiconductor
test
circuit
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PCT/JP2002/009052
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French (fr)
Japanese (ja)
Inventor
Masayuki Sato
Isao Shimizu
Kenichi Tonomura
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Renesas Technology Corp.
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318513Test of Multi-Chip-Moduls
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31723Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382Adaptable interconnections, e.g. for engineering changes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0287Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having slectively interconnectable sets of X-conductors and Y-conductors in different planes

Abstract

A multichip semiconductor device comprising a package case (100) capable of holding semiconductor chips, semiconductor chips (200) held by the package case, and an insulating board (110) provided with wirings (112, 113) electrically connected to the semiconductor chips and a cross point switch circuit (114) provided at cross points of the wiring and serving as wiring route switching means capable of interconnecting given wirings and made of a low-dielectric constant material joined to the package case.

Description

Substrate art for bright fine manual multi-chip semiconductor device and a test method and system

The present invention relates to a semiconductor device and its testing techniques including a plurality of semiconductor chips, for example, a plurality of semiconductor chips of the multichip module Contact Yopi plurality formed by sealed entry in the package is mounted on a single substrate system a technique effectively utilizes the available system board corresponds to. BACKGROUND

Recently, one CPU (central processing unit) on a semiconductor chip and a memory, the development of LSI called equipped with a system LSI including custom Murojikku has been actively conducted. On the other hand, semiconductor miniaturization technology is evolving every year, is the 0. 3 mu submicron technology established as m in recent years, while the current is 0. 1 m following study miniaturization technology is carried out is there. System LSI is developed is supported in such a semiconductor miniaturization techniques.

However, while increasing importance raw development of the insulating film of the MO S speeding viewpoint al high dielectric constant of the transistor as the semiconductor miniaturization is to suppress interference Noizu Ya signal by a coupling capacitance of the wiring is it is effective to have use of a low dielectric constant material as an insulating film between the wirings, it is becoming clear that the development of an insulating film having a low dielectric constant is also important. However, to form a high dielectric constant of the insulating film and the low dielectric constant insulating film on a single semiconductor chip is a process more difficult, large-scale and high-speed system LSI is an extension of current technology It came naturally also been found that there is a limit to the reduction.

Incidentally, as the low dielectric constant materials are known, such as epoxy resin or ceramic, a device conventionally referred to as a multi-chip module mounting a plurality of chips on a printed wiring substrate formed with the wiring on the insulating substrate made of such materials It has been known. In a multi-chip module, by the global wiring for connecting the chips formed on or in the substrate board of a low dielectric constant, the local wiring within the chip is formed on an insulating film having a high dielectric constant, the MOS transistor can be satisfied to reduce two requirements that the interference noise and the signal due to the coupling capacitance between the speed and wiring. Therefore, it is considered that a plurality of semiconductor chips to develop a multi-chip devices comprising the system enclosed in one package advances et be with future system LSI.

However, in the system including a plurality of semiconductor chips, in addition to the test of one single semiconductor chip is Ken查 whether operates normally, the system is normally in an assembled state in a system tests to check whether the operation is essential, it was revealed that there is a problem that increase in cost and an increase in the time required for testing by it can be expected. On the other hand, with the semiconductor integrated circuit is difficult to test the circuit between the chip in the back part you larger scale, when the chip with a built-in analog circuit providing a signal line for testing an analog circuit, the signal there is a problem that the characteristics of the circuit varies by line.

As the test technique of the semiconductor chip, in addition to the test by a device called a tester, ALPG in technology and in a chip called DFT (Design 'Four' Tesutapiriti) for testing by providing a scan path in the chip (Arugorizu Mick pattern. generator) technology called BIST that enables self-test (built 'in' self 'test) is known to provide a test circuit made of. Further, in recent years, it has been proposed technologies and to test on a wafer provided with a test circuit and wiring to disk Rise area of ​​the wafer, also a technique for testing constitute a test circuit on the board, such as aging board.

Further, a plurality of Suitsuchi elements on a wiring board is invention relates to a wiring board having a test structure was so performed to test the system and enables switching the routing arranged in a matrix (JP-A 7 _ 1 7 0 0 3 8 JP).

An object of the present invention is to provide a multi-chip device with less noise interference and signal due to a coupling capacitance of the wiring can be faster operation.

Another object of the present invention is to provide a multi-chip device testing method which can shorten the time required for the test.

Still another object of the present invention is to provide or configure a plurality of multi-chip devices having different system configurations, the substrate for electronic systems that can be used to test semiconductor chips.

For other objects and novel features to the a Rapi of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the Invention

To briefly explain the summary of typical inventions among the inventions disclosed in this specification, it is as follows.

That is, a plurality of semiconductor chips capable of holding a package case, the semiconductor chip held by the package case, intersections provided by any of the semiconductor chip and electrically connected to the wiring contact Yopi wiring by an insulating substrate made of a low dielectric material cross Boyne toss I Tutsi circuit of wirings as the wiring route switching means connectable is bonded to the package case is provided, in which so as to constitute a Maruchichi' Pudepaisu .

According to the above means, one semiconductor chip is capable of high-speed operation of the circuit it is possible to form the insulation Enmaku for insulating between wirings with a high dielectric constant material, between the semiconductor chips and the like low dielectric materials it is possible to connect wiring formed on a substrate made, it is possible to realize a small multi-chip device with noise interference and signal due to the coupling capacitance of the wiring.

Further, it preferably provided any for possible wiring path switching means connecting the wirings is provided, the wiring and that enables forming the interconnection and the other for example the test circuit of the normal on the substrate the substrate Accordingly, each semiconductor chip constituting the device it is possible to test independently, respectively it, for testing of the system is possible, it is possible to shorten the test can be facilitated test time . Further, constitute a test circuit using a semiconductor chip on the substrate, it becomes possible to test the other chips in the test circuit, it is possible to perform tests without using the tester advanced.

Another aspect of the present invention is the substrate having a distributed multiple wires and wiring wiring path switching unit can be connected to each other any wiring provided at the intersection of so as to intersect each other, the as Suitsuchi elements constituting the wiring path switching means, a pair of lead-shaped wire free ends are opposed to each other with a predetermined distance from each other, magnetic pieces provided on the tip or near the of the Li one de-like wiring consists of a, on whether at sweep rate Tutsi said magnetic piece having a magnetic pole, in which to use a device oFF state is configured to be set.

According to the above means, by setting the state of the switch element in the wiring intersection equipped with a different function or the number of semiconductor chips on a substrate, a highly versatile it can be constructed of different system board it can be realized. Also, to form the test circuit in the semiconductor chip on the substrate before building the system, to test the other semiconductor chip, it is possible to use as a test substrate of any of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a plan view showing an over embodiment of a package cases which constitute the multi-chip module according to the present invention.

Figure 2 is a rear view showing an embodiment of a cap combined board constituting a multi-chip module according to the present invention.

Figure 3 is an explanatory diagram showing an example of the internal structure of the substrate of FIG.

Figure 4 is a view to circuit diagram of one embodiment of a crosspoint sweep rate Tutsi circuit provided on the substrate of FIG.

Figure 5 is an enlarged sectional view showing a state where the assembled multi-chip module embodiment.

Figure 6 shows a specific example of a switch element which constitutes a suitable cross Poin toss switch circuit when the substrate is made of a low dielectric constant material, (A) is a front sectional view, (B) is a plan it is a cross-sectional view. Figure 7 shows a specific example of a switch element which constitutes the cross Boyne toss switch circuit suitable when the substrate is made of a semiconductor crystal, (A) is a positive 'side sectional view, (B) is a plan it is a cross-sectional view.

Figure 8 is a circuit diagram showing another configuration example of a suitable cross Boyne toss switch circuit when the substrate is a semiconductor crystal.

Figure 9 is a sectional view showing a specific example of the non-volatile storage element to be used as Suitsuchi elements constituting the crosspoint sweep rate Tutsi circuit of FIG.

Figure 1 0, Ru circuit diagram showing one example of a peripheral circuit for enabling writing of the connection information to the nonvolatile memory element constituting a crosspoint sweep rate Tutsi circuit of FIG.

Figure 1 1 shows another specific example of the switch elements constituting the crosspoint switch circuit suitable when the substrate is made of a low dielectric constant material, (A) is a front sectional view, (B) it is a plan sectional view. '

Figure 1 2 shows another specific example of the switch elements constituting the crosspoint switch circuit suitable when the substrate is made of a semiconductor crystal, (A) is a front sectional view, (B) it is a plan sectional view.

Figure 1 3 is turned on when the magnetic Suitsuchi elements constituting the cross Poin toss I Tutsi circuit of FIG. 3 is a switch element having the structure as shown in FIG. 1 1 and 1 2, the magnetizing device that allows off-state configuration it is a schematic diagram showing an example.

1 4, as an example of a suitable system by applying the multi-chip module of the present invention, a proc structure diagram showing an application system having an analog circuit.

Figure 1 5 is a Furochiya one preparative showing the procedure of the test method of the multi-chip module of Figure 1 according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

It will be described below with reference to preferred embodiments of the present invention with reference to the drawings.

FIG 1 Oyopi Figure 2 shows an embodiment of a multi-chip module according to the present invention. Incidentally, FIG. 1 Oyopi Figure 2 showing a state before assembling the module (with open case and cap).

In Figure 1, 1 0 0 recess of the synthetic resin, such as any material capable of holding a plurality of semiconductor chips are formed in a package case, substantially the same shape as the outer shape of the chip that holds for this package case 1 0 0 There is a plurality formed in a predetermined arrangement, the semiconductor chip 2 0 0 is accommodated in each recess. At this time, each chip Bonn loading pads such as another chip and terminals electrically recess of the package case 1 0 0 in the upward connection portion provided in order to connect (code 1 2 0 see in FIG. 5) It is housed in.

Although not particularly limited, in this embodiment, CPU (central processing unit) as an example of a semiconductor material chip 2 0 0 constituting the module 2 1 0 Ya static R AM (Random Access Memory) 2 2 0, dynamic R AM 2 3 0, custom logic chip 2 4 0, the user can configure any logic of FPGA (field 'programmable' gates such as user logic circuit constituting the logic functions required by the user array) 2 5 0 is shown. The semiconductor chip 2 0 0 constituting the module is not limited thereto, DSP (digital. Signal Processor) and D MA controller, AD conversion circuit, may be another chip such as DA conversion circuit.

The static R AM 2 2 0 and dynamic R AM 2 3 0 comprises a memory peripheral circuit of § address decoder or the like for selecting a memory cell corresponding to when Adore scan signal is applied. Furthermore, the dynamic R AM 2 3 0 comprises a refresh control circuit cyclically-option pseudo election as information charges in the memory cell even if the non-access time becomes long is not lost. Further, although not intended to be limited, the da Inamikku R AM 2 3 0, if there is a defective bit in the memory array of memory row or memory column including a defective bit for that spare memory row or spare so-called redundant circuit is provided respectively replaced with memory column.

Figure 2 shows a surface to be bonded to the package case 1 0 0 backside i.e. Figure 1 of the substrate 1 1 0 which also serves as a cap that is joined to the package case 1 0 0. This. 1 0 is formed of a semiconductor crystal such as a low dielectric constant material or silicon, such as epoxy resin or Ceramic. On the back surface of the substrate i 1 0, the package case

1 0 0 surface wiring 1 1 2 for connecting the bus 1 1 1 Ya chip that has been the semiconductor chip 2 0 0 electrically connected held to have been formed.

Further, the interlayer arbitrary substrate having a stacked structure of the substrate 1 1 0 Internal i.e. multiple insulator layers, internal wiring 1 1 3 arranged in a grid, each intersection of the internal wiring 1 1 3 provided with a vertical and horizontal or oblique direction any wirings can click port spot I cement sweep rate connects Tutsi circuit 1 1 4 of FIG is provided to the point.

Further, on the rear surface of the substrate 1 1 0, for electrical connections are contacted with the internal wiring 1 1 3 or to the package case 1 0 0 held semiconductor chip 2 0 0 pads or wirings of contactor door point 1 1 5 of that provided. Contactors DOO points 1 1 5 may be an electrode pad as the bonding pad may be a contact hole a signal is formed by Uni insulating film to expose the signal lines on the chip to be transmitted to be extracted to the outside.

As described above, in this embodiment, because wiring for connecting between each semiconductor chip are provided on the substrate 1 1 0 of a low dielectric constant material such as epoxy resin or Ceramic, forces between wire noise from wiring Ppuringu capacity is by small crosstalk to other distribution lines as possible out to suppress the occurrence of distortion due to the interference between the signals or transmitted. Moreover, the substrate 1 1 0, grid for having the internal wiring 1 1 3 and the cross Boyne toss I provided at each intersection of the internal wiring 1 1 3 Tutsi circuit 1 1 4, any one or more chips use can configure the test circuit for testing other chips, test chips constituting the module is so performed without using the tester by connexion highly functional thereto.

Further, since it is not necessary to provide a test circuit such as BIST the chip itself, it is possible to reduce the size of the chip constituting the module, it is possible to turn Mojiyu miniaturization Le. Further, in the module of Example, Kurosupoi Ntosuitsuchi circuit 1 1 4 can also child reconfigured as different systems function even set or Ranaru same hardware in the same semiconductor chip by resetting the is there. 2

8 Although not shown in FIG. 2, on the surface side of the substrate 1 1 0 is connected to the path 1 1 1, pad or lead terminals for connecting with external devices other than module (pins) It is provided. Besides pad or lead terminals it is connected to the bus 1 1 1, one of the pad or lead terminals for connecting external terminal and an external device directly semiconductor chip as provided on the surface side of the substrate 1 1 0 and it may be.

Enlarged view of the internal wiring 1 1 3 of the substrate 1 1 0 in FIG. 3, also in Figure 4 are examples of cross-point sweep rate Tutsi circuit 1 1 4 is shown provided at each intersection. In the embodiment of FIG. 3, although the cross point when to switch circuit 1 14 at the intersection of Te to base internal wirings 1 1 3 is provided, can also be Rukoto as provided in every or several intervals it is. The internal wiring 1 1 3 is constituted by a plurality of conductive layers by multilayer interconnection technique. 3, wires are indicated by broken lines 1 1 3 'is a wiring different conductive layers.

Crosspoint sweep rate Tutsi circuit 1 1 4, as shown in FIG. 4, the longitudinal direction of the signal line L y 1, L y 2 and the transverse direction of the signal lines LX 1, provided at the intersection of the L x 2, vertical side and Suitsuchi SW1 between possible connections away the signal line L y 1 and L y 2 countercurrent, the horizontal signal line LX 1 and Suitsuchi SW2 between possible connections away with LX 2, the longitudinal direction of the signal line L y 1 and the lateral Suitsuchi SW3 between possible connections away the signal line LX 1, the longitudinal direction of the signal line L y 1 and lateral scan between possible connections away the signal line LX 2 switch SW4 If, between the longitudinal direction of the signal line L y 2 and lateral Suitsuchi SW5 between possible connections away the signal line LX 2, the longitudinal direction of the signal line L y 2 and transverse to the signal line L x 1 consisting of a connection away from possible Suitsuchi SW6 Metropolitan.

In FIG. 4, reference numeral SX 1, SX 2, SX 3 ...... and SY 1, SY 2, SY 3 signal lines, shown in ......, the on of the respective switches SW1 to SW6, O off state control line for setting the signal line RRL that are arranged in a meandering to Nth set switch is oN switches SW1 to SW6, a release line for releasing the off-state. Figure 3 instead of constituting the circuit of six Suitsuchi SW1~SW6 shown cross Boyne toss I Tutsi circuit 1 14 Te to base 4 shown, in some intersections of Suitsuchi SW 1~SW6 the circuits having among SW 1 and SW2 only, or may be disposed a circuit having a SW3~SW6 of Suitsuchi SW 1~SW6 the intersection of the next. Similarly, cross Boyne toss I Tutsi circuit consisting of other combinations of the switch SW 1~SW6 also contemplated.

FIG. 5 shows a cross-sectional structure of a multi-chip module embodiment is shown. 5, those same reference numerals as in FIG. 2 is attached represent the same members or sites.

Although not particularly limited, in FIG. 5, the internal wiring 1 1 3 4 layers are provided on the substrate 1 1 0. Of these lines, L xl, L x 2 and SXI, the SX 2, SX 3 ...... the same wiring layer and L yl, L y 2 and SY 1, SY 2, SY 3 ...... the other It is made of the same wiring layer, wiring for further connecting the release line RRL and the chip is composed of a different wiring layer.

5, reference numeral 1 2 0 recess for accommodating the semiconductor chip 2 0 0 provided in the package case 1 0 0, 1 3 0 pads provided on the semiconductor chip 2 0 0, 1 1 6 insulator layer of a low dielectric constant material such as an epoxy resin constituting the substrate 1 1 0, 1 1 7 conductive to connect the pad 1 3 0 of the internal wiring 1 1 3 and the semiconductor chip 2 0 0 provided on a substrate it is a via composed of the body. Roh Tsu and de 1 3 0 and bi § 1 1 6 is connected with a low-melting-point metal or a conductive adhesive such as solder balls. Oite in recent years, room temperature bonding technique for connecting the bonding the surface to by bonding without using a mirror-finished by adhesive and has been studied, and the connection using such techniques as Nau line it may be.

Figure 6 shows a specific example of Suitsuchi SW. 1 to SW6 which the substrate 1 1 0 constitutes a low dielectric constant when the preferred cross Boyne toss I which is composed of a material Tutsi circuit 1 1 4 such as an epoxy resin. (A) is the same front cross-sectional view and FIG. 5 of FIG. 6, (B) is a planar, cross-sectional view.

Internal In this embodiment, as shown in FIG. 6, the empty portion 1 1 8 is formed in the insulating layer 1 1 6 a to 1 1 in 6 c constituting the substrate, the pair of the air unit 1 1 in 8 protruding wires 1 1 4 a, 1 1 4 b from the right and left, the tip is facing away slightly. Its to and their internal wiring 1 1 4 a, 1 14 b tip surface opposing ferromagnetic layer] VIG 1, MG 2 are formed respectively. The structure illustrated in FIG. 6 is a structure suitable for forming the substrate by laminating the insulating layer and the conductor layer by a known board processing techniques. Specifically, the internal wiring 1 1 4 a and 1 14 b are made multilayered in each separate conductor layer. May be ferromagnetic layers MG 1, MG 2 is also formed inside the wiring 1 1 4 a, 1 1 4 b as well as lamination technology, it is also possible to form a magnetic body.

Figure 7 shows a specific example of Suitsuchi SW1~SW6 which constitute preferred Kurosupo Intosuitsuchi circuit 1 1 4 when the substrate 1 1 0 is composed of semiconductor crystal. (A) is the same front cross-sectional view and FIG. 5 of FIG. 7, (B) is a plan sectional view.

In this embodiment, as shown in FIG. 7, the empty portion 1 1 8 is formed in the insulating layer 1 1 6 a, 1 1 in 6 b, the air unit 1 pair of internal wiring 1 8 1 1 4 a, 1 14 b is protruded from left to right, the tip is facing away slightly. Then, their internal wiring 1 1 4 a, 1 1 4 b tip facing surface of the ferromagnetic layer MG 1, MG 2 are formed respectively. The structure shown in FIG. 7 is a structure suitable for more formed by combining the deposition and etching of the insulator layer and conductive layer on the crystal substrate by a known semiconductor manufacturing technique.

Specifically, the insulating layer 1 1 6 a, 1 1 6 b is deposited in such a known CVD method (chemical vapor deposition) and plasma CVD method on a substrate made of a semiconductor crystal, the internal wiring 1 1 4 a and 1 1 4 b are formed by removing the excess portion of the conductive layer deposited by a CVD method or a sputtering method such as a known plasma Etsu quenching method Ya reactive I on etching. Ferromagnetic layer MG 1, MG 2 also can be formed by the internal wiring 1 1 4 a, 1 14 b as well as deposition and etching, strong at the tip of the internal wire 1 1 4 a and 1 1 4 b MG 1, MG 2 layers may be shape formed the by coating a magnetic substance. Semiconductor crystal may be a single crystal, it may be a polycrystalline. And each Suitsuchi SW1~SW6 constituting the crosspoint sweep rate Tutsi circuit of FIG. 4, when using the switch having the structure as shown in FIG. 6 or FIG. 7, or in the control line SX 1, SX 2, SX 3 one Contact Yopi SY 1, SY 2, and selects one or in SY 3 by flowing a current in a predetermined orientation, internal wiring 1 1 4 a located at the intersection of the selected control line it is arranged so as to be able to magnetize the 1 1 4 b ferromagnetic layers of the tip of the MG 1, MG 2.

That is, magnetic either of FIGS control lines are shown in 4 SX 1, SX 2, SX 3 ...... and SY 1, SY 2, SY 3 ...... is illustrated in Figure 6 Oyopi 7 are to pass through the vicinity of Suitsuchi, both ferromagnetic layers constructively with each other in ferromagnetic layer MG 1 'MG 2 near magnetic field to be generated when the flow of the predetermined direction of the current in the control lines MG 1 , it is possible to magnetize the MG 2 in a predetermined orientation, ferromagnetic layer MG 1 even when the current flows only in one of the control lines passing near, MG 2 are disposed so as not to be magnetized.

Thus, it is possible to magnetize the internal wiring 1 1 4 a, 1 1 4 b of the tip ferromagnetic layer MG 1 of, MG 2 located at the intersection of the selected control line. The ferromagnetic layer MG 1, MG 2 has been magnetized switch, the internal wiring 1 1 4 a a ferromagnetic layer MG 1 and MG 2 are each other adsorbed, 1 1 4 b to become conductive on-state Ru is set. Further, it is possible to demagnetize the ferromagnetic layer MG 1, MG 2 all magnetic Suitsuchi by generating an alternating magnetic field by passing an AC current to the release line RR L. Accordingly, sweep rate pitch of ferromagnetic layers MG 1, MG 2 is demagnetized internal wiring 1 1 4 a and 1 14 b is returned to the OFF state back to the original state by elasticity.

Thus, since the cross Boyne toss I Tutsi circuit of this embodiment can be or block Connect the between desired signal line, in the circuit of Figure 3, test a connection between any of the chip pins after performing, it is possible to change the connection to easily change the system, such as re-reconfigured to the desired system.

Figure 8 illustrates a preferred another example of cross-point switch circuit 1 1 4 when the substrate 1 1 0 is composed of a semiconductor crystal such as silicon. This example is one using a nonvolatile memory element comprising a MO S FET having a floating gate used as Suitsuchi elements constituting the crosspoint sweep rate Tutsi circuit 1 1 4 flash memory or the like, shown in Figure 4 It is configured as replaced by that of the switch SW1 to SW 6 in two nonvolatile memory elements in series form, respectively.

Specifically, the nonvolatile memory element F 1 1 series form between the vertical signal line L y 1 and L y 2, F 1 2 is provided, horizontal signal lines LX 1 and LX 2 nonvolatile memory element F of the series configuration between the non-volatile memory element F 2 1 serial form, F 2 2 is also a longitudinal direction of the signal line L y 1 and the transverse direction of the signal lines LX 1 between the 3 1, F 3 2, the nonvolatile memory element F 4 1 serial form between the vertical signal line L y 1 and the transverse direction of the signal line L x 2, F 4 2, vertical signal lines L y 2 and series configuration between the lateral direction of the signal line L x 2 nonvolatile memory element F 5 1, F 5 2, in the longitudinal direction signal line L y 2 and the transverse direction of the signal line L x 1 nonvolatile memory element F 6 1 serial form, F 6 2 are provided respectively between.

In FIG. 8, SX. 1 to SX 4 and SY. 1 to SY 4 is the nonvolatile memory element F ll, F 1 2; F 2 1, F 2 2; ...... F 6 1, F 6 2 ON, OFF a control line for controlling the state control line SX. 1 to SX 4 is in parallel to the wiring LX 1, LX 2, and the control line SY 1~SY 4 is arranged in parallel with the wiring L y 1, L y 2 ing. Their to, the series configuration a pair one of the control gate terminal of the nonvolatile memory element is connected to any one of the horizontal direction of the control line SX. 1 to SX 4, the other control gate terminal of the vertical It is connected to one of control lines SY 1~SY 4.

In the embodiment of FIG. 8, element between the two non-volatile memory element is provided in principle in each signal line in series form each between each signal line may be one. Are we two nonvolatile memory elements in series form, either by a single respective only the selection level of the control line SX 1~SX 4 and SY 1~SY 4 that are arranged perpendicular to each other one pair of in order to be able to specify a non-volatile memory element. If, when trying'll select one of the non-volatile memory element so as to respectively provide only one nonvolatile memory element between each signal line, another control for each non-volatile storage element of each intersection it becomes necessary to provide a line, the number of control lines becomes very large.

In contrast, as in the embodiment, the case in which the two non-volatile storage element in series form, if Shiteyare to one each only selected level of the control line SX 1~SX4 and SY 1~SY4, it is possible to select only one set of non-volatile storage elements in each intersection may be to cross-point sweep rate Tutsi circuit the intersection in the same column Contact Yopi same row provided by a control line in common, the total control the number of lines can Succoth reduced significantly. Incidentally, in advance by performing writing by selecting only one set of non-volatile storage elements in each intersection as described above (e.g., operation of lowering the threshold voltage), in a normal state of all the control lines LX, the L y If set to a selection level (high level) and Ya Ru, previously only memory element subjected to writing is rendered conductive, thereby connecting the corresponding signal line signal communicatively.

By the way, any of the storage devices in the control line SX 1~SX4 and SY 1 to SY 4 to and orthogonal configuration a connection switching means between the signal line by using the two nonvolatile memory elements in series form, as described above when configured to select, properly be same row devising a plurality of oddly the write memory ie writing such performed the connection information to the storage element in the same column (injection of charges into the floating gate) There is a need to. For example, assuming that the F 41 control line SX 2 storage element F 3 whose gate is connected to one in FIG. 8 is formed in the same Ueru region, In this case, the control line SX 1 Uweru Upon application of a write voltage between, F 3 2 and F 4 simultaneously write to 1 will be made. As a method of writing one for all memory elements while avoiding such a simultaneous write, it can be considered the following manner. First, as shown in FIG. 8, © Le region WL 1, WL 2 is formed in two rows in the vertical direction of the control lines SY 1, SY 2 and parallel become as board surface, horizontal among the storage elements of the pair direction storage element having a gate terminal connected to the control line SX (e.g. F 3 2 and F 4 1) above separate © formed vertically - previously formed on Le region WL 1, WL 2 . However, previously formed in the different horizontal storage elements in the same column being connected to the control line is identical © Le region formed in the vertical direction. Specifically, for example, F 3 2 and F 22 and F 6 1 are formed on Ueru WL 1, F 4 1 and F 1 1 and F 5 2 is previously formed on Ueru WL 2.

Then, through any one of the control lines SX and Ueru area WL of the high voltage is applied between the gate and Weru storage elements F ij in a position in which they intersect, for example, the threshold by performing writing in tunnel phenomenon is the value voltage to a low state. In this way, by applying any one of horizontal control lines SX and any one selectively write voltage in the vertical direction of Ueru region WL, only one storage element positioned in the intersection thereof it is possible to perform the writing.

Then, as described above using the storage device the threshold voltage is low, the memory element by applying, for example, a high level voltage using a control line (SX system) to the gate terminal of the memory element the causes turned on to flow the drain current is given a potential difference between the signal line and applying a write voltage and connected so to the same control gate of a storage element in a pair are connected line (SY system) it allows to the threshold voltage to the low state by injecting hot carrier generated in Chiyane Le in the floating gate. Thus, the storage device paired also in the same manner as the other can'll lower the threshold voltage.

Incidentally, according to the above method, it is not possible to perform writing by the drain current to the storage element constituting a memory element and a pair of voltage application is threshold voltage is not performed is to remain high between Getueru, I want to connect in scheme of the present embodiment to the control line perpendicular to a pair of non-volatile storage elements between the signal line to set only the conductive state, the memory element pairs is the same state that is one of a low threshold voltage der Re if other even low threshold voltage, since one of the other if the high threshold voltage is a high threshold voltage, there is no problem even if adopted write system as described above. Further, in the above embodiment, a case has been described to lower the threshold voltage of a set of non-volatile storage elements of the six sets of nonvolatile storage elements selectively, a set of non- volatile storage elements raising the threshold voltage of, it is also possible to only the raised element is configured to be conductive under normal operating conditions. Further, by selectively changing the threshold voltage of the six sets of two pairs or three pairs of non-volatile storage elements, or branches the one signal to multiple signal lines, a plurality of signals in the opposite wired logic configured to transmit the sum as convex was signals it is also possible.

Figure 9 shows an example of a nonvolatile memory element F 1 1 to F 6 2 structure constituting the cross Boyne toss I Tutsi circuit 1 1 4.

9, reference numeral S UB is substrate made of a semiconductor crystal such as silicon, WL is different © Le regions of the substrate and the conductive type or impurity concentration formed on the substrate surface, FL insulating on the substrate S UB film (not off Rote Ing gate comprising a conductive layer formed over the substantially), CG is a control gate that is connected the control line SX, the SY. Between the floating gate Ichito FG and the control one Rugate CG are also separated by an insulating film (not shown). Although not particularly limited, in this embodiment, the conductivity type of the substrate SUB is N-type, also conductivity type Uweru region WL is a P-type. S RC, DRN source region Oyopi drain of MO S FET ing a high-concentration diffusion layer formed on the surface of the surface contact Yopi Ueru area WL of both sides of the board S UB floating gate FG in a self-alignment technique it is a region.

The 1 0 shows an example of a peripheral circuit for enabling writing connection information into the nonvolatile Symbol 憶素Ko F 1 1 to F 6 2 constituting the cross Boyne toss I Tutsi circuit 1 1 4.

Figure 1 As shown in 0, in this embodiment, transverse to the nonvolatile memory element F 1 2 of a plurality of connection switching means arranged, F 2 1 select line gate is connected in ...... SX 1 one end of SX 2, SX 3, SX 4 ...... is coupled to the X switch decoder XS- DEC. Further, a plurality of connections arranged in the longitudinal direction switching nonvolatile memory element F means 1 1, F 4 2 gates of ...... is connected select line SY 1, SY 2, SY 3, SY 4 end of ...... is that is coupled to the Y switch decoder YS DE C.

The decoder XS- DE C is in the selected level of either one signal line in the selection lines SX 1, SX 2, SX 3, SX 4 ...... decodes the Adoresu signal XAD inputted from outside the chip to. Moreover, the decoder YS DE C is the address signal YAD select lines SY 1 decodes the input from chip outside, SY 2, SY 3, any one of the signal lines in the SY 4 ...... and it is configured so as to select level. Then, the decoder XS- DEC and YS DEC, in the normal operation after the setting of the connection switching means is terminated by writing to the nonvolatile memory device, all the select lines SX 1, SX 2, SX 3 It is configured to be set to SX 4 ...... and SY 1, SY 2, SY 3, SY 4 ...... a high level (or low level).

Incidentally, FIG. 1 0 Select line SX i, shows a peripheral circuit relating SY j c signal line L xi, with respect to the feed system of L yj Oyopi Ueru WL j, or provided the same decoders, by a method such as providing a pad for direct voltage application can and corresponding child. Nonvolatile memory element at the intersection of the signal lines constituting the cross-point sweep rate Tutsi circuit is in the erased, or OFF state Te temporarily to base before writing begins. And, in its case, it is difficult to suddenly write non-volatile memory element of the chip central is in state of the signal lines divided respectively variable wiring circuits. Therefore, writing to the nonvolatile memory elements on the chip may be as will become row in order from those in the corner of the chip.

Another embodiment of the switch SW1~SW6 constituting a suitable crosspoint switch circuit 1 1 4 when the substrate 1 1 0 is made up of a low dielectric constant material such as epoxy resin Ya ceramic in Figure 1 1 and also in FIG. 1 2 illustrates another embodiment of a suitable Suitsuchi SW1~SW6 when the substrate 1 1 0 is composed of a semiconductor crystal such as silicon. (A) is a front cross-sectional view in FIG. 1 1 and 1 2, (B) is a planar, cross-sectional view.

These examples, performed were so need not provide a clear line RRL and the control line shown in FIG. 4 SX 1, SX 2, SX 3 ...... and SY 1, SY 2, SY 3 ...... Example it is. Insulating film 1 1 6 surrounding is shown as being integral regardless the difference in formation process. Not meant to be formed at the same time just because are integrally indicated, it is actually laminated in the same manner as in FIG. 6 and 7 structure. When the base plate is composed of ceramic, it is possible to generate a substrate containment relay by low-temperature sintering by incorporating a sealed micro relay between glass prior to sintering.

Figure 1 1 Oyopi Figure 1 2 and as is apparent from a comparison of FIGS. 6 and 7, the magnetic Suitsuchi embodiment of FIG. 6 and the magnetic switch of Fig. 6, also the magnetic switch of Fig. 1 2 7 having a configuration similar to that of the magnetic Suitsuchi.

Differences in the magnetic Suitsuchi of FIG 1 Oyopi Figure 1 second magnetic Suitsuchi and 6 Oyopi Figure 7, in Figure 1 1 and Figure 1 2, the internal wiring 1 1 4 a, 1 1 4 b of instead without the ferromagnetic strip MG 1, MG 2 at the tip, a ferromagnetic strip MGP in the upper wall or sidewall of the insulating layer 1 1 6 inside the hollow portion 1 1 8 magnetic switch is formed is provided, on the Suitsuchi in or not to have or to have magnetic poles to the ferromagnetic strip MGP, is obtained so as to set the oFF state.

Further, in this embodiment, the internal wiring 1 1 4 a, 1 1 4 at least one (ferromagnet piece MGP side away) of b is formed of a magnetic material having conductivity. In this configuration, when to have a magnetic pole on the ferromagnetic strip MGP, internal wiring 1 1 4 a, 1 1 4 b is deformed are attracted to the ferromagnetic strip MG P by the same principle as the lead switch contact It is in a conductive state by. The upper wall or the side wall of the hollow portion 1 1 8 provided with the ferromagnetic material elements piece MG P, the internal wiring 1 1 4 a, 1 1 4 b is a magnetic layer on one tip any form shape of a non-magnetic material it may be provided.

When using the magnetic Suitsuchi of the embodiment of FIG. 1 1 or 1 2 as the cross-point switch circuit 1 1 4 provided on the substrate 1 1 0 of Figure 3, on any Suitsuchi of Suitsuchi SW1~SW6 as a method of setting the conditions, there is a method of using an apparatus having a magnetic to head as shown in FIG. 1 3 in example embodiment. As a method to return to the state of the off Suitsuchi SW1 to SW6, a method and substrate by heating the substrate 1 1 0 above the Curie one point of the material of the ferromagnetic material element piece MGP erasing magnetic poles of the ferromagnetic strip MGP whole by applying an alternating magnetic field and a method of erasing. When ferromagnetic strip MG P is demagnetized, the magnetic Suitsuchi internal wiring 1 1 4 a and 1 1 4 b is returned to the OFF state back to the original state by elasticity.

Apparatus shown in FIG. 1 3 is have a controller CPC for controlling the magnetic head MH, closer to head MH to magnetism that want to turn state of the magnetic switch on the substrate 1 1 0 Te, to generate magnetic field lines by applying a current to the head to be those for magnetizing the ferromagnetic material elements pieces MGP.

At this time, the positioning of the head by using the mark MK for positioning are provided on the substrate 1 1 0, accurate positioning if it to determine the position of the head to be the base point Bointo is easily. Also, the movement of the head to Tsu to de may be performed an arm which controls the motor (all not shown) that moves the motor and the Y direction is moved in the X direction holding a substrate 1 1 0 mounting it may be performed using the possible XY stage moving in the X and Y directions as a table to be location. In this manner, on to the magnetic switch, it is set in the OFF state is performed.

Figure 1 4 is an example of a preferred system by applying the multi-chip module of the present invention shows an application system having an analog circuit. The application system together with C PU and SR AM and MMU, the production process and the write signal of the read signal from the medium body magnetic P RML (partial 'response' maximum 'like Rii Hood) in a storage system, such as a hard disk an AD converter AD C and DA converting circuit D AC constituting a circuit for performing, a digital. signal. processor DSP for performing operations for processing the analog signal, as respective semiconductor integrated circuits on separate semiconductor chips and forming, were constructed in the module by bonding the substrate as shown in FIG. 2 or FIG. 3 and a lattice-shaped wiring 1 1 3 accommodated each chip in a single package case crosspoint when to switch circuit 1 1 4 it is intended.

P circuit RML method, as shown in FIG. 1 4, an automatic gain control amplifier 3 2 1 for amplifying a read signal head 3 1 1 or found to read magnetic amplified signal or al noise frequencies a filter circuit 3 2 2 to remove components, an AD converter 3 2 3 to AD convert a read signal (AD C), or encrypting the write data or decrypt read data stored encrypted cryptographic processing circuit 3 2 4 and (DEQ), the E emission coder & decoder 3 2 5 or to decode the read data or encoded write data, the signal processing for performing signal processing such as conversion into an analog signal of the write data circuit 3 and 2 6, necessary for the operation of the La Lee Toanpu 3 2 7 for driving the head 3 1 2 to the writing magnetic, AD converter 3 2 3 (AD C) and the encryption processing circuit 3 2 4 (DEQ) PLL for generating a clock signal that is (Fuwezu locked loop) circuit 3 And it is configured from such as 2 8.

In Figure 1 4 system, of the circuit proc included in a circuit P RML method, an encryption processing circuit 3 2 4 and (DEQ), DA conversion of the encoder and the decoder 3 2 5 Oyo Pi signal processing circuit 3 2 6 function of the circuit except the circuit can be realized by a digital signaling null processor DSP.

Further, in the system of this application example, generate and filter circuit 3 2 2 Test to order the DA converter 4 1 1 and AD converter 4 1 2, the AD converter 3 2 3 Test Tosuru analog signal DA converter 4 1 3, the signal processing circuit 3 2 6 test AD converter 4 1 4 for measuring the analog output voltage of, F FT (fast Fourier transform) to perform the frequency analysis circuit 4 1 5 etc. It is provided. Recently, P RML circuit is often configured as a system LSI on a single semiconductor chip. Then, necessary that case, the DA conversion circuit 4 1 1 and AD converter 4 1 2 such as an analog circuit to test whether they have the desired properties, providing a signal line Ya pad extracting an output signal to the outside of the chip there are, when provided with a signal line for testing an analog circuit, there is a problem that the characteristics of the circuit changes due to the signal line. In contrast, as described above, by configuring as multi-chip module by applying the present invention, the conventional ones were not performed only tests as a whole P RML circuit, constitutes a part of the P RML circuit the circuit of small units than it is possible to perform the test as a target. Moreover, on each Suitsuchi SW 1~SW6 crosspoint scan Itsuchi circuit 1 1 4 provided on the substrate 1 1 0 Applying the present invention, to change the reconfigure the OFF state the connection between chips can be, for example AD converter 3 2 3 when found to have a test line not desired characteristics to perform the test of the filter 3 2 2 and signal processing circuit 3 2 6 by using the AD converter 3 2 3 there is an advantage that it becomes possible things.

Incidentally, when performing the test of such an analog circuit, FIGS. 6 and 7, FIG. 1 1, the desired arbitrary to use the read magnetic switch as shown in Figure 1 2. Since the signal of the leveled down period occurs at Suitsuchi circuit using MO SF ET as shown in FIG. 8, "1", not suitable for transmission of no problem Ana port grayed signal is logical test for judging "0" This is because it is.

Next, an example of a test method of the multi-chip module of Figure 1 according to the present invention will be described with reference to FIG 5.

In tests of the multi-chip module of FIG. 1, first FP GA 2 5 0 is examined if it works correctly, it is the avoidance of defective pieces plant performed when the existence of defects is determined there is a defect (step S 1~S 3). Next, a test circuit for testing a S RAM 2 2 0 in a portion excluding the failed portion in the FP GA 2 5 0 (AL PG) is constructed connecting the FPGA 2 5 0 and SR AM2 2 0 black after setting of the scan points sweep rate Tutsi circuit 1 1 4 is made of S RAM 2 2 0 tests are sequentially performed to (step S 4, S 5).

When the S RAM 2 2 0 to defective portion is not found, the test circuit for testing the FP GA 2 5 custom logic circuits 24 in a portion excluding the failed portion in 0 0 and C PU 2 1 0 ( logic tester) is constructed, FP GA 2 5 0 and custom logic circuit 2 4 0 and C PU 2 1 0 and custom logic circuit 2 4 0 after setting Kurosuboi Ntosuitsuchi circuit 1 1 4 is performed to connect the and testing C PU 2 1 0 is performed (step S 6~S 8). In this case, the test pattern or test pattern generation program is stored already using S RAM 2 2 0 the test is completed.

If the defect is not found, the test circuit for testing a DRAM 2 3 0 in a portion excluding the failed portion in the FP GA 2 5 0 (AL PG) is constructed, the FP GA 2 5 0 DRAM 2 3 0 test since setting the cross-point scan Itsuchi circuit 1 1 4 is performed are sequentially performed so as to connect the D RAM 2 3 0 (step S 9, S 1 0). When the failed portion is found, its bad Adoresu from being stored in the S RAM 2 2 0 or an external storage device, the defective bit by utilizing the redundant circuit provided in the DRAM 2 3 0 relief program order to remedy is read into the C PU 2 1 0, C PU 2 1 0 and DRAM 2 3 0 and CPU 2 1 0 after setting the cross-point sweep rate Tutsi circuit 1 1 4 is performed to connect the the program Ru is the bit repair is performed is performed by (step S 1 1, S 1 2).

Then, for good, FP GA 2 5 above excluding the failed portion part of the 0 part of custom logic, such as user logic is configured (Step S 1 3), so as to constitute further the original system Cross resetting point sweep rate Tutsi circuit 1 1 4 is rope line, between the chips is completed by the connection has been multi-chip module so as to constitute a regular system (step S 1 4). After regular system construction of a multi-chip module, whether the test is working properly and the system is performed, which is determined to be normal is shipped as a good product (Step S 1 5, S 1 6). Na us, in the step S 1 3, the data constituting the user logic so that by utilizing the information indicating the defective portion which has been obtained in step S 1 to avoid the failed portion, F PGA 2 5 in 0 desired logic is configured by writing of the connection information storing memory cells.

By the above procedure, the construction of a multi-chip module having a desired function test of each chip constituting the multi-chip module is made. According to this embodiment, test the RAM 2 20 or DRAM 2 30, CPU 2 1 0 such that other chip Ri by the test circuit constituted by avoiding defective portion in F PGA25 within 0 is executed Therefore, high test result reliability without using an external tester of high performance can be obtained.

Also, when the chip having a relief non failure is detected, since the chip may be replaced with an equivalent other chip is also improved yield. In addition, F

P GA 2 5 After self-test completion by the test circuit configured in 0, since the custom logic is configured to FP GA 2 5 0, there is no wasted chip, due to the mounting the test circuitry module it is possible to suppress the 增大 of size.

Until Although the present invention made by the inventor has been concretely described based on examples, but the present invention is not limited to the above embodiments, rather it can be variously modified without departing from the spirit thereof Nor.

For example, in the above embodiment, the lattice-shaped wiring 1 1 3 and the intersection of the lines provided crosspoint sweep rate Tutsi circuit 1 1 4 is constructed any system as configurable board to board 1 1 0 , or by connecting the chips housed in the package case 1 0 0 constitute a test circuit, the paddle shift or one connection constituting a module original system only switchable wire crosspoint sweep rate Tutsi circuit 1 1 4 it may be configured as a substrate of each module only provided.

Wherein by the substrate as described in Example, although wasteful wiring and elements that are not used occurs, a plurality of multi-chip model substrate versatile available to Joule with different system configurations obtained, production both to be able to reduce the cost, there is an advantage that can be provided to the market as an independent product substrate. Hand, when configured as a substrate for the particular module, as described above, making it possible to design to match the module size makes it a this to reduce the size of the module, Ya wasteful wiring since element is significantly less, depending on the production number and it is possible to lower cost than high above versatile substrate.

Furthermore, a substrate having a cross Boyne G Switch circuit provided at the intersections of the grid-like wiring and wiring of the embodiment, also be used as aging board for mounting an object to be tested of the semiconductor chip in the test device, such as aging this can and child, yet by previously mounting the semi-conductor chip constituting the test circuit in addition to the test of the semiconductor chip, it becomes possible to perform the test at the same time as the aging test, the burden of the tester test due to the simple tester with reduce become possible. Moreover, by utilizing the substrate, if the test of the semiconductor chip is a memory, the method the present inventors have already proposed (International Publication WO 0 1 - 3 7 2 8 5 No., etc.) Accordingly, constitute a test circuit in one of memory on the substrate, it is also possible that testing other memory by said test circuit.

Further, constitute a test circuit in one of the memory on the board, the test instead of testing other memory bets circuit, one of the chip terminals wiring Contact Yopiku loss point sweep rate Tutsi circuit on the substrate yo les, even to perform the test on each chip by an external tester is pulled out to the outside of the module through the. Enormous test pattern to enhance the fault coverage you the entire system as a test target but is required, the test pattern by performing a test for each chip is Ru is shortened test time requires much less. Industrial Applicability

Has been described the case of applying the present invention the invention made by the present inventors multichip module type to be housed in the substrate as a package case and the cap is a field as the background in the above description but the invention can also be used in electronic devices configured on a printed circuit board such as a memory module.

Claims

The scope of the claims
1. A plurality of semiconductor chips and the insulating substrate are electrically connected to the wiring contact Yopi wiring provided at the intersection of any interconnection between the connectable wiring route switching means is provided, mounted on the insulating substrate multi-chip semiconductor device and having a plurality of semiconductor chips which are connected to each other by the wiring and the wiring connection switching means is.
2. Comprising a plurality of package case which can hold a semiconductor chip, according to claim 1, wherein the semiconductor chip is characterized in that said insulation board and the package case in a state held on the package case is formed by bonding multi-chip and a half according to
3. The wiring and characterized in that it comprises a regular wire constituting the desired system by connecting the plurality of semiconductor chips, and a test wiring for transmitting signals to test one semiconductor chip multi-chip semiconductor device according to claim 1 or 2.
4. The wiring multi-chip semiconductor device according to claim 3, characterized in that it is arranged in a lattice pattern on the inside or on the surface of the insulating substrate.
5. The insulating substrate is formed of a low dielectric constant material, the wiring path switching means includes a pair of lead-shaped wire free ends are opposed to each other with a predetermined distance to each other, the tip of the lead-shaped wire or claims, which is a magnetic body piece and Kakaranari, the magnetic body pieces is conducting or blocking state of the signal on whether having a magnetic pole configured to be set element disposed near the multi-chip semiconductor device according to any one of Items 1 to 4.
6. The insulating substrate is formed of a semiconductor crystal, according to claim 1 wherein the wiring path switching unit, which is a non-volatile memory element having a control gate and a floating gate formed on the semiconductor body crystals multi-chip semiconductor device according to any one of to 4.
7. The wiring path switching means is composed of two non-volatile storage elements connected in series, one of these two non-volatile storage element a control terminal, it is arranged in a direction to exchange each other It was among the first selection line contact Yopi second select line connected to the first select line, the other non-volatile storage element, characterized in that the control terminal is connected to the second select line multi-chip semiconductor device according to claim 6,.
8. The semiconductor chip electrically connected to the wiring configurable Contact Yopi wiring desired system on an insulating substrate to be provided wiring path switching means connectable to wirings arbitrary provided intersection of a plurality of semiconductor chips mounted such, these of the semiconductor chip by setting the wiring path switching means one of testable in after performing a test of the semiconductor chip, testable in the other semiconductor chips performs testing of the other semiconductor chip by switching the wiring route switching means, sets the routing so as to constitute the desired system the wiring path by switching the switching unit again after completion test for each semiconductor chip test method of multi-chip semiconductor device which is characterized in that.
9. The one of the plurality of semiconductor chips is a semiconductor chip for outputting an analog signal, the analyst port grayed signal the wiring contact Yopi wiring path switching means test circuit through the output from the semiconductor chip test method of the multi-chip semiconductor device according to 請 Motomeko 8, wherein the evaluating is supplied to the.
1 0. One of the plurality of semiconductor chips is a first semiconductor material chip which outputs an analog signal, one of the other semiconductor chip is a second semiconductor chip analog signal can be input, the in the second semiconductor chip or the second semiconductor chip and the semiconductor chip other than the first semiconductor chip to constitute a test circuit, inputting the analog signal output from said first semiconductor material chip to the second semiconductor chip test method of the multi-chip semiconductor device according to claim 9, feature that sets the wiring path switching means so that is evaluated in the test circuit.
1 1. A plurality of semiconductor chips and electrically connectable terminal portion, a plurality of wiring including a wire connected to the sea urchin arranged the terminal portion by intersecting with each other, intersections provided with any of the wiring substrate for the system being characterized in that a wiring path switching unit can be connected to interconnects.
1 2. The wiring path switching means includes a pair of Li one de-like wiring which free end is opposed to each other with a predetermined distance from each other, and the magnetic pieces provided on the tip or near the of the lead-shaped wire made, the system board according to claim 1 1, wherein the magnetic body pieces is whether Suitsuchi oN in either element oFF state is configured to set having a pole.
1 3. The tip of the lead-shaped wire protrudes hollow portion formed in the insulating layer, and this being arranged so as to face the tip end portion of the other of Li one de-like wiring within the hollow portion system board according to claim 1 2, characterized.
1 4. System board according to any one of claims 1 1 to 1 3 wherein the wiring is characterized in that it is arranged in a grid pattern.
1 5. The wire insulating film for insulating the said semiconductor claim chip than the insulating film formed on the surface you characterized in that it is formed of a material having a low dielectric constant 1 1-1 to be mounted system board according to any one of the 4.
PCT/JP2002/009052 2002-09-05 2002-09-05 Multichp semiconductor device, test method, and system board WO2004023552A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8932886B2 (en) 2004-06-04 2015-01-13 Cree, Inc. Power light emitting die package with reflecting lens and the method of making the same

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH03204957A (en) * 1990-08-31 1991-09-06 Toshiba Corp Semiconductor integrated circuit
EP0481703A2 (en) * 1990-10-15 1992-04-22 Aptix Corporation Interconnect structure for use with programming elements and test devices
JPH0513662A (en) * 1991-07-03 1993-01-22 Nippondenso Co Ltd Multichip module
EP0541288A2 (en) * 1991-11-05 1993-05-12 Fu-Chieh Hsu Circuit module redundacy architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03204957A (en) * 1990-08-31 1991-09-06 Toshiba Corp Semiconductor integrated circuit
EP0481703A2 (en) * 1990-10-15 1992-04-22 Aptix Corporation Interconnect structure for use with programming elements and test devices
JPH0513662A (en) * 1991-07-03 1993-01-22 Nippondenso Co Ltd Multichip module
EP0541288A2 (en) * 1991-11-05 1993-05-12 Fu-Chieh Hsu Circuit module redundacy architecture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8932886B2 (en) 2004-06-04 2015-01-13 Cree, Inc. Power light emitting die package with reflecting lens and the method of making the same

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