WO2004023318A1 - An integrated circuit which accepts instructions in multiple protocols, and a processing system including the integrated circuit - Google Patents

An integrated circuit which accepts instructions in multiple protocols, and a processing system including the integrated circuit

Info

Publication number
WO2004023318A1
WO2004023318A1 PCT/SG2002/000208 SG0200208W WO2004023318A1 WO 2004023318 A1 WO2004023318 A1 WO 2004023318A1 SG 0200208 W SG0200208 W SG 0200208W WO 2004023318 A1 WO2004023318 A1 WO 2004023318A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
processor
command
data
commands
system
Prior art date
Application number
PCT/SG2002/000208
Other languages
French (fr)
Inventor
Vivek Sabnis
Pramod Kumar Pandey
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Application independent communication protocol aspects or techniques in packet data networks
    • H04L69/08Protocols for interworking or protocol conversion

Abstract

An integrated circuit (3) of a data processing system contains software for (5) performing a conversion between multiple command protocols, whereby the integrated circuit (3) can receive commands in one of the multiple formats, convert them to a single predefined protocol, and implement them. The data processing system also includes memories (9, 11, 13, 15) which receive commands in the respective protocols. The memories (9, 11, 13, 15) store the (10) commands, together with any associated data. The generate an interrupt signal, and transmit it to the integrated circuit (3), which subsequently reads the command, and any associated data, converts it to the predefined protocol, and then implements it.

Description

An integrated circuit which accepts instructions in multiple protocols, and a processing system including the integrated circuit

Field of the invention

The present invention relates to an integrated circuit having a microcontroller and for use in a data processing system in which commands are transmitted to the integrated circuit in one of multiple protocols.

Background of Invention

A generic problem in data processing systems is that integrated circuit processors can only process instructions in a single protocol. This makes it difficult to construct a system incorporating multiple integrated circuits, or a system receiving commands from outside in one than one protocol. Typically the designer of a system must either choose a single protocol and ensure that all components of the system can operate in this protocol, or else incorporate custom interfaces to convert between different protocols.

Summary of the Invention

In general terms the present invention proposes that a processor of a data processing system contains a microprocessor and software for performing a conversion between multiple command protocols, whereby the processor can receive commands in one of the multiple formats, and use the microprocessor to convert them to a single predefined protocol which the microprocessor can then implement.

The data processing system preferably comprises memories which receive commands in the respective protocols, and store them, together with any associated data. They then generate an interrupt signal, and transmit it to the integrated circuit, which reads the command, and any associated data, from the memories converts it to the predefined protocol, and then implements it.

The signals themselves may be received by the data processing system through interfaces which are each capable of receiving commands in one of the multiple protocols. Alternatively, or additionally, the data processing system may contain one or more further components, such as other processors, which generate commands for the integrated circuit to carry out. By means of the invention these further components need not be selected to generate commands in the predetermined protocol.

The present invention makes it possible to provide complicated control and data transfer functions using the ROM of an integrated circuit with an embedded microprocessor. The functions are invoked via simple messages using simple interfaces.

The design can be used as an interface protocol in designs with more than one processor, when there is a requirement to pass data between them. The invention further makes possible a handshake mechanism for exchanging code and configuration in a multi-chip environment (all with embedded processors).

Optionally, the entire system (not only the processor but also the memories, interfaces etc) can be implemented on a single integrated circuit, so that the invention makes possible control and configuration of a system-on-chip via a simple interface (e.g. UART/IIC).

Alternatively, the invention may be implemented using a mixture of on-chip and off-chip processors using a PCT/Generic/IIC/UART interface. This may give a hardware platform on which a message passing stack can be developed independent of hardware. Brief Description of The Figures

Preferred features of the invention will now be described, for the sake of illustration only, with reference to the following figures in which:

Fig. 1 shows the overall structure of a data processing system which is an embodiment of the invention;

Fig. 2 shows schematically, the operation of generating interrupts; and Fig. 3 shows the structure of the two registers associated with each of the mailbox memories of Fig 1.

Detailed Description of the embodiments

Referring to Fig. 1 , a data processing system which is an embodiment of the invention is shown as comprising a Bus 1 which interconnects a CPU processor 3, a PCI/Host interface 5, a IIC interface 7. The PCI/Host interface 5 passes instructions back and forth between the bus 1 and a PCI (peripheral component interconnect) Master or external host (not shown). The IIC interface 7 passes instructions back and forth between the bus 1 and an IIC device using an IIC device (not shown). The interfaces 5, 7 transmit to the bus 1 instructions which are intended to be carried out by the CPU 3 but which are in differing interface protocols. The system shown in Fig. 1 can be further expanded by including any number of further processors analogous to processor 3, and/or by any number of further interfaces analogous to interfaces 5, 7 which transmit instructions to the bus 1 in differing protocols.

The bus 1 also passes instructions to four memories which are here referred to as "mailboxes" MB1 ,MB2, MB3, MB4. Typically, each mailbox has a main memory section 9, 11, 13, 15 which may have a size of 512x32 array of 2Kbyte boxes. Each of the mailboxes MB1 ,MB2, MB3, MB4 further includes two respective registers: respective status registers 901 , 111 , 131 , 151 and command registers 902, 112, 132, 152. The structure of these two registers is shown in Fig. 3.

Each status register 901 , 111 , 131 , 151 comprises a command section 17 (which is typically only a single bit), a mailbox ID section 19 storing a maxilbox ID and an (unused) section 21. The corresponding command register 902, 112, 132, 152 merely stores mailbox commands. The corresponding main memory section 9, 11 , 13, 15 stores the data associated with the command (i.e. data which the command will tell the processor 3 to process).

Although four mailboxes are shown, preferably the processor 3 is associated with only two of them: a first mailbox which stores commands for the processor to implement and a second mailbox which stores the output of the processor. The mailboxes thus have directional properties. Note that when there are multiple processors, an output mailbox of one processor may function as an input mailbox of another processor in respect of commands transmitted from the first processor to the second. In other variations of the embodiment, a given processor may have more than one output and/or input mailbox, for storing different sorts of commands, e.g. ones with different priorities.

On the arrival through one of the interfaces 5, 7 of a command which is intended for the processor 3 and which is written in a protocol which the microcontroller of the processor 3 does not directly process, the command is directed to the mailbox for storing commands for the processor 3. This means that the status register for that mailbox is updated so that the command section 17 indicates that there is a command pending. The command itself is written into the command register associated with that mailbox. The data associated with the command is written into the main memory section of the mailbox. The fact that the command section 17 indicates that a command is pending means that the mailbox generates an interrupt to the processor 3 (note that in alternative designs it would be possible for the processor to poll the mailboxes to see whether commands are waiting). The processor 3 receives the interrupt, knows which format the command will be in (because the interrupt signal carries this information). The processor 3 reads the command from the command register 902, 112, 132, 152 and the associated data from the main memory section 9, 11 , 13, 15 of the mailbox. After reading this data the processor 3 clears the command bit 17, so that no further interrupt will be generated.

The processor 3 is provided with internal software which converts the command from the original protocol stored in the command register of the mailbox into a protocol which the processor can handle. The details of this software will not be given here, since software capable of performing such conversions is well known to a skilled reader and is implemented in existing conversion interfaces. At this point the processor may write the command back into the mailbox (e.g. a different section of the mailbox) in the converted protocol, and subsequently a different section of the processor 3 reads the command again. The processor then implements the command in the converted protocol, including processing the associated data according to the command.

The processor writes the output of the processing operation to the mailbox for storing its output.

In the case that a given one of the interfaces 5, 7 receives commands in a protocol which is directly acceptable to the processsor 3 without any kind of conversion, then that command may be transmitted to the processor 3 directly without passing through any of the mailboxes. Similarly, when the output of the processor is in a format which can be handled by an interface, the output of the processor 3 can be transmitted directly out of the system using the interface.

Note that this simple but powerful concept can be expanded to any number of processors. For example, the system may include, in addition to the processor 3 a less powerful processor which is also connected to the processor by the bus 1. The second processor may command the processor to perform tasks (e.g. tasks itself would take an unacceptably long time) by transmitting a corresponding command to one of the mailboxes.

In the case that the systems includes two co-operating processors, for example, there may be two mailboxes for each of the processors. After resource allocation is done, a first processor may write data into the input memory in which commands for the other processor are stored: writing the data to be operated on into the mailbox, updating the Cmd_pending register 17 of the associated status register, and writing the command into the command register CMD_REGISTER of the associated register. The operation of writing a command into the command register will generate the interrupt to the other processor. The other processor will read the data from the mailbox and the command from the associated command register CMD_REGISTER. The data is processed according to the command. After reading the data, the processor clears the Cmd_pending bit of the status register STATUS_REGISTER, so that no further interrupt will be generated.

Within a given one of the integrated circuits 3, the reading, processing and writing is implemented via a messaging structure and nascent code running on a non-volatile storage unit (ROM) of the integrated circuit 3. This is illustrated in Fig. 2, which shows an interrupt arriving from the mailboxes MB1 , MB2, MB3 and MB4 into an interrupt control unit 22. Fig. 2 is schematic in that the interrupt control units for two different processors are shown as a single unit 22, whereas in fact there is a separate interrupt control unit inside each of the processors for receiving interrupts directed to that processor. The interrupt control unit 22 sends an interrupt signal to the main microprocessor of the processor 3, which causes that embedded microprocessor to read the command and converts it into the predetermined protocol (optionally making use of the cache memory within the processor 3 and/or associated RAM memories).

Every time an interrupt awakens the integrated circuit, it interprets the message and takes appropriate action, of reading the command and data from the mailbox which generated the interrupt. At the end of the action, the integrated circuit 3 either acknowledges the host processor (i.e. the processor which generated the command?) via a return message or returns the requested action item in the form of a predetermined message format.

Claims

Claims
1. A processor located on an integrated circuit and comprising:
a microprocessor; and
an interface for receiving commands in one of multiple protocols;
the microprocessor being arranged to operate software stored within the processor for converting the commands to a predefined format, and to implement the commands in that format.
2. A data processing system comprising:
a processor according to claim 1 ; and
one or more memory devices, each memory device being arranged to receive and store a command in one of said protocols and to generate an interrupt signal to the processor,
the processor being arranged, following receipt of the interrupt signal, to read the command from the corresponding memory device, convert it to the predefined format, and implement it.
3. A data processing system according to claim 2 in which the memory devices comprise a respective register for storing the command and a respective memory for storing data associated with the command and to be processed by the processor during the implementation of the command.
4. A data processing system according to claim 2 or claim 3 further including one more interface devices for receiving said commands in a respective one of said protocols and transferring them to the corresponding memory devices.
5. A data processing system according to claim 2, claim 3 or claim 4 further comprising at least one second processor having a processing speed lower than the processing speed of the microprocessor of the integrated circuit, the second processor being arranged to transmit commands to the integrated circuit by transferring those commands to the memory devices.
6. A data processing system according to any of claims 2 to 5 in which said processor is an integrated circuit, said interface being an interface to the integrated circuit.
7. A data processing system according to any of claims 2 to 5 which is entirely located on a single integrated circuit.
8. A method of processing commands in one of multiple command protocols, the method including:
receiving the commands at a processor;
accessing software stored in the processor;
operating the software to convert the commands to a predetermined protocol; and
implementing the commands.
9 A method according to claim 8 comprising the prior additional steps of:
transferring the commands to a memory associated with the processor,
generating an interrupt signal to the processor to indicate the existence of the command in the memory; and
in response to a signal from the processor transferring the command to the processor.
PCT/SG2002/000208 2002-09-06 2002-09-06 An integrated circuit which accepts instructions in multiple protocols, and a processing system including the integrated circuit WO2004023318A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/SG2002/000208 WO2004023318A1 (en) 2002-09-06 2002-09-06 An integrated circuit which accepts instructions in multiple protocols, and a processing system including the integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2002/000208 WO2004023318A1 (en) 2002-09-06 2002-09-06 An integrated circuit which accepts instructions in multiple protocols, and a processing system including the integrated circuit

Publications (1)

Publication Number Publication Date
WO2004023318A1 true true WO2004023318A1 (en) 2004-03-18

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Country Status (1)

Country Link
WO (1) WO2004023318A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010025323A1 (en) * 2000-03-02 2001-09-27 Jason Sodergren Multi-protocol adapter for in-vehicle and industrial communications networks
US20020019891A1 (en) * 1999-12-30 2002-02-14 James Morrow Generic device controller unit and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020019891A1 (en) * 1999-12-30 2002-02-14 James Morrow Generic device controller unit and method
US20010025323A1 (en) * 2000-03-02 2001-09-27 Jason Sodergren Multi-protocol adapter for in-vehicle and industrial communications networks

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"NORMALIZED MULTIPROTOCOL PACKET PROCESSOR" IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 36, no. 7, 1 July 1993 (1993-07-01), pages 225-226, XP000383610 ISSN: 0018-8689 *
ANONYMOUS: "TC1920;32-Bit Single-Chip Microcontroller" [Online] June 2002 (2002-06) , INFINEON TECHNOLOGIES AG , MUNICH XP002247806 Retrieved from the Internet: <URL: http://www.infineon.com/cmc_upload/documen ts/046/740/TC1920_po_V1.1.pdf> [retrieved on 2003-07-15] the whole document *

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