WO2004014043A1

WO2004014043A1 - Communicating data in a selected one of multiple protocols

Info

Publication number: WO2004014043A1
Application number: PCT/SG2002/000175
Authority: WO
Inventors: Xiaoni Wei; Pramod Kumar Pandey
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2002-08-05
Filing date: 2002-08-05
Publication date: 2004-02-12
Anticipated expiration: 2005-02-05

Abstract

An Ethernet communication interface (1) (for use in equipment (3) such as an (5) Ethernet switch) has a set of interface pins (7) and an internal control logic which assigns respective functions to the interface pins (7) which are consistent with a selected protocol. In other words, the same set of interface pins (7) is used in different ways in the different protocols. This means that any number of protocols may be supported using only a number of interface pins which is as low as the highest number of interface pins required by any single one of the standards. The interface (1) is initialised using initialisation pins (9) among the interface pins (7) which, during an initialisation phase, receive signals indicating which protocol to use. The equipment (3) can ensure that the interface (1) functions in the desired protocol by supplying the corresponding signals to the initialisation pins during the initialisation phase. During the communication phase the input pins (9) are 'pin-strapped', to perform the role of output pins.

Description

Communicating data in a selected one of multiple protocols

Field of the invention

The present invention relates to methods and integrated circuits for transmitting data in a selected one of multiple protocols.

Background of the Invention

A variety of Ethernet MAC interface protocols are known, such as GMII (gigabit medium independent interface), Mil (medium independent interface), RGMII (reduced GMII), TBI (ten bit interface), and SMII (serial Mil). It would be advantageous if an Ethernet device (such as a switch) were capable of operating according to more than one of these standards, according to which device(s) it is connected to.

The number of pins required by each of these standards is as follows: GMII, 182 pins; Mil interface 128 pins; RGMII interface 96; TBI interface, 192 pins, SMII interface 160 pins. Thus, to provide a single data interface with the sets of pins required for multiple respective standards conventionally requires that the total number of pins in the interface is very high, increasing both the size and the area of the interface.

Summary of the invention

The present invention proposes in general terms that, an Ethernet communication interface (for example, an Ethernet switch) having a set of interface pins should include an internal control logic which, according to an interface protocol selected from a predetermined set of interface protocols, assigns respective functions to the interface pins which are consistent with the selected protocol. In other words, the same set of interface pins is used in different ways in the different protocols. This means that any number of protocols may be supported using only a number of interface pins which is as low as the highest number of interface pins required by any single one of the standards.

Preferably, the interface includes one or more initialisation pins which, during an initialisation phase, receive signals which indicate to the interface which of the protocols is selected. The interface registers the selection, and assigns the functions of the interface pins accordingly. This means that an interface design can be used in a variety of different kinds of equipment which are required to communicate in different respective protocols. The equipment can ensure that the interface functions in the desired protocol simply by supplying the corresponding signals to the initialisation pins during the initialisation phase.

The initialisation pins are preferably comprised among the interface pins. That is, during the initialisation phase the initialisation pins receive the signal indicating the selected format, and subsequently during the communication phase functions are assigned to those pins which enable them to contribute to the communication in the selected format. This means that the total number of pins required by the device is not increased compared to the minimum number required to operate all the predetermined communication protocols. Note that in the second phase the initialisation pins may in certain of the communication protocols be required to be output pins, rather than input pins. The use of pins having input and output roles at different times is known as "pin-strapping".

Note that although this text refers to "pins", no limitation is thereby implied on the physical construction of the pins. For example, the "pins" need not be elongate conductors, but may be any element which permits an electrical connection to be made to a corresponding element of another device. Brief description of the figures

A non-limiting embodiment of the invention will now be described for the sake of example only with reference to the following drawings in which:

Fig. 1 is a schematic view of the use of an embodiment of the present invention;

Fig. 2 is a schematic view of the pinstrapping operation of the embodiment of Fig. 1 ; and

Fig. 3 is a view of the control arrangement for assigning functions to the interface pins of the embodiment of Fig. 1.

Detailed Description Of The Embodiments

Referring to Fig. 1 an interface device 1 according to the invention is shown within an item of equipment 3 which is required to communicate with a second item of equipment 5 in a certain communication protocol.

The interface device has a number of interface pins 7 including a plurality (e.g. two) initialisation pins 9. The initialisation pins 9 are connected to respective voltage sources 11 via transistors 13 which conduct only during an initialisation phase indicated by a reset signal ("core_reset_a"), which is transmitted also the interface device 1 , becoming high (logic 1) (in other embodiments, a logic 0 value could be the signal for a reset). When the signal core_reset_a is high, a latch 23 reads and stores inputs from the initialisation pins 9 and sends control signals to a control logic 15 of the interface device 1 which sets the communication protocol accordingly. In other words, the equipment 1 can control which communication protocol its interface device 3 uses merely by setting the values of the voltage sources 11 correspondingly. This means that a single design of interface device 3 can be used in multiple kinds of equipment 3 which are required to operate in different respective communication protocols. Note that the voltage sources 11 may optionally be set to a static value, but more preferably may generate a multibit input to the initialisation pins 9 (e.g. a sequence of highs and lows). One advantage of this is that the number of protocols between which a selection is made need not be limited by the number of initialisation pins.

When the core_reset_a signal becomes logic 0, the communication phase begins. The transistors 13 cease to conduct, cutting the initialisation pins 9 off from the voltage sources 11. The control logic 15 then connect the interface pins 7 to network layer devices (e.g. MAC and GMAC) of the equipment 3 (which may be on the same integrated circuit as the interface 3) with a connectivity determined by the selected protocol. Note that the initialisation pins 9 are used in this phase as if they were normal interface pins 7, so that their signal input role is replaced by a signal output role. Thus, the functions performed by the initialisation pins 9 change ("pinstrapping").

This change of roles is indicated in Fig. 2 which shows how, for a single initialisation pin 9, when the signal core_reset_a becomes logic high it turns on a switch 21 and also makes a latch 23 receptive to receiving a signal. An amplifier 25 ensures that during the initialisation phase the signal received at the initialisation pin 9 does not pass into other portions of the interface device. When the signal core_reset_a becomes logic low (i.e. the communication phase begins), the switch 21 turns off, and the interface pin 9 becomes an output pin having an output gtx_o[9;7]. The latch 23 stores the value it received during the initialisation phase, and continues to outputs two corresponding signals core_is_ge_mode and gmode_sel[1 ;0] (where "[1 ;0]" means "[1]" for one of the initialisation pins and "[0]" for the other), which are used to select the protocol used in the communication phase. The output core_is_ge_mode is generated based on the multibit inputs from voltage sources 11. The communication protocol thus selected is shown in Table 1.

Table 1

Fig. 3 shows an example of the control circuit which determines the correspondence coupling between the inferface pins 7 (marked as PAD - the physical layer) and the network layer signal emitting /receiving interfaces MAC, GMAC of the equipment 3. The correspondence is controlled by a number of selectors 31 which are controlled by the signals output by the latch 23. Note that the precise design of the circuitry shown in Fig. 3 will be straightforward to an expert in the field, given a predetermined set of communication protocols which he wishes to enable. The correspondences between the interface pins and the internal interfaces MAC and GMAC for the GMII, SMII, TBI, and Mil protocols are given in Appendix 1.

Although only a single embodiment of the invention has been described here, many variations are possible within the scope of the invention as will be clear to an expert. 4/014

Appendix 1

Dir. Pin name SMII/GMII/rBI/RGMII/ H interface

Dir. Pin name SMII interface

0 gfρ_pad_tx_clk smii_tx_clk=gfp_pad_tx_clk

0 gf _pad_tx[9:0] smii_tx_data[7:0]= gfp_pad_tx_code_group[7:0] smii_tx_sync= gfp_pad_tx_code_group[8]

I pad_gfp_rx_clka smii_rx_clk=pad_gfp_rx_clka

I pad_gf _rx_clkb

I pad_gfp rx code_grou smii_rx_data[7:0]= pad_gfp_rx_code_group[7:0] p[9:0J smii_rx_sync=pad_gfp_rx_code_group[S]

I pad_gfp_col

I pad_gfp_crs

Dir. Pin name GMII interface

0 gfp_pad_tx_clk gtx_clk= gi _pad_tx_clk

0 gfp_pad_tx[9:0] gtx_data[7:0]=gf _pad_tx_code_group[7:0] gtx_en=g p_pad_tx_code_group[8] gtx_er=gfp_pad_tx_code_group[9]

I pad_gfp_rx_clka

I pad_gfp_πc_clkb grx_clk=pad_gfp_rx_clkb

I pad_gfp rx code_grou grx_data[7:0]=pad_gfp_rx_code_group[7:0] p[9:0] grx_dv=pad_gfp_rx_code_group[8] grx_er=ρad_gfp_rx_code_group[9]

I pad_gfp_coI gmii_col= pad_gfp_coI

I pad_gfp_crs gmii_crs= pad_gfρ_crs

Dir Pin name TBI interface Dir. Pin name SMI-/GMII TBI/RG II/MII interlace

0 gfp_pad_tx_clk pma_tx_clk=gfp_pad_tx_clk

0 gfp_pad_-x[9:0] pma_tx_code_group[9:0]= gfp_pad_tx_code_group[9:0] pad_gfp_rx_clka pma_rx_clka=pad_gfp_rx_clka pad_gfp_rx_clkb pma_rx_clkb=pad_gfp_rx_clkb pad_gfp rx code_grou pma_rx_code_group[9:0]-pad_gfp_rx_code_group[9:0] p[9:0] pad_gfp_col pma_signaI_detect=pad_gfp_coI pad_gfp_crs

Dir. Pin name RGMII interface

0 gfp_pad_tx_clk rgmii_.x_clk= gf _pad_tx_clk

0 gfp_pad_tx[9:0] rgmii_tx_data[3:0]=gfp_pad_tx_code_group[3:0] rgmii_tx_ctl= gfp_pad_tx_code_group[8]

I pad_gfp_rx_clka

I pad_gfp_rx_clkb rgmii_rx_clk=pad_gfp_rx_clkb

I pad_gfp rx code_grou rgmii_rx_data[3:0]=pad_gfp_rx_code_group[3:0] p[9:0] rgmii_rx_ctl=pad_gfp_rx_code_group[8]

I pad_gfp_col

I pad_gfp_crs

Dir. Pin name Mil interface

0 gfp_pad_tx_clk

0 gfp_pad_tx[9:0] mii_tx_data[3:0]=gfp_pad_tx_code_group[3:0] mii_tx_en=gfp_pad_tx_code_group[8] mii_tx_er=gfp_ρad_tx_code_group[9]

I pad_gfp_rx_clka mii_tx_clk= pad_gfp_rx_clka

I pad_gfp_rx_clkb mii_rx_clk=pad_gfp_rx_clkb

I pad_gfp rx code_grou mii_rx_data[3:0]= pad-gfp_rx_code_group[3:0] p[9:0] mii_rx_dv=pad_gfp_rx_code_group[8] mii_rx_er=pad_gfp_rx_code_group[9]

I pad_gfp_col mii_col=pad_gfp_col

I pad_gfp_crs mii_crs=pad_gfp_crs

Claims

1. An Ethernet communication interface comprising:

a set of interface pins; and

a control logic which, according to interface protocol selected from a predetermined set of interface protocols, assigns respective functions to the interface pins which are consistent with the selected protocol.

2. An interface device according to claim 1 including one or more initialisation pins which, during an initialisation phase, receive initialisation signals which indicate to the interface which of the protocols is selected, and a latch for storing the received initialisation signals, the outputs of the latch controlling the control logic.

3. An interface device according to claim 2 in which the initialisation pins are included in the set of interface pins.

4. An apparatus having an interface device according to claim 2 or claim 3 and means for determining the inputs to the initialisation pins during the initialisation phase.

5. A communication method comprising the steps of:

(i) during an initialisation phase supplying signals to an interface device having a plurality of interface pins, the signals indicating a selection of a desired one of a predetermined set of protocols, the interface device registering the selection; and

(ii) during a communication phase communicating using the interface device, the interface device operating using the selected protocol.

6. A method according to claim 5 in which the signals are input to the interface device using initialisation pins which are comprised in the set of interface pins and which during the communication phase are used for the communication.

7. A method according to claim 6 in which the initialisation pins are used as output pins during the communication.