WO2004013960A1 - Hybrid structure for distributed power amplifiers - Google Patents

Hybrid structure for distributed power amplifiers Download PDF

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Publication number
WO2004013960A1
WO2004013960A1 PCT/US2003/022571 US0322571W WO2004013960A1 WO 2004013960 A1 WO2004013960 A1 WO 2004013960A1 US 0322571 W US0322571 W US 0322571W WO 2004013960 A1 WO2004013960 A1 WO 2004013960A1
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WO
WIPO (PCT)
Prior art keywords
power amplifier
distributed power
transistors
substrate
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/022571
Other languages
French (fr)
Inventor
Lei Zhao
Anthony M. Pavio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Motorola Inc filed Critical Freescale Semiconductor Inc
Priority to AU2003265286A priority Critical patent/AU2003265286A1/en
Priority to JP2004526126A priority patent/JP4313759B2/en
Publication of WO2004013960A1 publication Critical patent/WO2004013960A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/605—Distributed amplifiers
    • H03F3/607—Distributed amplifiers using FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/541—Transformer coupled at the output of an amplifier

Definitions

  • This invention relates generally to power amplifiers and more specifically to hybrid structures for distributed power amplifiers.
  • FIG. 1 shows a schematic 100 of a distributed power amplifier 102 integrated as a single chip coupled to balun/transformer 104 on a ceramic substrate 106.
  • the substrate 106 is typically formed using Low Temperature Cofired Ceramics Technology (LTCC).
  • LTCC Low Temperature Cofired Ceramics Technology
  • the distributed power amplifier 102 includes an input 108, a plurality of transistors 110, here shown as field effect transistors (FETs) each having drain 112, gate 114 and source 116, and an output 118.
  • Amplifier 102 further includes gate transmission line 120 having gateline inductors 121 as well as drain transmission line 122 having drainline inductors 123, along with drainline capacitors 124, and termination resistors 126, 128.
  • FIG. 2 shows a graph 200 of gain (dB) 202, output power (Pout, dBm) 204 and power-added efficiency (PAE%) 206 versus frequency (GHz).
  • Graph 200 is based on a simulation for a five-cell PHEMT (Pseudomorphic High Electron Mobility) transistor, drain-tapered, distributed amplifier with 1 watt output power with the wirebonds 130 connecting the IC 102 and the LTCC substrate 106 as shown in FIG. 1.
  • PHEMT Pulseudomorphic High Electron Mobility
  • Power amplifier efficiency is a design parameter of considerable interest, and circuit designers are constantly seeking ways of improving the efficiency which in turn translates into longer battery life for portable products.
  • FIG. 1 is a schematic diagram of a power amplifier in accordance with the prior art
  • FIG. 2 is a graph of gain and output power and power-added efficiency versus frequency in accordance with the prior art
  • FIG. 3 is a schematic diagram of a power amplifier in accordance with the present invention.
  • FIG. 4 is a graph of gain and output power and power-added efficiency versus frequency in accordance with the present invention.
  • FIG. 3 shows a schematic 300 for a distributed power amplifier 302 formed in accordance with the present invention, the power amplifier being coupled to a load, such as a transformer/balun 304.
  • drain transmission line inductors 323 and output 318 are built in the ceramic substrate 306, and the rest of the amplifier 302 is built in IC form.
  • the IC portion of power amplifier 302 includes an input 308, a plurality of transistors 310, here shown as FETs each having drain 312, gate 314 and source 316.
  • the IC portion of amplifier 302 further includes gate transmission line 320, gate transmission line inductors 321, drainline capacitors 324, and termination resistors 326, 328.
  • wirebond interconnection 330 is made between the drainline capacitors 324 and drainline inductors 323, which is a higher impedance point in the circuit.
  • the wirebond inductance will not introduce performance degradation typically caused by dynamic load errors.
  • the wirebond inductance becomes negligible and has little or no impact on the power amplifier's performance.
  • FIG. 4 is a graph of gain (dB), output power (Pout, dBm) and power-added efficiency (PAE%) versus frequency (GHz) achieved for a hybrid structure formed in accordance with the present invention.
  • the same parameters were used in the simulation of FIG. 4 as that in FIG. 2 except that the drainline transmission inductors were integrated onto the substrate 306 and wirebonded out from the PA to the inductive points.
  • FIG. 4 shows significant performance improvement of the power amplifier compared to FIG. 3 over the entire frequency band.
  • Low voltage power amplifiers formed in accordance with the present invention can be used in a variety of products including, but not limited to, software definable radios, cellular handsets, and wireless broadband applications.
  • the hybrid integration of the power amplifier extends to a variety of transistor types, including bipolar transistors in which the base transmission line remains part of the amplifier IC and the inductors of the collector transmission line is integrated into the substrate. While the hybrid structure has been described as preferably using a ceramic substrate, other substrate materials found in amplifier designs, such as organic substrates used in high density interconnect (HDI) can also be used.
  • HDI high density interconnect

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Microwave Amplifiers (AREA)

Abstract

A hybrid low voltage distributed power amplifier structure (300) provides improved efficiency by forming drain transmission line inductors (323) on a substrate (306) while the rest of the amplifier is built in IC form (302). A wirebond interconnection (330) is made between the IC s drainline capacitors (324) and the substrate s drainline inductors (323) which are a higher impedance point in the circuit. As a result, the wirebond inductance becomes negligible and has little or no impact on the power amplifier's performance.

Description

HYBRID STRUCTURE FOR DISTRIBUTED POWER AMPLIFIERS
FIELD OF THE INVENTION This invention relates generally to power amplifiers and more specifically to hybrid structures for distributed power amplifiers.
BACKGROUND OF THE INVENTION Low voltage power amplifiers are used in a variety of applications including radio and cellular handsets as well as wireless broadband applications to name a few. The term hybrid structure typically refers to passive circuit elements formed on non- semiconductor substrates combined with semiconductors. Hybrid structures are often used in the design of low voltage distributed power amplifier (PA) circuits because of the low cost properties of the structure. FIG. 1 shows a schematic 100 of a distributed power amplifier 102 integrated as a single chip coupled to balun/transformer 104 on a ceramic substrate 106. The substrate 106 is typically formed using Low Temperature Cofired Ceramics Technology (LTCC). The distributed power amplifier 102 includes an input 108, a plurality of transistors 110, here shown as field effect transistors (FETs) each having drain 112, gate 114 and source 116, and an output 118. Amplifier 102 further includes gate transmission line 120 having gateline inductors 121 as well as drain transmission line 122 having drainline inductors 123, along with drainline capacitors 124, and termination resistors 126, 128.
Traditionally, the distributed power amplifier 102 has been built with both the gate transmission line 120 and the drain transmission line 122 integrated on the power amplifier IC chip 102. The connection to the rest of the circuit is accomplished with wirebonds 130 at the output 118 of the power amplifier chip 102. For a low voltage power amplifier, the output 118 of the PA 102 is a low impedance point (3 to 4 ohm). Thus, the wirebond inductance significantly degrades the performance of the amplifier 102 since the inductive reactance of the wirebonds 130 is a large percentage of the total load impedance. FIG. 2 shows a graph 200 of gain (dB) 202, output power (Pout, dBm) 204 and power-added efficiency (PAE%) 206 versus frequency (GHz). Graph 200 is based on a simulation for a five-cell PHEMT (Pseudomorphic High Electron Mobility) transistor, drain-tapered, distributed amplifier with 1 watt output power with the wirebonds 130 connecting the IC 102 and the LTCC substrate 106 as shown in FIG. 1.
Power amplifier efficiency is a design parameter of considerable interest, and circuit designers are constantly seeking ways of improving the efficiency which in turn translates into longer battery life for portable products.
Accordingly, it would be desirable to have a power amplifier structure that is less susceptible to the wirebonds so as to have less impact on impedance and thereby provide improved efficiency.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
FIG. 1 is a schematic diagram of a power amplifier in accordance with the prior art;
FIG. 2 is a graph of gain and output power and power-added efficiency versus frequency in accordance with the prior art;
FIG. 3 is a schematic diagram of a power amplifier in accordance with the present invention; and FIG. 4 is a graph of gain and output power and power-added efficiency versus frequency in accordance with the present invention.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
DETAILED DESCRIPTION OF THE DRAWINGS FIG. 3 shows a schematic 300 for a distributed power amplifier 302 formed in accordance with the present invention, the power amplifier being coupled to a load, such as a transformer/balun 304. In accordance with the present invention, drain transmission line inductors 323 and output 318 are built in the ceramic substrate 306, and the rest of the amplifier 302 is built in IC form. Thus, the IC portion of power amplifier 302 includes an input 308, a plurality of transistors 310, here shown as FETs each having drain 312, gate 314 and source 316. The IC portion of amplifier 302 further includes gate transmission line 320, gate transmission line inductors 321, drainline capacitors 324, and termination resistors 326, 328. In accordance with the present invention, wirebond interconnection 330 is made between the drainline capacitors 324 and drainline inductors 323, which is a higher impedance point in the circuit. By moving the wirebond interconnection point to a higher impedance point in the circuit, the wirebond inductance will not introduce performance degradation typically caused by dynamic load errors. As a result, the wirebond inductance becomes negligible and has little or no impact on the power amplifier's performance.
FIG. 4 is a graph of gain (dB), output power (Pout, dBm) and power-added efficiency (PAE%) versus frequency (GHz) achieved for a hybrid structure formed in accordance with the present invention. The same parameters were used in the simulation of FIG. 4 as that in FIG. 2 except that the drainline transmission inductors were integrated onto the substrate 306 and wirebonded out from the PA to the inductive points. FIG. 4 shows significant performance improvement of the power amplifier compared to FIG. 3 over the entire frequency band.
Low voltage power amplifiers formed in accordance with the present invention can be used in a variety of products including, but not limited to, software definable radios, cellular handsets, and wireless broadband applications.
While shown as an FET configuration, one skilled in the art appreciates that the hybrid integration of the power amplifier extends to a variety of transistor types, including bipolar transistors in which the base transmission line remains part of the amplifier IC and the inductors of the collector transmission line is integrated into the substrate. While the hybrid structure has been described as preferably using a ceramic substrate, other substrate materials found in amplifier designs, such as organic substrates used in high density interconnect (HDI) can also be used.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages , solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
We claim:

Claims

1. A distributed power amplifier structure, comprising:
a substrate; power amplifier circuitry including a plurality of transistors having transmission line inductors coupled thereto; and transmission line inductors formed on the substrate and coupled to the transistors of the IC through wirebonds. '
2. A distributed power amplifier structure, comprising: a ceramic substrate; an integrated circuit (IC) on the ceramic substrate, the IC including: a plurality of transistors each having a drain, gate, and source, the source being coupled to ground, the gate being coupled to a series of gateline transmission inductors; a series of drainline transmission inductors formed on the ceramic; a drainline capacitor coupled to the drain of each transistor; and a wirebond interconnection between each drainline transmission inductor on the ceramic and each drainline capacitor on the IC.
3. The distributed power amplifier structure of claim 2, further comprising: an input on the IC; and an output taken from the series of" drainline transmission inductors, the output coupled to a load.
4. The distributed power amplifier of claim 2, wherein the power amplifier is used in a software definable radio.
5. The distributed power amplifier of claim 2, wherein the power amplifier is used in a cellular handset.
6. The distributed power amplifier of claim 2, wherein the power amplifier is used in a wireless broadband application.
7. The distributed power amplifier of claim 3, wherein the load comprises a balun/transformer integrated on the ceramic substrate.
8. The distributed power amplifier of claim 2, wherein the transistor is an Field Effect Transistor (FET). A distributed power amplifier structure, comprising:
a substrate; an integrated circuit (IC) formed over the substrate, the IC including a first portion of a distributed power amplifier circuit including transistors and a first set of transmission line inductors coupled to the transistors; and a second set of transmission line inductors formed on the ceramic substrate and coupled to the transistors of the IC through wirebond interconnects.
10. The distributed power amplifier structure of claim 9, wherein the substrate is ceramic.
11. The distributed power amplifier structure of claim 9, wherein the transistors are at least one of P-channel Field Effect Transistors (FETs), NT-channel Field Effect Transistors (FETs) and bipolar transistors.
PCT/US2003/022571 2002-08-02 2003-07-18 Hybrid structure for distributed power amplifiers Ceased WO2004013960A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2003265286A AU2003265286A1 (en) 2002-08-02 2003-07-18 Hybrid structure for distributed power amplifiers
JP2004526126A JP4313759B2 (en) 2002-08-02 2003-07-18 Hybrid structure for distributed power amplifiers.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/211,825 US6614307B1 (en) 2002-08-02 2002-08-02 Hybrid structure for distributed power amplifiers
US10/211,825 2002-08-02

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JP (1) JP4313759B2 (en)
KR (1) KR101031986B1 (en)
CN (1) CN100557957C (en)
AU (1) AU2003265286A1 (en)
WO (1) WO2004013960A1 (en)

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US7885409B2 (en) 2002-08-28 2011-02-08 Rockwell Collins, Inc. Software radio system and method
US7233207B2 (en) 2005-05-06 2007-06-19 Motorola, Inc. System and method for providing an input to a distributed power amplifying system
KR100806298B1 (en) * 2006-04-12 2008-02-22 한국과학기술원 Power Amplifier Using Transmission Line Transformer
KR100757371B1 (en) * 2006-07-07 2007-09-11 삼성전자주식회사 Power Amplifier Circuit and Method for Envelope Modulation of High Frequency Signals
US7720506B1 (en) 2006-07-28 2010-05-18 Rockwell Collins, Inc. System and method of providing antenna specific front ends for aviation software defined radios
US7831255B1 (en) 2006-07-31 2010-11-09 Rockwell Collins, Inc. System and method of providing automated availability and integrity verification for aviation software defined radios
US7724484B2 (en) * 2006-12-29 2010-05-25 Cobham Defense Electronic Systems Corporation Ultra broadband 10-W CW integrated limiter
JP2009088770A (en) * 2007-09-28 2009-04-23 Renesas Technology Corp Rf amplifier device
US7880558B2 (en) * 2008-08-29 2011-02-01 Motorola, Inc. Method and apparatus for adjusting load impedance of a distributed amplifier
KR102051846B1 (en) 2012-07-31 2019-12-05 삼성디스플레이 주식회사 Display driving circuit and display device having them
CN103368601B (en) * 2013-06-03 2015-09-23 深圳清华大学研究院 Wireless communication transceiver front end
KR101661151B1 (en) * 2015-09-10 2016-09-29 국방과학연구소 Nonuniform distributed power amplifier having tapered capacitors
CN106533366A (en) * 2016-11-16 2017-03-22 中国电子科技集团公司第四十研究所 Novel high-frequency broadband power amplifier
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CN107528555B (en) * 2017-08-09 2020-10-27 四川九洲电器集团有限责任公司 Distributed amplifier

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Publication number Publication date
AU2003265286A1 (en) 2004-02-23
KR101031986B1 (en) 2011-05-02
US6614307B1 (en) 2003-09-02
CN1675831A (en) 2005-09-28
JP4313759B2 (en) 2009-08-12
JP2005535227A (en) 2005-11-17
KR20050035254A (en) 2005-04-15
CN100557957C (en) 2009-11-04

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