WO2003081960A1 - Interface for digital communication - Google Patents

Interface for digital communication Download PDF

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Publication number
WO2003081960A1
WO2003081960A1 PCT/IB2003/000661 IB0300661W WO03081960A1 WO 2003081960 A1 WO2003081960 A1 WO 2003081960A1 IB 0300661 W IB0300661 W IB 0300661W WO 03081960 A1 WO03081960 A1 WO 03081960A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
interface
circuit part
sequence
digital pulses
Prior art date
Application number
PCT/IB2003/000661
Other languages
French (fr)
Inventor
Marcel Beij
Arnold W. Buij
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP03706777A priority Critical patent/EP1491076B1/en
Priority to DE60320545T priority patent/DE60320545T2/en
Priority to US10/508,452 priority patent/US20050152439A1/en
Priority to AU2003208488A priority patent/AU2003208488A1/en
Priority to JP2003579512A priority patent/JP2005521353A/en
Publication of WO2003081960A1 publication Critical patent/WO2003081960A1/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/175—Controlling the light source by remote control
    • H05B47/18—Controlling the light source by remote control via data-bus transmission

Definitions

  • the invention relates to an interface for digital communication comprising input terminals for receiving a first signal comprising a first sequence of digital pulses from a master, a circuit part I for generating a second signal comprising a second sequence of digital pulses out of the first signal, output terminals for supplying the second sequence of digital pulses to a slave.
  • Such an interface is known from a digital interface system that is known as Digital Addressable Lighting Interface (DALI).
  • DALI Digital Addressable Lighting Interface
  • a light emitting diode is coupled between the output terminals and the circuit part I comprises a current limiter.
  • the light emitting diode is part of one or more optocouplers that function as an opto-isolator making it possible for one master to control more than one slave.
  • DALI uses bi-phase encoding pulses. This means that a data bit is built up of a complementary pair of pulses so that every data bit has a "high/low ratio" that is substantially equal to 1.
  • the current limiter conducts and limits a current that flows through the light emitting diode when the first signal is high.
  • this current has a rise time, being the time interval needed to reach its maximal value, and a fall time, being the time interval needed for the current to decrease from its maximal value to zero.
  • rise and fall times are strongly influenced by the maximal amplitude of the digital pulses belonging to the first sequence.
  • this maximal amplitude that is often referred to as the bus voltage, varies very much.
  • An important disadvantage of the known interface is that the combination of rise and fall time, the bus voltage and the opto-isolator change the "high/low ratio" of the signal to such an extent that the second signal is relatively often not recognized as a DALI signal by the slave.
  • the invention aims to provide an interface that generates a second signal that has a proper "high/low ratio" irrespective of the bus voltage.
  • An interface as mentioned in the opening paragraph is therefore in accordance with the invention characterized in that the interface further comprises a circuit part II for generating a reference signal that represents the highest amplitude of the digital pulses belonging to the first sequence and for activating circuit part I when the amplitude of the first signal is higher than the reference signal and for deactivating circuit part I when the amplitude of the first signal is lower than the reference signal. It has been found that the "high/low-ratio" of the second signal generated by an interface according to the invention is very close to "1" irrespective of the bus voltage.
  • circuit part I comprises a current limiter.
  • the circuit part II comprises first unidirectional means and capacitive means for sampling and storing the highest amplitude of the digital pulses belonging to the first sequence.
  • the circuit part II additionally comprises a voltage divider and second unidirectional means.
  • the interface is preferably further equipped with a light emitting diode coupled between the output terminals.
  • FIG. 1 shows an embodiment of an interface according to the invention.
  • Kl and K2 are input terminals for receiving a first signal comprising a first sequence of digital pulses from a master.
  • Input terminals Kl and K2 are connected by means of a series arrangement of diode Dl and capacitor Cl.
  • diode Dl forms first unidirectional means and capacitor Cl forms capacitive means.
  • capacitor Cl and diode Dl form means for sampling and storing the highest amplitude of the digital pulses belonging to the first sequence.
  • Capacitor Cl is shunted by a series arrangement of ohmic resistors R4 and R5 that forms a voltage divider.
  • a common terminal of ohmic resistors R4 and R5 is connected to an anode of diode D2 forming second unidirectional means.
  • Input terminals Kl and K2 are also connected by means of a series arrangement of PNP transistor Tl, ohmic resistor R2 and light emitting diode LED that forms part of an optocoupler during operation of the interface.
  • the series arrangement of PNP transistor Tl and ohmic resistor R2 is shunted by a series arrangement of ohmic resistor Rl and PNP transistor T2.
  • An emitter of PNP transistor T2 is connected to a basis of PNP transistor Tl.
  • a basis of PNP transistor T2 is connected to a first end of ohmic resistor R3 and to a cathode of diode D2.
  • a further end of ohmic resistor R3 is connected to a collector of PNP transistor Tl.
  • Ohmic resistors Rl, R2 and R3 together with PNP transistors Tl and T2 form a current limiter that functions as a circuit part I for generating a second signal comprising a second sequence of digital pulses out of the first signal.
  • Capacitor Cl, ohmic resistors R4 and R5 and diodes Dl and D2 together form a circuit part II for generating a reference signal that represents the highest amplitude of the digital pulses belonging to the first sequence and for activating circuit part I when the amplitude of the first signal is higher than the reference signal and for deactivating circuit part I when the amplitude of the first signal is lower than the reference signal.
  • the operation of the interface shown in Fig. 1 is as follows.
  • the voltage between input terminals Kl and K2 equals the bus voltage.
  • a first signal comprising a first sequence of digital pulses is present at the input terminals
  • the voltage between the input terminals changes between the bus voltage and substantially zero.
  • Capacitor Cl is charged to a voltage that is substantially equal to the bus voltage.
  • Via resistors R4 and R5 and diode D2 a reference signal is generated that is a predetermined fraction of the bus voltage and is present at the basis of PNP transistor T2.
  • the current limiter formed by ohmic resistors Rl, R2 and R3 and PNP transistors Tl and T2 will only become conductive when the first signal has an amplitude that is higher than the reference signal and will become non-conductive when the first signal has amplitude that is lower than the reference signal.
  • the reference signal is proportional to the bus voltage and will change when the bus voltage changes.
  • the first interface was a practical embodiment of the interface shown in Fig. 1 while the second interface did not comprise the circuit part II but was otherwise identical to the first interface.
  • the "high/low ratios" of the second signal generated by both interfaces out of the same first signal were measured for different bus voltages. For a bus voltage of 20 V it was found that the first interface generated a second signal with a "high/low-ratio" of 52/48 while the second interface generated a second signal with a "high/low-ratio" of 55/45. For a bus voltage of 16 N the respective "high/low-ratios" were 51/49 and 54/46.

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  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
  • Logic Circuits (AREA)
  • Optical Communication System (AREA)

Abstract

In a digital interface comprising a current limiter, a reference voltage proportional to the bus voltage is generated and the current limiter is switched on when the incoming digital signal is higher than the reference voltage and switched of when the incoming signal is smaller than the reference voltage. The 'high/low-ratio' of the digital signal at the output of the interface is substantially improved by the use of the reference voltage.

Description

INTERFACE FOR DIGITAL COMMUNICATION
The invention relates to an interface for digital communication comprising input terminals for receiving a first signal comprising a first sequence of digital pulses from a master, a circuit part I for generating a second signal comprising a second sequence of digital pulses out of the first signal, output terminals for supplying the second sequence of digital pulses to a slave.
Such an interface is known from a digital interface system that is known as Digital Addressable Lighting Interface (DALI). In the known interface a light emitting diode is coupled between the output terminals and the circuit part I comprises a current limiter. The light emitting diode is part of one or more optocouplers that function as an opto-isolator making it possible for one master to control more than one slave. DALI uses bi-phase encoding pulses. This means that a data bit is built up of a complementary pair of pulses so that every data bit has a "high/low ratio" that is substantially equal to 1. h the known interface the current limiter conducts and limits a current that flows through the light emitting diode when the first signal is high. However, this current has a rise time, being the time interval needed to reach its maximal value, and a fall time, being the time interval needed for the current to decrease from its maximal value to zero. These rise and fall times are strongly influenced by the maximal amplitude of the digital pulses belonging to the first sequence. In practice this maximal amplitude, that is often referred to as the bus voltage, varies very much. An important disadvantage of the known interface is that the combination of rise and fall time, the bus voltage and the opto-isolator change the "high/low ratio" of the signal to such an extent that the second signal is relatively often not recognized as a DALI signal by the slave.
The invention aims to provide an interface that generates a second signal that has a proper "high/low ratio" irrespective of the bus voltage.
An interface as mentioned in the opening paragraph is therefore in accordance with the invention characterized in that the interface further comprises a circuit part II for generating a reference signal that represents the highest amplitude of the digital pulses belonging to the first sequence and for activating circuit part I when the amplitude of the first signal is higher than the reference signal and for deactivating circuit part I when the amplitude of the first signal is lower than the reference signal. It has been found that the "high/low-ratio" of the second signal generated by an interface according to the invention is very close to "1" irrespective of the bus voltage.
Good results have been obtained for embodiments of an interface according to the invention, wherein the circuit part I comprises a current limiter.
In a preferred embodiment of an interface according to the invention, the circuit part II comprises first unidirectional means and capacitive means for sampling and storing the highest amplitude of the digital pulses belonging to the first sequence. Thus part of the circuit part II is realized in a simple and dependable manner. Preferably the circuit part II additionally comprises a voltage divider and second unidirectional means.
When the interface is meant to enable communication between one master and more than one slave, the interface is preferably further equipped with a light emitting diode coupled between the output terminals.
An embodiment of an interface according to the invention will be explained making reference to a drawing. In the drawing Fig. 1 shows an embodiment of an interface according to the invention.
In Fig. 1, Kl and K2 are input terminals for receiving a first signal comprising a first sequence of digital pulses from a master. Input terminals Kl and K2 are connected by means of a series arrangement of diode Dl and capacitor Cl. In this embodiment diode Dl forms first unidirectional means and capacitor Cl forms capacitive means. Together capacitor Cl and diode Dl form means for sampling and storing the highest amplitude of the digital pulses belonging to the first sequence. Capacitor Cl is shunted by a series arrangement of ohmic resistors R4 and R5 that forms a voltage divider. A common terminal of ohmic resistors R4 and R5 is connected to an anode of diode D2 forming second unidirectional means. Input terminals Kl and K2 are also connected by means of a series arrangement of PNP transistor Tl, ohmic resistor R2 and light emitting diode LED that forms part of an optocoupler during operation of the interface. The series arrangement of PNP transistor Tl and ohmic resistor R2 is shunted by a series arrangement of ohmic resistor Rl and PNP transistor T2. An emitter of PNP transistor T2 is connected to a basis of PNP transistor Tl. A basis of PNP transistor T2 is connected to a first end of ohmic resistor R3 and to a cathode of diode D2. A further end of ohmic resistor R3 is connected to a collector of PNP transistor Tl. Ohmic resistors Rl, R2 and R3 together with PNP transistors Tl and T2 form a current limiter that functions as a circuit part I for generating a second signal comprising a second sequence of digital pulses out of the first signal. Capacitor Cl, ohmic resistors R4 and R5 and diodes Dl and D2 together form a circuit part II for generating a reference signal that represents the highest amplitude of the digital pulses belonging to the first sequence and for activating circuit part I when the amplitude of the first signal is higher than the reference signal and for deactivating circuit part I when the amplitude of the first signal is lower than the reference signal.
The operation of the interface shown in Fig. 1 is as follows. When the interface is in operation but no communication is taking place, the voltage between input terminals Kl and K2 equals the bus voltage. When a first signal comprising a first sequence of digital pulses is present at the input terminals, the voltage between the input terminals changes between the bus voltage and substantially zero. Capacitor Cl is charged to a voltage that is substantially equal to the bus voltage. Via resistors R4 and R5 and diode D2 a reference signal is generated that is a predetermined fraction of the bus voltage and is present at the basis of PNP transistor T2. As a result the current limiter formed by ohmic resistors Rl, R2 and R3 and PNP transistors Tl and T2 will only become conductive when the first signal has an amplitude that is higher than the reference signal and will become non-conductive when the first signal has amplitude that is lower than the reference signal. It is important to note that the reference signal is proportional to the bus voltage and will change when the bus voltage changes. When the current limiter is conductive, a current flows through light emitting diode LED causing the light emitting diode LED to emit light. This light is received by one or more light sensitive cells that form one or more optocouplers together with light emitting diode LED. The current through the LED forms the second signal.
An experiment was conducted in which two interfaces were used. The first interface was a practical embodiment of the interface shown in Fig. 1 while the second interface did not comprise the circuit part II but was otherwise identical to the first interface. The "high/low ratios" of the second signal generated by both interfaces out of the same first signal were measured for different bus voltages. For a bus voltage of 20 V it was found that the first interface generated a second signal with a "high/low-ratio" of 52/48 while the second interface generated a second signal with a "high/low-ratio" of 55/45. For a bus voltage of 16 N the respective "high/low-ratios" were 51/49 and 54/46. For a bus voltage of 8 V the respective "high/low-ratios" were 51/49 and 56/44. It can be concluded that the circuit part II that is present in an interface according to the invention improves the "high/low-ratio" of the second signal substantially for a wide range of bus voltages.

Claims

CLAIMS:
1. Interface for digital communication comprising input terminals for receiving a first signal comprising a first sequence of digital pulses from a master, a circuit part I for generating a second signal comprising a second sequence of digital pulses out of the first signal, output terminals for supplying the second sequence of digital pulses to a slave, characterized in that the interface further comprises a circuit part II for generating a reference signal that represents the highest amplitude of the digital pulses belonging to the first sequence and for activating circuit part I when the amplitude of the first signal is higher than the reference signal and for deactivating circuit part I when the amplitude of the first signal is lower than the reference signal.
2. Interface according to claim 1 , wherein the circuit part I comprises a current limiter.
3. Interface according to claim 1 or 2, wherein the circuit part II comprises first unidirectional means and capacitive means for sampling and storing the highest amplitude of the digital pulses belonging to the first sequence.
4. Interface according to claim 3, wherein the circuit part II further comprises a voltage divider and second unidirectional means.
5. Interface according to one or more of the previous claims, wherein the interface is further equipped with a light emitting diode coupled between the output terminals.
PCT/IB2003/000661 2002-03-26 2003-02-26 Interface for digital communication WO2003081960A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP03706777A EP1491076B1 (en) 2002-03-26 2003-02-26 Interface for digital communication
DE60320545T DE60320545T2 (en) 2002-03-26 2003-02-26 INTERFACE FOR DIGITAL COMMUNICATION
US10/508,452 US20050152439A1 (en) 2002-03-26 2003-02-26 Interface for digital communication
AU2003208488A AU2003208488A1 (en) 2002-03-26 2003-02-26 Interface for digital communication
JP2003579512A JP2005521353A (en) 2002-03-26 2003-02-26 Interface for digital communication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02076185 2002-03-26
EP02076185.4 2002-03-26

Publications (1)

Publication Number Publication Date
WO2003081960A1 true WO2003081960A1 (en) 2003-10-02

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ID=28051812

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/000661 WO2003081960A1 (en) 2002-03-26 2003-02-26 Interface for digital communication

Country Status (8)

Country Link
US (1) US20050152439A1 (en)
EP (1) EP1491076B1 (en)
JP (1) JP2005521353A (en)
CN (1) CN1643995A (en)
AT (1) ATE393565T1 (en)
AU (1) AU2003208488A1 (en)
DE (1) DE60320545T2 (en)
WO (1) WO2003081960A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008130840A1 (en) * 2007-04-18 2008-10-30 Lutron Electronics Company, Inc. Communication circuit for a digital electronic dimming ballast

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7373533B2 (en) * 2005-09-30 2008-05-13 Silicon Laboratories Programmable I/O cell capable of holding its state in power-down mode
AT13367U1 (en) * 2012-04-26 2013-11-15 Tridonic Gmbh & Co Kg Interface with send and receive branch
JP6382825B2 (en) 2012-10-17 2018-08-29 フィリップス ライティング ホールディング ビー ヴィ Digital communication receiver interface circuit for line pairs with duty cycle imbalance compensation
RU2713399C2 (en) * 2015-04-27 2020-02-05 Филипс Лайтинг Холдинг Б.В. Lighting control module, lighting system using same, and dimming level adjustment method
US10862298B2 (en) 2018-04-11 2020-12-08 Schweitzer Engineering Laboratories, Inc. Duty cycle modulated universal binary input circuit with reinforced isolation
US10602590B1 (en) 2018-10-23 2020-03-24 Abl Ip Holding Llc Isolation of digital signals in a lighting control transceiver
US11934169B2 (en) 2021-05-05 2024-03-19 Schweitzer Engineering Laboratories, Inc. Configurable binary circuits for protection relays in electric power systems

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3825896A (en) * 1972-05-01 1974-07-23 Texas Instruments Inc Computer input/output interface systems using optically coupled isolators
US4197471A (en) * 1977-09-29 1980-04-08 Texas Instruments Incorporated Circuit for interfacing between an external signal and control apparatus
US4433256A (en) * 1982-07-06 1984-02-21 Motorola, Inc. Limiter with dynamic hysteresis
US5043607A (en) * 1989-06-23 1991-08-27 Thomson Composants Microondes Output interface circuit between two circuits of different natures
WO2002013401A2 (en) * 2000-08-09 2002-02-14 Telefonaktiebolaget Lm Ericsson (Publ) Electronic circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4918296A (en) * 1987-03-06 1990-04-17 Omron Tateisi Electronics Company Article identifying system
KR100405023B1 (en) * 2000-12-05 2003-11-07 옵티시스 주식회사 Optical communication interface module for universal serial bus
WO2004047151A2 (en) * 2002-11-20 2004-06-03 Bookham Technology, Plc Optical transceiver module with improved ddic and methods of use

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3825896A (en) * 1972-05-01 1974-07-23 Texas Instruments Inc Computer input/output interface systems using optically coupled isolators
US4197471A (en) * 1977-09-29 1980-04-08 Texas Instruments Incorporated Circuit for interfacing between an external signal and control apparatus
US4433256A (en) * 1982-07-06 1984-02-21 Motorola, Inc. Limiter with dynamic hysteresis
US5043607A (en) * 1989-06-23 1991-08-27 Thomson Composants Microondes Output interface circuit between two circuits of different natures
WO2002013401A2 (en) * 2000-08-09 2002-02-14 Telefonaktiebolaget Lm Ericsson (Publ) Electronic circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008130840A1 (en) * 2007-04-18 2008-10-30 Lutron Electronics Company, Inc. Communication circuit for a digital electronic dimming ballast
US7764479B2 (en) 2007-04-18 2010-07-27 Lutron Electronics Co., Inc. Communication circuit for a digital electronic dimming ballast
US7983012B2 (en) 2007-04-18 2011-07-19 Lutron Electronics Co., Inc. Communication circuit for a digital electronic dimming ballast

Also Published As

Publication number Publication date
AU2003208488A1 (en) 2003-10-08
DE60320545T2 (en) 2008-10-23
JP2005521353A (en) 2005-07-14
CN1643995A (en) 2005-07-20
ATE393565T1 (en) 2008-05-15
EP1491076B1 (en) 2008-04-23
DE60320545D1 (en) 2008-06-05
US20050152439A1 (en) 2005-07-14
EP1491076A1 (en) 2004-12-29

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