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Method and system for managing hardware resources to implement system functions using an adaptive computing architecture


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WO2003054722A3 PCT/US2002/039566 US0239566W WO03054722A3 WO 2003054722 A3 WO2003054722 A3 WO 2003054722A3 US 0239566 W US0239566 W US 0239566W WO 03054722 A3 WO03054722 A3 WO 03054722A3
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French (fr)
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WO2003054722A2 (en )
Robert Plunkett
Ghobad Heindari
Paul L Master
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Quicksilver Tech Inc
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    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/177Initialisation or configuration control
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
    • Y02B60/00Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10Energy efficient computing
    • Y02B60/12Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1207Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply acting upon the main processing unit
    • Y02B60/00Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10Energy efficient computing
    • Y02B60/12Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1225Access, addressing or allocation within memory systems or architectures, e.g. to reduce power consumption or heat production, or to increase battery life
    • Y02D10/12
    • Y02D10/13


The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions.
PCT/US2002/039566 2001-03-22 2002-12-10 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture WO2003054722A3 (en)

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US10/015,530 2001-12-12
US10015530 US7752419B1 (en) 2001-03-22 2001-12-12 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

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