WO2003049385A2 - Method and arrangement for data processing in a communication system - Google Patents

Method and arrangement for data processing in a communication system Download PDF

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Publication number
WO2003049385A2
WO2003049385A2 PCT/GB2002/005526 GB0205526W WO03049385A2 WO 2003049385 A2 WO2003049385 A2 WO 2003049385A2 GB 0205526 W GB0205526 W GB 0205526W WO 03049385 A2 WO03049385 A2 WO 03049385A2
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Prior art keywords
data
processing
configuration
communication system
processing means
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PCT/GB2002/005526
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French (fr)
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WO2003049385A3 (en
Inventor
Joseph Keith Charles Moloney
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IPWireless Inc
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IPWireless Inc
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Priority to EP02785622.8A priority Critical patent/EP1491008B1/en
Priority to AU2002350909A priority patent/AU2002350909A1/en
Priority to EP10184548.5A priority patent/EP2309697B1/en
Publication of WO2003049385A2 publication Critical patent/WO2003049385A2/en
Publication of WO2003049385A3 publication Critical patent/WO2003049385A3/en
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/34—Network arrangements or protocols for supporting network services or applications involving the movement of software or configuration parameters 
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/06—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information

Definitions

  • This invention relates to data processing in communication systems, and particularly though not exclusively to Coded Composite Transport Channel (CCTrCH) processing in packet-based UTRA TDD (UMTS - Universal Mobile Telecommunication System - Terrestrial Radio Access systems operating in Time Division Duplex mode) .
  • CCTrCH Coded Composite Transport Channel
  • UMTS Terrestrial Radio Access Network there are two modes of operation Frequency Division Duplex (FDD) and Time Division Duplex (TDD) .
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • users are separated in both the code domain and time domain.
  • the time domain UTRA framing has 4096 radio frames which make up a super frame with each radio frame consisting of 15 timeslots. A timeslot can be allocated to either Uplink (UL) or downlink (DL) transmission.
  • UTRA specifies the processing that is applied to Transport Channel (TrCH) data by Layer 1 (LI) to build up CCTrCHs. These CCTrCHs are mapped onto timeslots.
  • TrCH Transport Channel
  • LI Layer 1
  • Each CCTrCH has a particular set of characteristics, which change dynamically for each CCTrCH that is processed. Possible configuration parameters that may be applied dynamically to each CCTrCH include: number of
  • TrCHs in a CCTrCH are TrCHs in a CCTrCH; CRC length; transport block size; type of channel coding; Transmission Time Interleave (TTI) period; and amount of physical resource.
  • An implementation of a CCTrCH processing stack may contain a mixture of hardware and software implementations of individual processing steps. Each processing step requires configuration information.
  • the controlling entity must store the configuration parameters for the CCTrCH; 2) the controlling entity must keep track of the CCTrCH as it is processed by each of the processing steps and recall the configuration parameters in order that they can be applied along with the data to the next processing step; and 3) as the amount of output data for a process is not necessarily the same as the input data the controlling entity must calculate and control the following process with this data.
  • FIG. 1 shows a block schematic diagram illustrating time domain UTRA framing
  • FIG. 2 shows a block schematic diagram illustrating multiplexing and channel coding in UTRA
  • FIG. 3 shows a block schematic diagram illustrating an stack or arrangement for processing of CCTrCH data in a packet data UTRA TDD system incorporating the present invention
  • FIG. 4 shows a block-schematic diagram of a UTRA TDD system in which the invention is used.
  • UTRA Frequency Division Duplex FDD
  • TDD Time Division Duplex
  • UL Uplink
  • DL Downlink
  • UTRA specifies the processing that is applied to the Transport Channel (TrCH) data by Layer 1 (LI), as shown in FIG. 2.
  • Transport Blocks (blocks of a defined number of bits) are submitted by the media access control (MAC) to Ll for processing.
  • a Transport Block typically corresponds to a MAC protocol data unit (PDU) or corresponding unit.
  • Layer 1 processes each Transport Block as shown in FIG. 2 to build up CCTrCHs. Firstly, cyclic redundancy check (CRC) attachment is performed at 205; then, transport block (TrBk) concatenation/code block segmentation is performed at 210. Next, channel coding is performed at 215; then, radio frame equalisation is performed at 220. Next, first interleaving is performed at 225; then, radio frame segmentation is performed at 230, and rate matching is performed at 235. A number of rate-matched data streams are multiplexed together on a single transport channel at 240; then, the resultant multiplexed data stream is processed by bit scrambling at 245.
  • CRC cyclic redundancy check
  • TrBk transport block concatenation/code block segmentation
  • channel coding is performed at 215; then, radio frame equalisation is performed at 220.
  • first interleaving is performed at 225; then, radio frame segmentation is performed at 230, and rate matching is performed at 235.
  • the bit- scrambled data stream is segmented into a number of physical channels at 250; then, second interleaving is performed on each of the segmented physical channel data streams at 255. Finally, physical channel mapping is performed at 260 to produce a number of CCTrCHs for physical channels such as PhCH#l and PhCH#2. These CCTrCHs are mapped onto timeslots in known manner.
  • Each CCTrCH has a particular set of characteristics. These characteristics change dynamically for each CCTrCH that is processed.
  • Type of Channel coding 5) Transmission Time Interleave (TTI) period 6) Amount of physical resource
  • an implementation of a CCTrCH processing stack may contain a mixture of hardware and software implementations of the individual processing steps shown in FIG. 2. Each processing step requires configuration information.
  • the conventional approach is to use a centralized controller.
  • this approach has a number of disadvantages : •
  • the controlling entity must store the configuration parameters for the CCTrCH.
  • the controlling entity must keep track of the CCTrCH as it is processed by each of the processing steps and recall the configuration parameters in order that they can be applied along with the data to the next processing step.
  • the present invention at least in the preferred embodiment described below, utilises a method for simplifying the problem of control of configuration parameters in a CCTrCH processing stack, though it can equally be applied to any processing stack that has dynamic configuration parameters.
  • a CCTrCH configuration header 310 is attached to each of the CCTrCH data blocks when applying the data to the CCTrCH processing stack for processing CCTrCH information for communication across the UTRA TDD system's air interface.
  • the CCTrCH configuration header 310 is internally derived (e.g., within a receiver by LI Signalling) and, in a preferred embodiment, includes a TFI (Transport Format Indicator) passed over the air-interface.
  • TFI Transport Format Indicator
  • the header 310 is read along with the input data 320 by the process in order to gain the configuration data the process requires.
  • the same header 310 is then attached to its output data 320 (to form an integral CCTrCH data block 330) for use by the next process in the CCTrCH processing stack.
  • the processing stage may also add extra configuration data (e.g., output data size) to the configuration header, that can save recalculation of certain parameters.
  • a CCTrCH configuration header 310 is attached to every CCTrCH data block that is applied to a
  • each processing stage in the CCTrCH processing stack interrogates the CCTrCH configuration header 310 in order to gain the configuration data it requires;
  • each processing stage in the CCTrCH processing stack attaches the header 310 to its output data 320;
  • each processing stage may add extra configuration data to the CCTrCH header 310.
  • the method and arrangement utilising configuration headers described above provides the advantages that the controlling entity does not need to store the configuration parameters for the CCTrCH, since they are passed in the configuration header; nor does the controlling entity need to keep track of the CCTrCH as it is processed by each of the processing steps; nor does the controlling entity need to calculate and control a following process with data output from a previous process, since the processing proceeds methodically from one process to another using the configuration headers.
  • CCTrCH data may alternatively be carried out (in part or in whole) in hardware, for example in the form of an integrated circuit (not shown) such as an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Integrated Circuit) .
  • an integrated circuit not shown
  • FPGA Field Programmable Gate Array
  • ASIC Application Specific Integrated Integrated Circuit
  • a UTRA TDD system 400 includes a user terminal 410 (commonly referred to as ⁇ User Equipment' ' ) which communicates over a CDMA radio link 420 with a base station 430 (commonly referred to as a Node B' ) .
  • the Node B 430 is controlled by a radio network controller 440, which communicates with other system infrastructure shown collectively as 450.
  • processing stack or arrangement 300 described above for processing CCTrCH data may be advantageously implemented in either a UE 410 or a Node B 430 of the system as shown in the figure.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Communication Control (AREA)

Abstract

A method and arrangement (300) for processing data in a communication system (400), using a configuration header (310) containing configuration data for use in processing data through a plurality of processes including a first process and a second process; and passing the configuration header (310) with inter-process data (320) from the first process to the second process, whereby the second process extracts configuration data from the configuration header passed from the first process. Extra data may also be added to the configuration header to save recalculation of certain parameters. This avoids disadvantages of using a central controller and allows processing to proceed from one processing step to another without requiring prior knowledge of the processing latencies of each processing step.

Description

METHOD AND ARRANGEMENT FOR DATA PROCESSING IN A
COMMUNICATION SYSTEM
Field of the Invention
This invention relates to data processing in communication systems, and particularly though not exclusively to Coded Composite Transport Channel (CCTrCH) processing in packet-based UTRA TDD (UMTS - Universal Mobile Telecommunication System - Terrestrial Radio Access systems operating in Time Division Duplex mode) .
Background of the Invention
In a UMTS Terrestrial Radio Access Network (UTRAN) there are two modes of operation Frequency Division Duplex (FDD) and Time Division Duplex (TDD) . In UTRA TDD, which is packet-based, users are separated in both the code domain and time domain. The time domain UTRA framing has 4096 radio frames which make up a super frame with each radio frame consisting of 15 timeslots. A timeslot can be allocated to either Uplink (UL) or downlink (DL) transmission.
In a typical TDD system the UL and DL transmissions have to be synchronized to reduce interference. In addition DL broadcast signaling and UL random access signaling has to be supported. This leads to a partitioning of the radio frame with individual timeslots being dedicated for use either for DL or UL. UTRA specifies the processing that is applied to Transport Channel (TrCH) data by Layer 1 (LI) to build up CCTrCHs. These CCTrCHs are mapped onto timeslots.
Each CCTrCH has a particular set of characteristics, which change dynamically for each CCTrCH that is processed. Possible configuration parameters that may be applied dynamically to each CCTrCH include: number of
TrCHs in a CCTrCH; CRC length; transport block size; type of channel coding; Transmission Time Interleave (TTI) period; and amount of physical resource.
An implementation of a CCTrCH processing stack may contain a mixture of hardware and software implementations of individual processing steps. Each processing step requires configuration information.
The conventional approach has been to use a centralized controller for this processing. However this approach has the following disadvantages:
1) the controlling entity must store the configuration parameters for the CCTrCH; 2) the controlling entity must keep track of the CCTrCH as it is processed by each of the processing steps and recall the configuration parameters in order that they can be applied along with the data to the next processing step; and 3) as the amount of output data for a process is not necessarily the same as the input data the controlling entity must calculate and control the following process with this data.
This conventional approach becomes complex when the configuration data changes dynamically for each CCTrCH as it is processed and the latency through each process changes depending on the configuration itself.
A need therefore exists for processing of data in a communication system wherein the abovementioned disadvantage (s) may be alleviated.
Statement of Invention
In accordance with a first aspect of the present invention there is provided a method, for data processing in a communication system, as claimed in claim 1.
In accordance with a second aspect of the present invention there is provided an arrangement, for data processing in a communication system, as claimed in claim 6.
In accordance with a third aspect of the present invention there is provided a communication system as claimed in claim 11. Brief Description of the Drawings
One method and arrangement for processing of CCTrCH data in a packet data UTRA TDD system incorporating the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
FIG. 1 shows a block schematic diagram illustrating time domain UTRA framing;
FIG. 2 shows a block schematic diagram illustrating multiplexing and channel coding in UTRA;
FIG. 3 shows a block schematic diagram illustrating an stack or arrangement for processing of CCTrCH data in a packet data UTRA TDD system incorporating the present invention; and
FIG. 4 shows a block-schematic diagram of a UTRA TDD system in which the invention is used.
Description of Preferred Embodiment
In a UMTS Terrestrial Radio Access Network (UTRAN) there are two modes of operation: UTRA Frequency Division Duplex (FDD) and UTRA Time Division Duplex (TDD) . In UTRA TDD users are separated in both the code domain and time domain. In the time domain employed in UTRA framing, illustrated in FIG. 1, 4096 radio frames make up a super frame with each radio frame consisting of 15 timeslots. A timeslot can be allocated to either Uplink (UL) or Downlink (DL) transmission.
In a typical TDD system the UL and DL transmissions have to be synchronized to reduce interference. In addition DL broadcast signaling and UL random access signaling has to be supported. This leads to a possible partitioning of the radio frame as shown below:
Figure imgf000007_0001
UTRA specifies the processing that is applied to the Transport Channel (TrCH) data by Layer 1 (LI), as shown in FIG. 2.
Transport Blocks (blocks of a defined number of bits) are submitted by the media access control (MAC) to Ll for processing. A Transport Block typically corresponds to a MAC protocol data unit (PDU) or corresponding unit.
Layer 1 processes each Transport Block as shown in FIG. 2 to build up CCTrCHs. Firstly, cyclic redundancy check (CRC) attachment is performed at 205; then, transport block (TrBk) concatenation/code block segmentation is performed at 210. Next, channel coding is performed at 215; then, radio frame equalisation is performed at 220. Next, first interleaving is performed at 225; then, radio frame segmentation is performed at 230, and rate matching is performed at 235. A number of rate-matched data streams are multiplexed together on a single transport channel at 240; then, the resultant multiplexed data stream is processed by bit scrambling at 245. The bit- scrambled data stream is segmented into a number of physical channels at 250; then, second interleaving is performed on each of the segmented physical channel data streams at 255. Finally, physical channel mapping is performed at 260 to produce a number of CCTrCHs for physical channels such as PhCH#l and PhCH#2. These CCTrCHs are mapped onto timeslots in known manner.
Each CCTrCH has a particular set of characteristics. These characteristics change dynamically for each CCTrCH that is processed. The following lists examples of some of the possible configuration parameters that may be applied dynamically to each CCTrCH:
1) Number of TrCHs in a CCTrCH
2) CRC length
3) Transport Block Size
4) Type of Channel coding 5) Transmission Time Interleave (TTI) period 6) Amount of physical resource
In practice, an implementation of a CCTrCH processing stack may contain a mixture of hardware and software implementations of the individual processing steps shown in FIG. 2. Each processing step requires configuration information.
The conventional approach is to use a centralized controller. However, this approach has a number of disadvantages : • The controlling entity must store the configuration parameters for the CCTrCH.
• The controlling entity must keep track of the CCTrCH as it is processed by each of the processing steps and recall the configuration parameters in order that they can be applied along with the data to the next processing step.
• As the amount of output data for a process is not necessarily the same as the input data the controlling entity must calculate and control the following process with this data.
This approach becomes complex when the configuration data changes dynamically for each CCTrCH as it is processed, and the latency through each process changes depending on the configuration itself.
The present invention, at least in the preferred embodiment described below, utilises a method for simplifying the problem of control of configuration parameters in a CCTrCH processing stack, though it can equally be applied to any processing stack that has dynamic configuration parameters.
Referring now to FIG. 3, to solve the problems of a centralized controller a CCTrCH configuration header 310 is attached to each of the CCTrCH data blocks when applying the data to the CCTrCH processing stack for processing CCTrCH information for communication across the UTRA TDD system's air interface. The CCTrCH configuration header 310 is internally derived (e.g., within a receiver by LI Signalling) and, in a preferred embodiment, includes a TFI (Transport Format Indicator) passed over the air-interface.
At each stage or processing element of the processing stack or arrangement 300 the header 310 is read along with the input data 320 by the process in order to gain the configuration data the process requires.
The same header 310 is then attached to its output data 320 (to form an integral CCTrCH data block 330) for use by the next process in the CCTrCH processing stack. The processing stage may also add extra configuration data (e.g., output data size) to the configuration header, that can save recalculation of certain parameters.
Thus, it will be understood, in employing the configuration headers 310, in the above method:
1) a CCTrCH configuration header 310 is attached to every CCTrCH data block that is applied to a
CCTrCH processing stack;
2) the CCTrCH configuration header 310 is treated as an integral part of the CCTrCH data 330;
3) each processing stage in the CCTrCH processing stack interrogates the CCTrCH configuration header 310 in order to gain the configuration data it requires;
4) each processing stage in the CCTrCH processing stack attaches the header 310 to its output data 320; and
5) each processing stage may add extra configuration data to the CCTrCH header 310.
It will be understood and appreciated that the method and arrangement utilising configuration headers described above provides the advantages that the controlling entity does not need to store the configuration parameters for the CCTrCH, since they are passed in the configuration header; nor does the controlling entity need to keep track of the CCTrCH as it is processed by each of the processing steps; nor does the controlling entity need to calculate and control a following process with data output from a previous process, since the processing proceeds methodically from one process to another using the configuration headers.
It will also be understood and appreciated that the method and arrangement described above allows CCTrCH processing to be performed, without the need for central control, by proceeding methodically from one processing step to another without prior knowledge of the processing latencies of each processing step.
It will be appreciated that the method described above for processing of CCTrCH data may be carried out in software running on a processor (not shown) , and that the software may be provided as a computer program element carried on any suitable data carrier (also not shown) such as a magnetic or optical computer disc.
It will be also be appreciated that the method described above for processing of CCTrCH data may alternatively be carried out (in part or in whole) in hardware, for example in the form of an integrated circuit (not shown) such as an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Integrated Circuit) .
It will further be appreciated that although the method described above for processing of CCTrCH data has been presented in the context of processing CCTrCH data for transmission, the same technique of using configuration headers passed between successive processing stages may equally be performed in processing received CCTrCH data. Referring now also to FIG. 4, a UTRA TDD system 400 includes a user terminal 410 (commonly referred to as ΛUser Equipment'' ) which communicates over a CDMA radio link 420 with a base station 430 (commonly referred to as a Node B' ) . The Node B 430 is controlled by a radio network controller 440, which communicates with other system infrastructure shown collectively as 450. Such a system (insofar as it has been described up to this point) is well known and need not be described further. However, it will be understood that the processing stack or arrangement 300 described above for processing CCTrCH data may be advantageously implemented in either a UE 410 or a Node B 430 of the system as shown in the figure.
It will further be appreciated that although the invention has been described above in the context of processing CCTrCH data in a UTRA TDD system, the invention may be generally applied to data processing in any communication system. In conclusion, therefore, it will be understood that the use of configuration headers in a data processing in a communication system as described avoids the disadvantages of using a central controller and allows processing to proceed from one processing step to another without requiring prior knowledge of the processing latencies of each processing step.

Claims

Claims
1. A method for processing data in a communication system, the method comprising: providing a configuration header containing configuration data for use in processing data through a plurality of processes including a first process and a second process; and passing the configuration header with inter-process data from the first process to the second process, whereby the second process extracts configuration data from the configuration header passed from the first process.
2. The method of claim 1, wherein the plurality of processes includes a third process, and the method further comprises the second process adding data to the configuration header passed from the first process and passing the resultant header to the third process with inter-process data.
3. The method of claim 1 or 2 wherein the communication system is a packet data wireless communication system.
4. The method of claim 3 wherein the communication system is a UTRA TDD system.
5. The method of claim 4 wherein the method is for processing CCTrCH data.
6. An arrangement for processing data in a communication system, the arrangement comprising: means for providing a configuration header containing configuration data for use in processing data through a plurality of processing means including a first process means and a second processing means; and means for passing the configuration header with inter-process data from the first processing means to the second processing means, whereby the second processing means is arranged to extract configuration data from the configuration header passed from the first processing means.
7. The arrangement of claim 6, wherein the plurality of processing means includes a third processing means, and wherein the second processing means is arranged to add data to the configuration header passed from the first processing means and to pass the resultant header to the third process with inter-process data.
8. The arrangement of claim 6 or 7 wherein the communication system is a packet data wireless communication system.
9. The arrangement of claim 8 wherein the communication system is a UTRA TDD system.
10. The arrangement of claim 9 wherein the arrangement is arranged to process CCTrCH data.
11. A communication system including means for processing data comprising: means for providing a configuration header containing configuration data for use in processing data through a plurality of processing means including a first process means and a second processing means; and means for passing the configuration header with inter-process data from the first processing means to the second processing means, whereby the second processing means is arranged to extract configuration data from the configuration header passed from the first processing means.
12. The system of claim 11, wherein the plurality of processing means includes a third processing means, and wherein the second processing means is arranged to add data to the configuration header passed from the first processing means and to pass the resultant header to the third process with inter-process data.
13. The system of claim 11 or 12 wherein the communication system is a packet data wireless communication system.
14. The system of claim 13 wherein the communication system is a UTRA TDD system.
15. The system of claim 14 wherein the means for processing data is arranged to process CCTrCH data.
16. User equipment for use in a communication system, the user equipment comprising the arrangement of any one of claims 6 to 10.
17. A base station for use in a communication system, the base station comprising the arrangement of any one of claims 6 to 10.
18. A computer program element comprising computer program means for performing substantially the method of any one of claims 1 to 5.
19. An integrated circuit comprising substantially the arrangement of any one of claims 6 to 10.
PCT/GB2002/005526 2001-12-05 2002-12-05 Method and arrangement for data processing in a communication system Ceased WO2003049385A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP02785622.8A EP1491008B1 (en) 2001-12-05 2002-12-05 Method, apparatuses and system for data processing in a UMTS Terrestrial Radio Access (UTRA) communication system
AU2002350909A AU2002350909A1 (en) 2001-12-05 2002-12-05 Method and arrangement for data processing in a communication system
EP10184548.5A EP2309697B1 (en) 2001-12-05 2002-12-05 Method and apparatus for data processing by a user terminal in a wireless communication system

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GB0129103A GB2382960B (en) 2001-12-05 2001-12-05 Method and arrangement for data processing in a communication system
GB0129103.8 2001-12-05

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Publication number Priority date Publication date Assignee Title
US7480276B2 (en) 2001-12-05 2009-01-20 Ipwireless, Inc. Method and arrangement for data processing in a communication system
USRE43926E1 (en) 2001-12-05 2013-01-15 Sony Corporation Method and arrangement for data processing in a communication system

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US7480276B2 (en) 2009-01-20
EP2309697A1 (en) 2011-04-13
EP1491008B1 (en) 2014-10-15
GB0129103D0 (en) 2002-01-23
GB2382960B (en) 2005-03-16
EP2309697B1 (en) 2019-01-30
GB2382960A (en) 2003-06-11
AU2002350909A1 (en) 2003-06-17
AU2002350909A8 (en) 2003-06-17
US20050018710A1 (en) 2005-01-27
EP1491008A2 (en) 2004-12-29
WO2003049385A3 (en) 2003-08-21
EP2276208A1 (en) 2011-01-19
USRE43926E1 (en) 2013-01-15

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