WO2003028218A1 - Fractional-n type frequency synthesizer - Google Patents

Fractional-n type frequency synthesizer Download PDF

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Publication number
WO2003028218A1
WO2003028218A1 PCT/US2002/030279 US0230279W WO03028218A1 WO 2003028218 A1 WO2003028218 A1 WO 2003028218A1 US 0230279 W US0230279 W US 0230279W WO 03028218 A1 WO03028218 A1 WO 03028218A1
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Prior art keywords
output
circuit
input
summer
filter
Prior art date
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PCT/US2002/030279
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French (fr)
Inventor
Kartik Sridharan
Original Assignee
Ashvattha Semiconductor, Inc.
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Publication date
Application filed by Ashvattha Semiconductor, Inc. filed Critical Ashvattha Semiconductor, Inc.
Priority to JP2003531614A priority Critical patent/JP2005505162A/en
Priority to KR10-2004-7004518A priority patent/KR20040073432A/en
Priority to EP02775964A priority patent/EP1446885A4/en
Publication of WO2003028218A1 publication Critical patent/WO2003028218A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0916—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop
    • H03C3/0933—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop using fractional frequency division in the feedback loop of the phase locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0916—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop
    • H03C3/0925—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop applying frequency modulation at the divider in the feedback loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Definitions

  • This relates to a fractional-N type frequency synthesizer.
  • Frequency synthesizers generate an output signal having a frequency that is a multiple of a reference frequency.
  • the operation of the frequency synthesizer is controlled by a phase lock loop (PLL) in which a variable frequency oscillator 2 is locked to the frequency of a known reference frequency 8 by a phase discriminator 6.
  • the oscillator typically is a voltage controlled oscillator (VCO) and the phase discriminator generates an output voltage that is proportional to the phase difference between the known reference frequency and the output of the oscillator.
  • the output voltage of the phase discriminator is applied as an error signal to control the output frequency of the VCO.
  • a variable frequency divisor 4 is used to divide the output frequency before it is compared with the reference frequency.
  • the output frequency from the VCO is an exact multiple of the reference frequency; and, if the divisor is an integer, the smallest increment in the VCO output frequency is equal to the reference frequency.
  • a very low reference frequency is required.
  • a low reference frequency introduces a variety of unacceptable effects.
  • circuits have been devised for dividing the output frequency by a fractional number. The prior art circuit shown in Fig. 2 which is Fig. 1 of U.S.
  • Patent 5,038,117 comprises a voltage controlled oscillator 11, a fractional divider 13, a phase comparator 15 and a filter 17.
  • a control circuit 18 controls the integer component N and the fractional component .F by which the output frequency is divided.
  • N.F is achieved by averaging the divisor such that the output frequency is divided byN for .F of a duty cycle and by N+l for (l-.F) of the duty cycle.
  • a general technique for reducing such phase error is to cascade multiple stages of first or second order Delta-Sigma modulators 310, 320, 330 and supply an output of each stage to digital cancellation logic 340.
  • the modulator comprises first and second summers 412, 413, first and second filters 415, 419 and a quantizer 417.
  • Filter 419 connects an output signal, y(n), from quantizer 417 to a negative input of first summer 412 which combines an input signal x(n) with the filtered output and provides the result to an input to filter 415.
  • Second summer 413 calculates the difference between the signals at the input and the output of quantizer 417 to generate a signal, e(n), representing the quantization error of the quantizer.
  • the noise transfer function is (1 - Z "1 )" 1 , where m is the overall order.
  • FIG. 5 A model of the Delta-Sigma modulator of Fig. 3 is shown in Fig. 5 which is reproduced from Fig. 5(d) of the '117 patent.
  • each of three identical stages 510, 520, 530 comprises first and second summers 512, 513, an integrator 515, a quantizer 517 and a Z "1 delay 519.
  • a digital cancellation logic circuit 540 comprises a first differentiator 542 coupled to the output of the second stage 520, second and third differentiators 544, 546
  • a digital cancellation logic circuit 640 comprises a first differentiator 642, coupled to the carry output of adder 614 of the second stage 620, second and third differentiators 644, 646 coupled in cascade to the carry output of adder 614 of the third stage 630 and summer circuitry coupled to the carry output of the adder 614 of the first stage 610, the output of the first differentiator 642 and the output of the third differentiator 646.
  • the second filter comprises a first summer, first and second filters and a quantizer.
  • the second filter connects an output of the quantizer to the first summer and an output of the summer is connected to an input of the first filter and an output of the first filter is connected to an input to the quantizer.
  • the second filter introduces off- axis zeroes into equations representative of this circuit.
  • the second filter is realized by first and second delay elements connected in cascade, a multiplier and a second summer. An input to the first delay element is connected to the output of the quantizer and an output of the second delay element is connected to an input to the second summer.
  • An input to the multiplier is connected to a node between the first and second delay elements and an output of the multiplier is connected to an input to the second summer.
  • the second summer subtracts the signal from the second delay element from the signal from the multiplier and provides it as an input to the first summer.
  • the invention may also be implemented in software to generate fractional N divisors having desirable spectral characteristics.
  • FIG. 1 is a block diagram of a prior art frequency synthesizer circuit
  • FIG. 2 is a block diagram of a prior art fractional-N divisor frequency synthesizer circuit
  • FIG. 3 is a block diagram of a prior art multistage Delta-Sigma modulator
  • FIG. 4 is a block diagram of one stage of a prior art general Delta-Sigma modulator
  • FIG. 5 is a block diagram of a prior art multistage modulator for use in fractional-N synthesis
  • FIG. 6 is a block diagram of a prior art implementation of the modulator of Fig. 5;
  • FIG. 7 is a block diagram of an illustrative embodiment of a multistage modulator of the present invention.
  • FIG. 8 is a block diagram of an illustrative model of one stage of a modulator of the present invention.
  • Fig. 7 is a block diagram of an illustrative embodiment of the invention.
  • the circuit of Fig. 7 is a three stage modulator suitable for use in generating the divisor in a fractional N frequency synthesizer.
  • Each stage comprises an adder 714 and one or more filter elements.
  • the filter element is a Z "1 delay element 719.
  • the filter element comprises first and second delay elements 721, 723, connected in cascade, a multiplier 725 and a summer 727.
  • An input to the first delay element 721 is connected to the output of the adder and an output of the second delay element 723 is connected to an input to the summer 727.
  • An input to the multiplier 725 is connected to a node between the first and second delay elements 721, 723 and an output of the multiplier is connected to an input to the summer 727.
  • the summer subtracts the signal from the second delay element 723 from the signal from the multiplier 725 and provides it as an input to the adder 714.
  • the output of summer 750 can be shown to be
  • a model of the third stage 730 is shown in Fig. 8.
  • the model comprises summer
  • the second filter connects an output of the quantizer to the summer and an output of the summer is connected to an input of the first filter and an output of the first filter is connected to an input to the quantizer.
  • the second filter introduces off-axis zeroes into equations representative of this circuit.
  • Filter 819 introduces the polynomial term (1 - KZ "1 + Z "2 ) into the z-transform equation representative of the circuit of Fig. 7.
  • the roots or zeroes of this term are
  • ⁇ adders, multipliers and delay elements to form a filter element 719 that is represented by a polynomial having any number of off-axis zeroes.
  • the invention is also not limited to the number of stages of the modulator. While a modulator of three stages has been disclosed for purposes of illustration, the invention may be practiced using any number of stages desired. Further, the invention is not limited to use in the Delta-Sigma modulators

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

In a fractional-N frequency synthesizer (710,720,730), a circuit (730) for generating at least one off-axis zero (725) in an equation representative of the circuit.

Description

FRACTIONAL-N TYPE FREQUENCY SYNTHESIZER
FIELD OF THE INVENTION
This relates to a fractional-N type frequency synthesizer.
BACKGROUND OF THE INVENTION
Frequency synthesizers generate an output signal having a frequency that is a multiple of a reference frequency. In a typical prior art circuit shown in Fig. 1 which is reproduced from Fig. 1 of U.S. Patent 3,217,267, the operation of the frequency synthesizer is controlled by a phase lock loop (PLL) in which a variable frequency oscillator 2 is locked to the frequency of a known reference frequency 8 by a phase discriminator 6. In such arrangement, the oscillator typically is a voltage controlled oscillator (VCO) and the phase discriminator generates an output voltage that is proportional to the phase difference between the known reference frequency and the output of the oscillator. The output voltage of the phase discriminator is applied as an error signal to control the output frequency of the VCO.
To provide for different output frequencies from the VCO, a variable frequency divisor 4 is used to divide the output frequency before it is compared with the reference frequency. As a result, the output frequency from the VCO is an exact multiple of the reference frequency; and, if the divisor is an integer, the smallest increment in the VCO output frequency is equal to the reference frequency. Thus, to provide a small step size between adjacent output frequencies when using an integer divisor, a very low reference frequency is required. A low reference frequency, however, introduces a variety of unacceptable effects. To avoid the use of a low reference frequency, circuits have been devised for dividing the output frequency by a fractional number. The prior art circuit shown in Fig. 2 which is Fig. 1 of U.S. Patent 5,038,117, comprises a voltage controlled oscillator 11, a fractional divider 13, a phase comparator 15 and a filter 17. A control circuit 18 controls the integer component N and the fractional component .F by which the output frequency is divided. As is known in the art, different techniques may be used to effect fractional N division. In one such technique, division by N.F is achieved by averaging the divisor such that the output frequency is divided byN for .F of a duty cycle and by N+l for (l-.F) of the duty cycle.
Further details concerning such fractional-N frequency synthesizers may be found in U.S. Patents 3,217,267 and 5,038,117, which are incorporated herein by reference. Unfortunately, switching between divisors results in an undesirable phase error or phase jitter near the carrier frequency. Techniques for reducing such phase error are also known and are described in U.S. Patent 4,609,881 and in Steven R. Norsworthy et al. (Ed.) Delta-Sigma Data Converters Theory, Design, and Simulation, IEEE Press (1997), which
5 are incorporated herein by reference, as well as in the above-referenced U.S. Patents
3,217,267 and 5,038,117. As shown in Fig. 3 which is reproduced from Fig. 3.3 of Delta- Sigma Data Converters, a general technique for reducing such phase error is to cascade multiple stages of first or second order Delta-Sigma modulators 310, 320, 330 and supply an output of each stage to digital cancellation logic 340. The general form of each modular
10 stage is shown in Fig. 4 which is adapted from Fig. 3.1 of Delta-Sigma Data Converters. As shown in Fig. 4, the modulator comprises first and second summers 412, 413, first and second filters 415, 419 and a quantizer 417. Filter 419 connects an output signal, y(n), from quantizer 417 to a negative input of first summer 412 which combines an input signal x(n) with the filtered output and provides the result to an input to filter 415. An output of filter
15 415 is provided to an input to quantizer 417. Second summer 413 calculates the difference between the signals at the input and the output of quantizer 417 to generate a signal, e(n), representing the quantization error of the quantizer. Ideally, for the circuit of Fig. 3 the noise transfer function is (1 - Z"1)"1, where m is the overall order. Such a function has m coincident zeroes at z = 1 in the Z-transform plane.
20 A model of the Delta-Sigma modulator of Fig. 3 is shown in Fig. 5 which is reproduced from Fig. 5(d) of the '117 patent. Here, each of three identical stages 510, 520, 530 comprises first and second summers 512, 513, an integrator 515, a quantizer 517 and a Z"1 delay 519. A digital cancellation logic circuit 540 comprises a first differentiator 542 coupled to the output of the second stage 520, second and third differentiators 544, 546
25 coupled in cascade to the output of the third stage 530 and summer circuitry 550 coupled to the outputs of the first stage 510, the first differentiator 542 and the third differentiator 546. A series of error terms arising at different stages of the circuit of Fig. 5 are canceled when the terms are combined. In particular, following equation 16 of the '117 patent, the combined output of the circuit of Fig. 5 can be written
30
O = f + (1 - Z 1) Q, - (1 - Z 1) Q, + (1 - Z-1)2 Q2 - (1 - Z 1)2 Q2 + (1 - Z 1)3 Q3
where Qn is the quantization error associated with stage n. This equation reduces to
35 O = f + (1 - Z 1)3 Q3. As will be recognized by those skilled in the art, this equation has three coincident zeroes at z = 1 in the Z-transform plane.
An actual implementation of the Delta-Sigma modulator of Fig. 5 is shown in Fig. 6. Here, each of three identical stages 610, 620, 630 comprise an adder 614 and a Z'1 delay 619. A digital cancellation logic circuit 640 comprises a first differentiator 642, coupled to the carry output of adder 614 of the second stage 620, second and third differentiators 644, 646 coupled in cascade to the carry output of adder 614 of the third stage 630 and summer circuitry coupled to the carry output of the adder 614 of the first stage 610, the output of the first differentiator 642 and the output of the third differentiator 646.
SUMMARY OF THE INVENTION While prior art circuits of the type shown in Figs. 3, 5 and 6 have better performance than conventional fractional-N synthesizer circuits, there is still a need for even better performance. We have devised such a circuit. With reference to the Z-transform plane, such better performance is achieved by separating the zeroes in the Z-transform plane. As a result, the spectrum of the noise components of the fractional-N divisor is shifted away from the carrier frequency, thereby reducing the components near the carrier frequency and increasing the components farther away. This is advantageous because it is possible to remove the higher frequency components from the divisor signal by conventional filtering techniques. The model of a circuit for separating the zeroes is similar to that of Fig. 4 and comprises a first summer, first and second filters and a quantizer. The second filter connects an output of the quantizer to the first summer and an output of the summer is connected to an input of the first filter and an output of the first filter is connected to an input to the quantizer. In accordance with the invention, the second filter introduces off- axis zeroes into equations representative of this circuit. In a preferred embodiment, the second filter is realized by first and second delay elements connected in cascade, a multiplier and a second summer. An input to the first delay element is connected to the output of the quantizer and an output of the second delay element is connected to an input to the second summer. An input to the multiplier is connected to a node between the first and second delay elements and an output of the multiplier is connected to an input to the second summer. The second summer subtracts the signal from the second delay element from the signal from the multiplier and provides it as an input to the first summer.
The invention may also be implemented in software to generate fractional N divisors having desirable spectral characteristics. BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, features and advantages of the invention will be more readily apparent from the following detailed description of the invention in which: FIG. 1 is a block diagram of a prior art frequency synthesizer circuit; FIG. 2 is a block diagram of a prior art fractional-N divisor frequency synthesizer circuit;
FIG. 3 is a block diagram of a prior art multistage Delta-Sigma modulator; FIG. 4 is a block diagram of one stage of a prior art general Delta-Sigma modulator; FIG. 5 is a block diagram of a prior art multistage modulator for use in fractional-N synthesis;
FIG. 6 is a block diagram of a prior art implementation of the modulator of Fig. 5; FIG. 7 is a block diagram of an illustrative embodiment of a multistage modulator of the present invention; and
FIG. 8 is a block diagram of an illustrative model of one stage of a modulator of the present invention; and
DETAILED DESCRIPTION OF THE INVENTION
Fig. 7 is a block diagram of an illustrative embodiment of the invention. The circuit of Fig. 7 is a three stage modulator suitable for use in generating the divisor in a fractional N frequency synthesizer. Each stage comprises an adder 714 and one or more filter elements. In first and second stages 710, 720, the filter element is a Z"1 delay element 719. In the third stage 730, the filter element comprises first and second delay elements 721, 723, connected in cascade, a multiplier 725 and a summer 727. An input to the first delay element 721 is connected to the output of the adder and an output of the second delay element 723 is connected to an input to the summer 727. An input to the multiplier 725 is connected to a node between the first and second delay elements 721, 723 and an output of the multiplier is connected to an input to the summer 727. The summer subtracts the signal from the second delay element 723 from the signal from the multiplier 725 and provides it as an input to the adder 714.
The output of summer 750 can be shown to be
Output = f + (1 - Z ") Q, - (1 - Z 1) Q, + (1 - Z 1)2 Q2 - (1 - Z 1)2 Q2 +
(1 - KZ"1 + Z"2)(l - Z 1)2 Q3 = f + (1 - Z 1)2 (1 - KZ"1 + Z"2) Q3. Thus, the circuit of Fig. 7 achieves the same advantages of the circuit of Figs. 5 and 6 in cancelling intermediate terms and has the added advantage that the zeroes of the term (1 - KZ"1 + Z"2) are not on the abscissa for the case where K < 2.
A model of the third stage 730 is shown in Fig. 8. The model comprises summer
5 812, first and second filters 815, 819 and a quantizer 817. The second filter connects an output of the quantizer to the summer and an output of the summer is connected to an input of the first filter and an output of the first filter is connected to an input to the quantizer. In accordance with the invention, the second filter introduces off-axis zeroes into equations representative of this circuit.
10 Filter 819 introduces the polynomial term (1 - KZ"1 + Z"2) into the z-transform equation representative of the circuit of Fig. 7. The roots or zeroes of this term are
K ± κ:
15
For values of K < 2, this term introduces into the equation a pair of non-coincident zeroes on opposite sides of the abscissa.
As will be apparent from the foregoing disclosure to those skilled in the art,
^ numerous variations can be made in the practice of the invention. Other combinations of delay elements, adders and multipliers can be used to produce in the equations representative of the modulator other polynomial terms having off-axis zeroes. For example, more than three delay elements can be used, and/or more than one adder, and/or more than one multiplier. And, in general, those skilled in the art will be able to combine
^ adders, multipliers and delay elements to form a filter element 719 that is represented by a polynomial having any number of off-axis zeroes. The invention is also not limited to the number of stages of the modulator. While a modulator of three stages has been disclosed for purposes of illustration, the invention may be practiced using any number of stages desired. Further, the invention is not limited to use in the Delta-Sigma modulators
•^ described. It may also be practiced in other circuits where it is desirable to generate off-axis zeroes.

Claims

What is claimed is:
1. In a fractional N frequency synthesizer, a circuit comprising: first, second and third filter circuits connected in cascade, a digital cancellation logic circuit comprising a first differentiator having an input connected to an output of the second filter circuit, second and third differentiators connected in cascade with the second differentiator having an input connected to an output of the third filter circuit and summer circuitry having inputs connected to the output of the first filter circuit, an output of the first differentiator and an output of the third differentiator; each of said first and second filter circuits functioning as a Sigma-Delta modulator; said third filter circuit comprising an adder, a summer and a delay circuit, an input of the delay circuit being connected to an output of the adder, said delay circuit having a plurality of outputs that are combined by said summer to form a summer output signal that is provided as an input to the adder, said delay circuit introducing at least one off-axis zero into an equation representative of said circuit.
2. In a fractional N frequency synthesizer, a circuit model comprising: a first summer; first and second filters, and a quantizer, an output of the first summer being connected to an input to the first filter and an output of the first filter being connected to an input to the quantizer, an output of the quantizer being connected to the second filter and an output of the second filter being connected to an input to the summer; where the second filter introduces at least one off-axis zero into an equation representative of said circuit.
3. The circuit model of claim 2 wherein the second filter comprises first and second circuit elements having inputs coupled to the output of the quantizer and outputs coupled to an input to a second summer and an output of said second summer is connected to an input to said first summer.
4. In a fractional N frequency synthesizer, a circuit model comprising: at least first and second modulator stages connected in cascade, each comprising: a first summer; first and second filters, and a quantizer, an output of the first summer being connected to an input to the first filter and an output of the first filter being connected to an input to the quantizer, an output of the quantizer being connected to the second filter and an output of the second filter being connected to an input to the summer; where the second filter in at least one stage introduces at least one off-axis zero into an equation representative of said circuit.
5. The circuit model of claim 4 wherein the second filter in at least one stage comprises first and second circuit elements having inputs coupled to the output of the quantizer in that stage and outputs coupled to an input to a second summer and an output of said second summer is connected to an input to said first summer in that stage.
6. In a fractional N frequency synthesizer, a circuit model comprising: a least first, second, and third modulator stages connected in cascade, each comprising a first summer, first and second filters and a quantizer, an input of the second filter being connected to an output of the quantizer and an output of the second filter being connected to a negative input of the first summer, an output of the first summer being connected to an input to the first filter and an output of the first filter being connected to an input to the quantizer; a digital cancellation logic circuit comprising a first differentiator having an input connected to the output of the second modulator stage, second and third differentiators connected in cascade with the second differentiator having an input connected to the output of the third modulator stage and summer circuitry having inputs connected to the output of the first modulator stage, an output of the first differentiator and an output of the third differentiator; and a circuit in at least one modulator stage for introducing at least one off-axis zero into an equation representative of said circuit.
7. The circuit model of claim 6 further comprising in said first and second stages a second summer connected to said quantizer so as to generate a quantization error signal that is supplied as an input to the first summer of the next stage.
8. The circuit model of claim 6 wherein the first filter is an integrator.
9. The circuit model of claim 6 wherein the second filter includes at least one delay element.
10. In a fractional N frequency synthesizer, a circuit comprising:
5 a first circuit comprising a first adder and a delay circuit, an input of the delay circuit being connected to an output of the adder and an output of the delay circuit being connected to an input of the adder; a second circuit comprising a first adder and a delay circuit, an input of the delay circuit being connected to an output of the adder and an output of the delay circuit being 10 connected to an input of the adder, an output of the delay circuit of the first circuit being connected to a second input of the adder; a third circuit comprising a first adder and a delay circuit, an input of the delay circuit being connected to an output of the adder and an output of the delay circuit being connected to an input of the adder, an output of the delay circuit of the second circuit being 15 connected to a second input of the adder; a digital cancellation logic circuit comprising a first differentiator having an input connected to a carry output of the adder of the second circuit, second and third differentiators connected in cascade with the second differentiator having an input connected to a carry output of the adder of the third circuit and summer circuitry having 20 inputs connected to a carry output of the adder of the first circuit, an output of the first differentiator and an output of the third differentiator; and a circuit in at least one of said first, second and third circuits for introducing at least one off-axis zero into an equation representative of said circuit.
25 11. The circuit of claim 10 wherein the circuit for introducing at least one off-axis zero comprises first and second delay elements connected in cascade, an input of the first delay element being connected to an output of the adder and at least one multiplier or additional delay element connected to a node between the first and second delay elements, outputs of said second delay element and said multiplier or additional delay element being connected
30 to a summer the output of which is connected to a second input to the first adder of that stage.
35
PCT/US2002/030279 2001-09-26 2002-09-24 Fractional-n type frequency synthesizer WO2003028218A1 (en)

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JP2003531614A JP2005505162A (en) 2001-09-26 2002-09-24 Fractional N frequency synthesizer
KR10-2004-7004518A KR20040073432A (en) 2001-09-26 2002-09-24 Fractional-n type frequency synthesizer
EP02775964A EP1446885A4 (en) 2001-09-26 2002-09-24 Fractional-n type frequency synthesizer

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US09/966,205 2001-09-26
US09/966,205 US6570452B2 (en) 2001-09-26 2001-09-26 Fractional-N type frequency synthesizer

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EP1657821A1 (en) * 2003-11-28 2006-05-17 Fujitsu Limited Sd modulator of pll circuit
US7602252B2 (en) 2006-10-10 2009-10-13 Advantest Corporation Sigma delta modulator, fractional frequency synthesizer and sigma delta modulating method

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* Cited by examiner, † Cited by third party
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US6920182B2 (en) * 2001-01-09 2005-07-19 Microtune (Texas), L.P. Delta-sigma modulator system and method
US7391840B2 (en) * 2002-07-03 2008-06-24 Telefonaktiebolaget Lm Ericsson (Publ) Phase locked loop circuit, electronic device including a phase locked loop circuit and method for generating a periodic signal
EP1649601A1 (en) * 2003-07-25 2006-04-26 Fujitsu Limited Variable frequency synthesizer comprising a sigma-delta modulator
US7038507B2 (en) * 2003-11-14 2006-05-02 Teledyne Technologies Incorporated Frequency synthesizer having PLL with an analog phase detector
US7932787B1 (en) 2005-06-30 2011-04-26 Cypress Semiconductor Corporation Phase lock loop control system and method
US8072277B1 (en) 2005-06-30 2011-12-06 Cypress Semiconductor Corporation Spread spectrum frequency synthesizer
US7961059B1 (en) 2005-06-30 2011-06-14 Cypress Semiconductor Corporation Phase lock loop control system and method with non-consecutive feedback divide values
US8174326B1 (en) 2005-06-30 2012-05-08 Cypress Semiconductor Corporation Phase lock loop control error selection system and method
US7948327B1 (en) 2005-06-30 2011-05-24 Cypress Semiconductor Corporation Simplified phase lock loop control model system and method
US7813411B1 (en) 2005-06-30 2010-10-12 Cypress Semiconductor Corporation Spread spectrum frequency synthesizer with high order accumulation for frequency profile generation
US7405629B2 (en) * 2005-06-30 2008-07-29 Cypress Semiconductor Corp. Frequency modulator, circuit, and method that uses multiple vector accumulation to achieve fractional-N frequency synthesis
US7701297B1 (en) 2005-06-30 2010-04-20 Cypress Semiconductor Corporation Spread spectrum frequency synthesizer with improved frequency shape by adjusting the length of a standard curve used for spread spectrum modulation
US7912109B1 (en) 2005-06-30 2011-03-22 Cypress Semiconductor Corporation Spread spectrum frequency synthesizer with first order accumulation for frequency profile generation
US7741918B1 (en) 2005-06-30 2010-06-22 Cypress Semiconductor Corporation System and method for an enhanced noise shaping for spread spectrum modulation
KR100698862B1 (en) * 2005-08-19 2007-03-26 후지쯔 가부시끼가이샤 Variable frequency synthesizer comprising a sigma-delta modulator
US7482885B2 (en) * 2005-12-29 2009-01-27 Orca Systems, Inc. Method of frequency synthesis for fast switching
US7519349B2 (en) * 2006-02-17 2009-04-14 Orca Systems, Inc. Transceiver development in VHF/UHF/GSM/GPS/bluetooth/cordless telephones
US7839965B2 (en) 2006-11-21 2010-11-23 Agere Systems Inc. High-speed serial data link with single precision clock source
US7656236B2 (en) * 2007-05-15 2010-02-02 Teledyne Wireless, Llc Noise canceling technique for frequency synthesizer
US8179045B2 (en) 2008-04-22 2012-05-15 Teledyne Wireless, Llc Slow wave structure having offset projections comprised of a metal-dielectric composite stack
US9202660B2 (en) 2013-03-13 2015-12-01 Teledyne Wireless, Llc Asymmetrical slow wave structures to eliminate backward wave oscillations in wideband traveling wave tubes

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800342A (en) * 1985-02-21 1989-01-24 Plessey Overseas Limited Frequency synthesizer of the fractional type
US5311181A (en) * 1990-01-31 1994-05-10 Analog Devices, Inc. Sigma delta modulator
US5648779A (en) * 1994-12-09 1997-07-15 Advanced Micro Devices, Inc. Sigma-delta modulator having reduced delay from input to output
US5949361A (en) * 1997-05-12 1999-09-07 The United States Of America Represented By The Secretary Of The Navy Multi-stage delta sigma modulator with one or more high order sections
US5982315A (en) * 1997-09-12 1999-11-09 Qualcomm Incorporated Multi-loop Σ Δ analog to digital converter
US6121910A (en) * 1998-07-17 2000-09-19 The Trustees Of Columbia University In The City Of New York Frequency translating sigma-delta modulator
US6236703B1 (en) * 1998-03-31 2001-05-22 Philsar Semiconductor Inc. Fractional-N divider using a delta-sigma modulator
US6351229B1 (en) * 2000-09-05 2002-02-26 Texas Instruments Incorporated Density-modulated dynamic dithering circuits and method for delta-sigma converter
US6392493B1 (en) * 1999-08-10 2002-05-21 Koninklijke Philips Electronics N.V. Fractional-N frequency synthesizer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3217267A (en) 1963-10-02 1965-11-09 Ling Temco Vought Inc Frequency synthesis using fractional division by digital techniques within a phase-locked loop
GB2140232B (en) 1983-05-17 1986-10-29 Marconi Instruments Ltd Frequency synthesisers
US5038117A (en) 1990-01-23 1991-08-06 Hewlett-Packard Company Multiple-modulator fractional-N divider
US6509800B2 (en) * 2001-04-03 2003-01-21 Agilent Technologies, Inc. Polyphase noise-shaping fractional-N frequency synthesizer

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800342A (en) * 1985-02-21 1989-01-24 Plessey Overseas Limited Frequency synthesizer of the fractional type
US5311181A (en) * 1990-01-31 1994-05-10 Analog Devices, Inc. Sigma delta modulator
US5648779A (en) * 1994-12-09 1997-07-15 Advanced Micro Devices, Inc. Sigma-delta modulator having reduced delay from input to output
US5949361A (en) * 1997-05-12 1999-09-07 The United States Of America Represented By The Secretary Of The Navy Multi-stage delta sigma modulator with one or more high order sections
US5982315A (en) * 1997-09-12 1999-11-09 Qualcomm Incorporated Multi-loop Σ Δ analog to digital converter
US6236703B1 (en) * 1998-03-31 2001-05-22 Philsar Semiconductor Inc. Fractional-N divider using a delta-sigma modulator
US6121910A (en) * 1998-07-17 2000-09-19 The Trustees Of Columbia University In The City Of New York Frequency translating sigma-delta modulator
US6392493B1 (en) * 1999-08-10 2002-05-21 Koninklijke Philips Electronics N.V. Fractional-N frequency synthesizer
US6351229B1 (en) * 2000-09-05 2002-02-26 Texas Instruments Incorporated Density-modulated dynamic dithering circuits and method for delta-sigma converter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1446885A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1657821A1 (en) * 2003-11-28 2006-05-17 Fujitsu Limited Sd modulator of pll circuit
EP1657821A4 (en) * 2003-11-28 2006-08-23 Fujitsu Ltd Sd modulator of pll circuit
US7279990B2 (en) 2003-11-28 2007-10-09 Fujitsu Limited Sigma-delta modulator for PLL circuits
US7602252B2 (en) 2006-10-10 2009-10-13 Advantest Corporation Sigma delta modulator, fractional frequency synthesizer and sigma delta modulating method

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KR20040073432A (en) 2004-08-19
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US6570452B2 (en) 2003-05-27
EP1446885A1 (en) 2004-08-18
EP1446885A4 (en) 2009-05-13

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