WO2003025643A1

WO2003025643A1 - Integrated optical device and method of production

Info

Publication number: WO2003025643A1
Application number: PCT/GB2002/003678
Authority: WO
Inventors: John Paul Drake; Sureshchandra Mishrilal Ojha; Stephen William Roberts
Original assignee: Bookham Technology Plc
Priority date: 2001-08-15
Filing date: 2002-08-09
Publication date: 2003-03-27
Also published as: GB0119917D0

Abstract

A method of manufacturing an integrated optic device including an array waveguide grating comprising an array of silicon rib waveguides coupled at one end to a silicon free propagation region, and at least one input/output silicon rib waveguide coupled to the free propagation region for optical communication with the array waveguide grating across the free propagation region, wherein the array waveguide grating and the at least one input/output waveguide are formed by subjecting a layer of epitaxial silicon to two etching steps so as to form thereby the array of silicon rib waveguides having a first etch depth along their entire length, and the at least one input/output silicon rib waveguide having a second etch depth greater than the first etch depth.

Description

INTEGRATED OPTICAL DEVICE AND METHOD OF PRODUCTION

The present invention relates to a method of making an integrated optical device and to an integrated optical device perse.

Integrated optical devices comprising optical components in discrete areas of a substrate are known. An example is an array waveguide grating (AWG) as commonly used for wavelength division multiplexing (WDM) and demultiplexing (DWDM) in the field of optical telecommunications. A common application of an AWG is to split light of multiple wavelengths from a single incoming optical fibre and send each wavelength to a different output fibre. In this way signals may be transmitted on different optical wavelengths (channels) in the same fibre and then separated at the destination. In a multiplexer, a number of incoming optical fibres can supply individual optical channels, which are then multiplexed in the AWG onto a single output waveguide.

In practice, an AWG is integrated on a silicon-on-insulator wafer with a series of input waveguides and a series of output waveguides separated by an array of curved waveguides. The input waveguides are separated from the curved waveguides by a slab region, as are the curved waveguides separated from the output waveguides. Such an AWG is described further in US 5,002,350.

The waveguides are formed as ridge waveguides by etching into epitaxial silicon in the silicon-on-insulator wafer. Each waveguide is thus defined by its width and its depth. In fact the optical properties of the waveguides are strongly dependent on their cross-sectional dimensions. According to present manufacturing techniques, ridge waveguides are formed in a uniform wafer from which the waveguides are etched through a photolithographic mask. The height of the waveguide ridge is normally constant across the wafer, as is the depth of the etch because all the waveguides are etched at once. The waveguides therefore vary only in their cross-sectional width. This means that it is difficult to accommodate the differing optical requirements of the input and output waveguides and the array of curved waveguides while still optimising chip size.

It is an aim of the invention to overcome this problem.

The inventors have determined that significant differences in optical properties also arise as a result of different etch depths, as discussed in more detail in the following.

Deeper etched waveguides can support relatively smaller bend radii without exhibiting transmission loss. Thus, deeper etching can in principle produce smaller chips.

The more deeply etched a waveguide, the more tightly confined are the optical transmission modes. As pass band profiles are limited by the overlap integral of the input and output waveguide modes, these profiles roll off faster if the waveguide modes are more tightly confined in the input and output waveguides. It is desirable to have filter pass band profiles that roll off as fast as possible to reduce signal leakage and crosstalk into adjacent channels. Thus, deeper etching allows the design of wider filter pass bands with lower adjacent channel crosstalk.

The loss of an AWG is generally limited by the loss in the coupling region which exists between the input and output waveguides respectively and the array of curved waveguides, the so-called star coupler. This loss arises from the non-adiabatic transition at the ends of the array waveguides where the light ceases to be confined laterally by etched trenches. The loss of the coupler can be minimised by careful optimisation of the geometry. In general terms a lower loss can be achieved if the etch is shallower as this makes the transition smoother.

The crosstalk floor of an AWG is limited by imperfections in the fabrication of the array waveguides. These imperfections can be variations in material composition or simply dimensional variations, either of which causes the effective index of the waveguide to be non- uniform in a more or less random fashion. The inventors have determined through numerical simulations that waveguides that exhibit higher optical confinement (deeper etched waveguides) will in general cause a bigger variation in effective index than those with lower confinement, i.e. shallower etched waveguides, for comparable width variations. This has been found to be the case even when the length of the deeper etch array waveguide is taken into account. Hence for low crosstalk, relatively shallow etching is preferred.

Thus it is clear that there are conflicting requirements on the etched depth of the overall AWG device. If in the known single etch process the etch is designed to be either deeper or shallower, improvements result in some parameters but this is always accompanied by a degradation in others.

According to one aspect of the present invention there is provided a method of manufacturing an integrated optical device on a substrate, the device comprising a first region containing a first plurality of optical waveguides and a second region containing at least one second waveguide, the method comprising: defining the first plurality of optical waveguides within a first exposure field; performing an etch step to etch the first plurality of optical waveguides to a first depth; defining the at least one second waveguide within a second exposure field; and performing a separate etch step to etch the second waveguide to a second depth greater than the first depth.

According to another aspect of the invention there is provided an integrated optical device comprising a first region containing a first plurality of optical waveguides and a second region containing at least one second waveguide, each of the waveguides having been formed by etching, wherein the etched depth of the optical waveguides of the first plurality is less than the etched depth of the at least one second waveguide.

For a better understanding of the present invention and to show how the same may be carried into effect reference will now be made by way of example to the accompanying drawings in which:

Figure 1 illustrates the use of a stepper field arrangement for a two step etch process;

Figure 2 is a section through the array waveguides in the central part;

Figure 3 is a section through the input and output waveguides; and

Figure 4 illustrates a method according to another embodiment of the present invention.

Figure 1 illustrates an array waveguide (AWG) manufactured on a silicon-on-insulator chip. The waveguide array 3 consists of a plurality of curved waveguides. The array 11 acts as a dispersive array of ridge waveguides formed on the chip. Each of the waveguides has a straight input section and a straight output section, with a curved section between the input section and the output section. The straight input sections incline inwards towards each other so as to point to a focus position at the end of a set of input waveguides 2.

Similarly the straight output sections are inclined towards each other so as to form a focus in a region adjacent the entrance to an array 4 of output waveguides. Due to dispersion within the array 11 being dependent on wavelength, the demultiplexed output channels are focused on an arc of a circle at a focal line adjacent the input to the output waveguides 4. The array of output waveguides 4 detects channel images formed at the focal line. It will be appreciated that the array waveguide structure shown in Figure 1 can be used as a demultiplexer, with the input waveguides 2 supplying a plurality of multiplexed optical channels, which are separated by the AWG central section 3 and supplied along the output waveguides of the output waveguide array 4. Alternatively, the structure can be used as a multiplexer to multiplex a plurality of input optical signals onto a single output waveguide.

In addition to showing the array waveguide, Figure 1 illustrates the stepper fields that are used for its manufacture. A first field containing input waveguides 2 is shown, which overlaps with a second field containing the array of curved waveguides 3, which in turn overlaps with a third field containing the output waveguides 4. The second field includes the entire curved array 3 so the curved waveguide array 3 can be formed in a single exposure without the need to stitch two fields across the array. Similarly, the input 2 and output 4 waveguides are each defined within a single field and are thus free from any possible stitching error. The regions 5 where the fields overlap lie across the coupler or slab regions between the waveguides. These coupler areas are relatively large and featureless so any slight misalignment of the fields where they are stitched together in these areas is of little or no consequence.

Figure 2 is a section through the curved waveguides 3 in the intermediate part of the array waveguide. Figure 2 illustrates a silicon- on-insulator wafer 8 comprising a silicon substrate 10, a layer of silicon dioxide 12 and an upper layer 14 of epitaxial silicon. Prior to formation of the ridge waveguides, the upper surface of the epitaxial silicon layer is planar. The ridge waveguides 30 are formed by etching vertically into the epitaxial silicon layer 14. In the intermediate section 3 of curved waveguides, the etch depth is d1 , which is termed herein "shallow", for example in the range 1.2 μm to 2.00 μm for a width of 1.7 μm.

Figure 3 is a section through a ridge waveguide of the input 2 or output 4 array. Like numerals denote like parts as in Figure 2. The difference between the ridge waveguide structure of Figure 2 and that of Figure 3 is that the etch depth for the ridge waveguide in Figure 3, d2, is greater than d1. This is termed herein "deep", and is for example in the range 2.00 to 2.80 μm. In the structure of Figure 2 and Figure 3, a layer of oxide 16 covers the ridge waveguides.

In the above example the epi thickness t is 4μm.

Generally, for a depth x of the epitaxial silicon layer 14 the following parameters apply - d1 lies in the range 0.3x to 0.5x and d2 lies in the range 0.5x to 0.7x. A typical epi depth for AWG products in silicon is 4.3 μm.

The width w of the ridge waveguide in Figure 2 is the same as that in Figure 3, although this is not of course essential. That is, the width could vary as well as the depth. However it is important that the depths vary for the following reasons. The shallow etch which is used for the array waveguides 3 provides sufficiently low loss and crosstalk while still maintaining an acceptable bend radius. The deep etch used for the input 2 and output 4 waveguides allows high optical confinement (and hence low adjacent channel crosstalk) and a small bend radius in these waveguides.

The differing etch steps can be achieved using the following method. Using a photolithographic stepping machine, for example the PAS Double 500/100D produced by ASM Lithography, the central field, that is the field for the array waveguides 3, is located. Note that use of this stepper is discussed in more detail in WO00/73854 (PCT/GB0O/O1984). De-magnified images of the appropriate mask pattern for the array waveguides 3 are projected onto the wafer surface by a microlithographic lens mounted just above the wafer surface. An illumination system exposes light through a chrome-on-glass reticle that has the mask pattern etched into the chrome. After the ridge waveguide has been thus photolithographically defined, it is subject to a first etch for a time which produces the shallow depth d1. Next, the fields for the input and output waveguides 2, 4 are located and the array waveguides 3 masked to protect them from the subsequent procedure. The input and output waveguides are photolithographically defined as just described and a second etch is carried out for a time long enough to produce the deep etch d2 illustrated in Figure 3.

The etching steps are dry etches using gases that become reactive to silicon in a RF field. This is carried out in vacuum chamber for an appropriate time, for example in the range 2 to 15 minutes depending on conditions. Figure 4 illustrates an alternative method for producing the same structures. The left-hand side of Figure 4 shows a cross-section through a portion of the optic chip in which one of the input or output waveguides (2, 4) is formed, and the right-hand side of Figures illustrates a cross-section through a portion of the optic chip in which one of the waveguides of the array waveguides (3) is formed.

In this alternative method, a thin silicon oxide layer 20 is formed over the entire surface of the epitaxial silicon layer (14) of the SOI chip (Step (B)). The thin oxide layer is resistant to the etching processes used later in this method and serves to protect the underlying silicon. Other materials can be used for this etch resistant layer, such as silicon nitride. A standard technique is then used to pattern the thin oxide layer according to the desired configuration for both the input and output waveguides (2, 4) and the AWG (3) (Step (C)). Once the patterning of the oxide layer is complete for both the input and output waveguides and the AWG, the exposed portions of the silicon layer corresponding to the input and output waveguides (2, 4) are protected by forming an etch-resistant resist layer (22) over them (Step (D). Next, the exposed portions of the silicon layer corresponding to the AWG (3) are subjected to shallow etching to form the AWG comprising an array of waveguides (30) of relatively shallow etch depth (Step (E)). Next, the resist layer (22) is removed to expose the portions of the silicon layer corresponding to the input and output waveguides (2, 4), and the etched portions of the silicon layer corresponding to the AWG (3) are protected by forming an etch-resistant resist layer (24) over them (Step (F)). Next, the exposed portions of the silicon layer corresponding to the input and output waveguides are subjected to relatively deep etching to form the input and output waveguides (30) of relatively deep etch depth compared to the AWG (Step (G). In an optional step, the resist layer (24) is removed (Step (H)). With regard to the dimensions of the input and output waveguides (2,4) and the AWG (3), reference is made to the earlier detailed description.

The two step etch technique of the present invention allows a far greater degree of optimisation of each waveguide for its purpose in the device, hence simultaneously improving size, loss, adjacent and non- adjacent crosstalk parameters.

The applicant draws attention to the fact that the present invention may include any feature or combination of features disclosed herein either implicitly or explicitly or any generalisation thereof, without limitation to the scope of any definitions set out above. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

CLAIMS:

1. A method of manufacturing an integrated optical device on a substrate, the device comprising a first region containing a first plurality of optical waveguides and a second region containing at least one second waveguide, the method comprising: defining the first plurality of optical waveguides within a first exposure field; performing an etch step to etch the first plurality of optical waveguides to a first depth; defining the at least one second waveguide within a second exposure field; and performing a separate etch step to etch the second waveguide to a second depth greater than the first depth.

2. A method according to claim 1 , wherein the steps of defining the first plurality of optical waveguides and performing an etch step to etch them is carried out before the steps of defining the least one second waveguide and the separate etch step to etch it.

3. A method according to claim 1 or 2, wherein the defining steps are carried out using a photolithographic process.

4. A method according to any preceding claim, wherein the first and second exposure fields are contiguous, the arrangement being such that a line of contact or area of overlap between the first and second fields lies within a third relatively featureless area of the substrate which separates the first and second regions.

5. A method according to any preceding claim when carried out using a photolithographic stepper.

6. A method according to any preceding claim, wherein the first plurality of optical waveguides are masked after they have been etched BY the first step and prior to the steps of defining and etching the at least one second waveguide.

7. A method according to any preceding claim, wherein the first depth lies in the range 1.2 to 2.00 μm.

8. A method according to any preceding claim, wherein the second depth lies in the range 2.00 to 2.8 μm.

9. An integrated optical device comprising a first region containing a first plurality of optical waveguides and a second region containing at least one second waveguide, each of the waveguides having been formed by etching, wherein the etched depth of the optical waveguides of the first plurality is less than the etched depth of the at least one second waveguide.

10. An integrated optical device according to claim 9, which comprises a third region containing a third plurality of optical waveguides having an etch depth which is the same as the at least one second waveguide.

11. An integrated optical device according to claim 9 or 10, wherein the first plurality of optical waveguides are curved and constitute an array of waveguides, of which the at least one second waveguide forms an input or output.

12. An integrated optical device according to claim 9, 10 or 11 , wherein the depth of the first plurality of optical waveguides lies in the range 1.2 to 2 μm.

13. An integrated optical device according to any of claims 9 to 12, wherein the second depth lies in the range 2.00 to 2.8 μm.

14. A method of manufacturing an integrated optic device including an array of waveguides coupled at one end to a free propagation region, and at least one input/output waveguide coupled to the free propagation region for optical communication with the array of waveguides across the free propagation region, wherein the array of waveguides and the at least one input/output waveguide are formed by subjecting a layer of optic material to two etching steps, the etch depths of the two etching steps selected so as to form thereby the array of waveguides having a first, uniform etch depth along their entire length, and the at least one input/output waveguide having a second etch depth greater than the first etch depth.

15. A method of manufacturing an integrated optic device according to claim 14, the two etching steps including: a first etch step to etch a selected portion of the layer of optic material to a first depth to form the array of waveguides; and a second etch step to etch a selected portion of the layer of optic material to a second depth greater than the first depth to form the at least one input/output waveguide.

16. A method of manufacturing an integrated optic device according to claim 15, including the steps of: forming an etch resistant layer over the layer of optic material; patterning the etch resistant layer to expose selected portions of the layer of optic material according to the desired configuration for the array of waveguides and the at least one input/output waveguide; and then carrying out the first and second etching steps, each etching step being preceded by a selective masking step to protect those exposed portions of the layer of optic material that are not to be etched in the respective etching step.

17. A method of manufacturing an integrated optic device including an array waveguide grating comprising an array of silicon rib waveguides coupled at one end to a silicon free propagation region, and at least one input/output silicon rib waveguide coupled to the free propagation region for optical communication with the array waveguide grating across the free propagation region, wherein the array waveguide grating and the at least one input/output waveguide are formed by subjecting a layer of epitaxial silicon to two etching steps so as to form thereby the array of silicon rib waveguides having a first etch depth along their entire length, and the at least one input/output silicon rib waveguide having a second etch depth greater than the first etch depth.

18. An integrated optic device including an optic chip in which there is defined an array waveguide grating comprising an array of silicon rib waveguides coupled at one end to a silicon free propagation region, and at least one input/output silicon rib waveguide coupled to the free propagation region for optical communication with the array waveguide grating across the free propagation region, each of the silicon rib waveguides having been formed by etching, wherein the etch depth of the silicon rib waveguides composing the array waveguide grating is uniform along their entire length and is less than the etch depth of the at least one input/output rib waveguide.