WO2003021496A3 - Gate estimation process and method - Google Patents

Gate estimation process and method Download PDF

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Publication number
WO2003021496A3
WO2003021496A3 PCT/US2002/027009 US0227009W WO03021496A3 WO 2003021496 A3 WO2003021496 A3 WO 2003021496A3 US 0227009 W US0227009 W US 0227009W WO 03021496 A3 WO03021496 A3 WO 03021496A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
design parameter
parameter file
component
estimation process
Prior art date
Application number
PCT/US2002/027009
Other languages
French (fr)
Other versions
WO2003021496A2 (en
Inventor
William Wheeler
Matthew Adiletta
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of WO2003021496A2 publication Critical patent/WO2003021496A2/en
Publication of WO2003021496A3 publication Critical patent/WO2003021496A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Abstract

A method comprising maintaining a circuit design parameter file for a circuit being designed by a circuit designer. The circuit design parameter file specifies a physical characteristic of the circuit. The method monitors a design environment to detect the addition of a circuitry component to the circuit and access a component design parameter file that specifies at least one design parameter for that added circuitry component. The method updates the circuit design parameter file based on the at least one design parameter included in the component design parameter file.
PCT/US2002/027009 2001-08-29 2002-08-23 Gate estimation process and method WO2003021496A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/941,519 US7073156B2 (en) 2001-08-29 2001-08-29 Gate estimation process and method
US09/941,519 2001-08-29

Publications (2)

Publication Number Publication Date
WO2003021496A2 WO2003021496A2 (en) 2003-03-13
WO2003021496A3 true WO2003021496A3 (en) 2004-02-19

Family

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Family Applications (1)

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PCT/US2002/027009 WO2003021496A2 (en) 2001-08-29 2002-08-23 Gate estimation process and method

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US (1) US7073156B2 (en)
TW (1) TW583562B (en)
WO (1) WO2003021496A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104484541B (en) * 2015-01-13 2017-05-24 成都锐开云科技有限公司 Stray capacitance extraction method based on Markov transfer matrix bank

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Also Published As

Publication number Publication date
TW583562B (en) 2004-04-11
WO2003021496A2 (en) 2003-03-13
US7073156B2 (en) 2006-07-04
US20030046652A1 (en) 2003-03-06

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