WO2003019879A1 - Three-stage non-blocking fault tolerant cross-connect architecture - Google Patents

Three-stage non-blocking fault tolerant cross-connect architecture Download PDF

Info

Publication number
WO2003019879A1
WO2003019879A1 PCT/IT2001/000454 IT0100454W WO03019879A1 WO 2003019879 A1 WO2003019879 A1 WO 2003019879A1 IT 0100454 W IT0100454 W IT 0100454W WO 03019879 A1 WO03019879 A1 WO 03019879A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
protection
input
cross
output
matrices
Prior art date
Application number
PCT/IT2001/000454
Other languages
French (fr)
Inventor
Mario Signorazzi
Original Assignee
Telefonaktiebolaget Lm Ericsson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/0001Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005Switch and router aspects
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/35Application specific switches
    • H04L49/356Storage area network switches
    • H04L49/357Fibre channel switches
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/101Crossbar or matrix
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/15Interconnection of switching modules
    • H04L49/1515Non-blocking multistage, e.g. Clos
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/55Error prevention, detection or correction
    • H04L49/557Error correction, e.g. fault recovery or fault tolerance
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/0001Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005Switch and router aspects
    • H04Q2011/0037Operation
    • H04Q2011/0043Fault tolerance

Abstract

The invention concerns an electro and/or optical cross-connect core (E/OXC) in telecommunications, of the kind employing cross bars switch elements and/or selectors as building blocks and a three stage, SSNB, WSNB or RNB interconnecting architecture with suitable input and output cross connections, in order to provide a fault protection with protection ratio 1:N. According to the invention the elementary input and output matrices of the cross-connect core involve protection resources consisting of additional input/output channels; in that said additional protection channels are interconnected with the ordinary input/output channels of each elementary matrix; and in that the size of each of the matrices in the central stage is equal or smaller than the one required to provide a 1:N protection generated by each input/output matrix connected thereto. The cooperation among the elementary matrices to solve the fault of one of them can be controlled only by firmware and the size of the central stage can be determined only depending on he number of ordinary ports and of the chosen protection redundancy (1:N), both for input/output ports and for protection ports, so as to allow the undisturbed restoring of the connections interrupted by the fault and the matrix substitution, still without disturbs.

Description

THREE-STAGE NON-BLOCKING FAULT TOLERANT CROSS-CONNECT ARCHITECTURE

This invention refers to an electro and/or optical cross connect core (E/OXC), which uses a three-stage architecture and which is able to ensure a fault protection with a protection ratio 1 :N.

It is well-known that the next generation of Optical Transport Networks (OTN) have to provide global transport for circuit and packet switching services and particularly for IP services. OTN's will have to provide paths for light delivery and automatic routing and restoration thereof. To achieve that in an effective way, the Optical Transport Network needs to be flexible, reliable, reconfigurable, scalable and cost effective.

To provide flexibility and reconfigurability, optical cross connects (OXC's) have been developed an introduced in the OTN through which high capacity data streams are routed through the optical path layer. It is desirable that the OXC operations are independent of client signal (i.e. of signal bit rate and signal characteristics) and protocol.

Optical Cross-Connects have to be scalable and expandable, i.e. starting from a basic OXC size with a certain number of ports, it should be possible to easily reduce or expand the OXC size by reducing or increasing the number of boards.

Cost effectiveness requires a modular OXC implementation, i.e. all the boards constituting the OXC core have to be the same or of a few similar kinds.

Reliability implies that OTN provide some form of automatic protection and restoration of interrupted lightpaths in case of fault, with a minimal impact over the other concurring services. That has to be provided by the OXC architecture possibly even through other Network Elements (network topology, Routing Protocols etc.) which may concur in achieving reliability goals. The same reason implies that Fully Non-Blocking or Wide Sense Non-Blocking operation is required in all the possible OXC status.

A usual requirement for this aspect is that the OXC must provide full protection and restoration of the services under every single fault condition. In this context, single fault can be regarded as the minimum hardware or software element that can reliably monitored and substituted in its function (e.g. a PBA or a Module). Module replacement should be hitless too.

Most of the OXC implementations uses electronic or optical Cross-Bar elementary switch matrices as OXC internal building blocks and, in this context, fig. 1 in the annexed drawings shows a possible optical cross-connect architecture to which this invention can be applied. A comb 1 of channels having high capacity wavelength is transported on each input fibre 2. All of these optical signals are demultiplexed in 3 before entering the E/OXC 4. The cross-connect 4 is one of the basic elements in the architecture, since most characteristics of OXC's depend on its features.

When the implementations of optical cross-connect core use, as internal E/OXC building blocks, electronic or optical elementary switch matrices which are commercially available, such matrices are usually "square" (input and output array have the same length), presently with a size like 68x68 or smaller due to technological reasons. However, the invention applies also to rectangular matrices.

Conventional OXC design achieves strictly non blocking characteristic by using in its core (that is the central stage switch array) the well known three stage architecture fully connected. It is built by interconnecting a large number of smaller size switch elements, usually commercially available.

This design allows non-blocking feature because it is capable to route each of the N OXC core inputs in a NxN OXC, using the number of matrix elements effectively, at the cost of a reduction of the scalability characteristic.

This is due to the intricate nets linking each of central elementary modules to each of input/output stage module. Some solution have been proposed to relieve the scalability problem, but this circumstance has also prevented to find an acceptable I to N protection approach: it is in fact very difficult to imagine how a spare resource can be shared by different working OXC elements and used, in case of fault, unless incongruous (and fault prone) selection tree switch arrays are added. For this reason, no implementation of I to N protection is nowadays available, at the best of applicant's knowledge, and protection strategies offered for large Cross-Connects contemplate only 1 + 1 or 1 : 1 protection, as shown in Fig. 2. The problem is now solved by the present invention, which provides a cross- connect core of new concept, utilising cross-bar switch elements as building blocks and a three-stage interconnection architecture with appropriate input/output linking, in order to provide a 1 :N protection against single fault, with economic and reliability advantages.

More precisely, the invention refers to an electro and/or optical cross-connect core (E/OXC) in the telecommunications, of the kind employing as building blocks cross-bar switch elements and/or selectors and a three-stage interconnection architecture, with appropriate input and output cross-linkings, in order to ensure a 1 :N protection against single faults, characterised in that input and output element matrices in the cross-connect core show protection resources consisting of additional input/output channels; in that said additional protection channels are interconnected to the usual input/output channels of each matrix element; and in that the size of each matrix of the central stage is equal or smaller than the one required to provide the 1 :N protection load generated by each input/output matrix connected thereto.

In this cross-connect core the cooperation among the elementary matrices, in order to solve the fault of one of them, is exclusively controlled by firmware and the size of the central stage is selected only depending on the number of common ports and of the selected protection ratio (1 :N), both for input/output ports and for protection ports, in order to allow undisturbed restoring of connections interrupted because of the fault and the matrix replacement with no disturb.

The invention is now illustrated more in depth, by way of example, for an optical, SSNB (Strict Sense Non Blocking) type cross-connect according to CIos' theorema, with reference to the enclosed drawings, wherein:

Fig. 1 shows an optical cross-connect architecture (E/OXC), which has already been described above, to which the inventive cross-connect core is applied;

Fig. 2 shows a connection architecture having 1 : 1 protection according to the prior art;

Fig. 3 shows a 20x20 cross-connect architecture, having protection ratio 1 :4 according to this invention;

Fig. 4 shows a possible synthesis of the 8x1 0 input matrices used in Fig. 3, by using smaller rectangular matrices, and a selector; and Fig. 5 shows the application of the invention to a cross-connect architecture with 544x544 ports, having a 1 : 1 6 protection ratio, due to the use of commercial matrix elements (68x68 instead of 64x64) .

As it has been set forth above, the invention consists in: using Input/Output elementary matrices having an amount of protection resource (that is: extra Input/Output channels) and in distributing this resource so that the Input/Output channels of each elementary matrix are interconnected with the protection channels of the other Input/Output elementary matrices; rearranging the interconnections among elementary matrices, in order to cope with the fault of one of them is performed by the Cross-connect firmware, with no extra switch element other than the ones contained in the elementary matrices required to actuate protection; the size of each central core elementary matrix shall be equal smaller to that required for carrying the 1 :N protection ratio generated by each Input/Output matrix connected to it; so for example, if the I/O stages connected to the central elementary matrix cover M traffic ports with 1 :N protection, so central elementary switch size should be smaller than 2*M/N X 2*M/N in order to satisfy CIos' condition, while in WSNB case (Wide Sense Non Blocking) the maximum size is 1 .5M/Nx1 .5M/N and in RNB case (Rearrangeable Non Blocking) the maximum size is M/NxM/N; all of this in order to allow an undisturbed restoring of the connections interrupted by the fault and the module replacement.

To illustrate the invention and its cost benefits, consider its application, which is shown in Fig. 3, to a 20x20 cross-connect with 1 :4 protection, then comparing the same to the 20x20 cross-connect having protection 1 : 1 , shown in Fig. 2. In Fig. 3 protection inputs/outputs have been drawn in dashed line, in order to make it clear how they are distributed to protect the Cross-Connect inputs/outputs.

As a general rule, the number of inputs/outputs of the lateral stages in the 1 :N protected Cross-Connect must be doubled with respect to the non-protected one but the core size must be increased only by 1 :N, due to the capacity added for protection purposes.

This is because input/output stages are not used in they full connectivity capability, but only for that required by single fault protection as it is shown in Fig. 4, where an assembly of smaller rectangular matrices 5 and a selector 6 are used. If purposely built elementary matrices are available and can be assembled, consisting of smaller crossbar matrices and selection tree matrices accordingly to Fig. 4, substantially reduction of conventional cost is obtained, which are determined depending on the number of elementary switchers. However, the implementation choice is a matter to be decided in the specific design process putting into the balance the higher flexibility offered by full crossbar matrices when scalability is to be taken into account and the available switch elements sizes and cost. Furthermore, the cost of elementary switch matrices is determined mainly by market criteria rather than by the only technological complexity.

It is easy to see that the 1 :N protected architecture is tolerant against every single fault with a single point fault at level of elementary switch matrix.

To show this fact, it can be observed that, should any input/output matrix fail, its task may be taken over by an equivalent number of protection channels, connected to its inputs/outputs, while the loss of an elementary matrix of the central core implies a connectivity loss equivalent to that required by the protection channels while normal traffic can be still satisfied.

In every case, the connections torn down by the single fault may be restored without affecting the others using the remaining protection resources; subsequent board substitution to restore the OXC full capability is hitless.

The advangages of using the proposed 1 :N protection scheme rely on the related Hardware simplification (that is recurring cost reduction and higher reliability) at expense of a slightly more complex Firmware (nonrecurring cost) .

A rough measure of the hardware simplification may be obtained by considering the number of single elementary switches, needed in the two alternative protection solutions.

Conventional 20X20, 1 : 1 protected system: ( 1 0x4x8 + 4x1 0x10)x2 = 1 440

Inventive 20X20, 1 :4 protected system: ( 10x8x10 + 5x10x10) = 1 300 with a saving in conventional costs around 7%

Inventive 20X20, 1 :4 protected system accordingly to Fig. 4:

( 1 0(5x1 0 + 1 x4) + 5x10x1 0) = 1 040, with a saving of 38% . Using integrated crossbar switch arrays (usually manufactured in "square" format; we should employ for instance 10x10 and 8x8 elementary matrices); the advantages becomes apparent:

20X20, 1 : 1 protected: (10x8x8 + 4x10x10)x2 = 2080

20X20, 1 :4 protected: (10x10x10 + 5x10x10) = 1 500

Saving in conventional cost: 28%.

This situation becomes even more favourable when it is considered that many vendors offer matrices with input/output size equal to a power of two plus a small amount (e.g. 68x68, 34x34) for ancillary purposes.

This fact is better exposed in Fig. 5 which shows an application of this invention over a 544x544 Cross-Connected system with 1 : 1 6 protection, using 68x68 elementary matrices.

The conventional cost for the 1 : 1 protected, 544X544 Cross-Connect is:

(48x68x68)x2 = 443904, while the 1 :16 protected Cross-Connect 544x544 shown in Fig. 5 core is: 51 x68x68 = 235824 with a savings of 47%.

Claims

1 . Electro and/or optical cross-connect core (E/OXC) in telecommunications, of the kind employing cross bars switch elements and/or selectors as building blocks and a three stage, SSNB, WSNB or RNB interconnecting architecture with suitable input and output cross connections, in order to provide a fault protection with protection ratio 1 :N, characterised in that the elementary input and output matrices of the cross-connect core involve protection resources consisting of additional input/output channels; in that said additional protection channels are interconnected with the ordinary input/output channels of each elementary matrix; and in that the size of each of the matrices in the central stage is equal or smaller than the one required to provide a 1 :N protection generated by each input/output matrix connected thereto.
2. Cross-connect core as set forth in claim 1 ., wherein the cooperation among the elementary matrices to solve the fault of one of them is controlled only by firmware.
3. Cross-connect core as set forth in claims 1 . and 2., wherein the size of the central stage is determined only depending on the number of ordinary ports and of the chosen protection redundancy ( 1 :N), both for input/output ports and for protection ports, so as to allow the undisturbed restoring of the connections interrupted by the fault and the matrix substitution, still without disturbs.
4. Architecture to provide the elementary matrices to be used in input and output stages of the cross-connect core as set forth in claims 1 . and 2., characterised in that it employs smaller elementary matrices, joined to a selection tree.
PCT/IT2001/000454 2001-08-31 2001-08-31 Three-stage non-blocking fault tolerant cross-connect architecture WO2003019879A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/IT2001/000454 WO2003019879A1 (en) 2001-08-31 2001-08-31 Three-stage non-blocking fault tolerant cross-connect architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IT2001/000454 WO2003019879A1 (en) 2001-08-31 2001-08-31 Three-stage non-blocking fault tolerant cross-connect architecture

Publications (1)

Publication Number Publication Date
WO2003019879A1 true true WO2003019879A1 (en) 2003-03-06

Family

ID=11133721

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IT2001/000454 WO2003019879A1 (en) 2001-08-31 2001-08-31 Three-stage non-blocking fault tolerant cross-connect architecture

Country Status (1)

Country Link
WO (1) WO2003019879A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4983961A (en) * 1988-01-29 1991-01-08 Ant Nachrichtentechnik Gmbh Three stage non-blocking switching array
US5229990A (en) * 1990-10-03 1993-07-20 At&T Bell Laboratories N+K sparing in a telecommunications switching environment
DE19805001A1 (en) * 1998-02-07 1999-08-12 Bosch Gmbh Robert Optical switching network

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4983961A (en) * 1988-01-29 1991-01-08 Ant Nachrichtentechnik Gmbh Three stage non-blocking switching array
US5229990A (en) * 1990-10-03 1993-07-20 At&T Bell Laboratories N+K sparing in a telecommunications switching environment
DE19805001A1 (en) * 1998-02-07 1999-08-12 Bosch Gmbh Robert Optical switching network

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHIH-CHIAN YANG ET AL: "RECONFIGURABLE FAULT TOLERANT NETWORKS FOR FAST PACKET SWITCHING", IEEE TRANSACTIONS ON RELIABILITY, IEEE INC. NEW YORK, US, vol. 40, no. 4, 1 October 1991 (1991-10-01), pages 474 - 487, XP000232098, ISSN: 0018-9529 *

Similar Documents

Publication Publication Date Title
Cao et al. Waveband switching in optical networks
US6023452A (en) Network failure restoration method with different recovery performances for different signal groups
Keslassy et al. Scaling internet routers using optics
Danielsen et al. Wavelength conversion in optical packet switching
US5884017A (en) Method and system for optical restoration tributary switching in a fiber network
US6616349B1 (en) Two-fiber interconnected ring architecture
US20090041457A1 (en) Modular WSS-based communications system with colorless add/drop interfaces
US7414985B1 (en) Link aggregation
US6579018B1 (en) Four-fiber ring optical cross connect system using 4×4 switch matrices
US20090232492A1 (en) Directionless optical architecture and highly available network and photonic resilience methods
US20040107382A1 (en) Method for network layer restoration using spare interfaces connected to a reconfigurable transport network
US20040233843A1 (en) Method and system for path protection in a communications network
US5912753A (en) Optical telecommunications network
US6696917B1 (en) Folded Clos architecture switching
US6243512B1 (en) Optical 2-fiber ring network
US20020159114A1 (en) Method and apparatus for routing signals through an optical network
US7403473B1 (en) Method and apparatus for accelerated protection switching in a multi-switch network element
US6226111B1 (en) Inter-ring cross-connect for survivable multi-wavelength optical communication networks
Gerstel et al. Fault tolerant multiwavelength optical rings with limited wavelength conversion
US5200746A (en) Switching module for digital cross-connect systems
US6061482A (en) Channel layered optical cross-connect restoration system
US5878177A (en) Layered switch architectures for high-capacity optical transport networks
US20040091198A1 (en) Modular photonic switch with wavelength conversion
US20040221058A1 (en) Nested protection switching in a mesh connected communications network
US20040037290A1 (en) Switching device for telecommunication networks

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BY BZ CA CH CN CO CR CU CZ DE DM DZ EC EE ES FI GB GD GE GH HR HU ID IL IN IS JP KE KG KP KR LC LK LR LS LT LU LV MA MD MG MN MW MX MZ NO NZ PH PL PT RO SD SE SG SI SK SL TJ TM TR TT TZ UG US UZ VN YU ZA

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ UG ZW AM AZ BY KG KZ MD TJ TM AT BE CH CY DE DK ES FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW MR NE SN TD TG

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase in:

Ref country code: JP