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A general input/output architecture protocol and related methods to manage data integrity

Info

Publication number
WO2003019391A3
WO2003019391A3 PCT/US2002/027043 US0227043W WO2003019391A3 WO 2003019391 A3 WO2003019391 A3 WO 2003019391A3 US 0227043 W US0227043 W US 0227043W WO 2003019391 A3 WO2003019391 A3 WO 2003019391A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
protocol
input
related
output
general
Prior art date
Application number
PCT/US2002/027043
Other languages
French (fr)
Other versions
WO2003019391A2 (en )
Inventor
Eric Wehage
Jasmin Ajanovic
David J Harriman
David M Lee
Blaise Fanning
Buck Gremel
Ken Creta
Wayne A Moore
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/10Flow control or congestion control
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Programme control for peripheral devices
    • G06F13/12Programme control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Programme control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/405Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4252Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a handshaking protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4269Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a handshaking protocol, e.g. Centronics connection
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/10Flow control or congestion control
    • H04L47/30Flow control or congestion control using information about buffer occupancy at either end or transit nodes

Abstract

An enhanced general input/output communication architectue, protocol and related methods are presented.
PCT/US2002/027043 2001-08-24 2002-08-23 A general input/output architecture protocol and related methods to manage data integrity WO2003019391A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US31470801 true 2001-08-24 2001-08-24
US60/314,708 2001-08-24

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE2002626627 DE60226627D1 (en) 2001-08-24 2002-08-23 Ehörige procedures to manage data integrity
KR20047002645A KR100624610B1 (en) 2001-08-24 2002-08-23 A general input/output architecture protocol and related methods to manage data integrity
EP20020761492 EP1442548B1 (en) 2001-08-24 2002-08-23 A general input/output inteface and related method to manage data integrity

Publications (2)

Publication Number Publication Date
WO2003019391A2 true WO2003019391A2 (en) 2003-03-06
WO2003019391A3 true true WO2003019391A3 (en) 2003-05-30

Family

ID=23221101

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2002/027043 WO2003019391A3 (en) 2001-08-24 2002-08-23 A general input/output architecture protocol and related methods to manage data integrity
PCT/US2002/026933 WO2003019393A1 (en) 2001-08-24 2002-08-23 A general intput/output architecture, protocol and related methods to implement flow control
PCT/US2002/027042 WO2003019394A1 (en) 2001-08-24 2002-08-23 A general input/output architecture, protocol and related methods to support legacy interrupts

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/US2002/026933 WO2003019393A1 (en) 2001-08-24 2002-08-23 A general intput/output architecture, protocol and related methods to implement flow control
PCT/US2002/027042 WO2003019394A1 (en) 2001-08-24 2002-08-23 A general input/output architecture, protocol and related methods to support legacy interrupts

Country Status (6)

Country Link
US (13) US7231486B2 (en)
KR (3) KR100647161B1 (en)
CN (3) CN100409606C (en)
DE (4) DE60222782D1 (en)
EP (3) EP1442548B1 (en)
WO (3) WO2003019391A3 (en)

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