WO2003005137A1 - Data processing - Google Patents
Data processing Download PDFInfo
- Publication number
- WO2003005137A1 WO2003005137A1 PCT/GB2002/002892 GB0202892W WO03005137A1 WO 2003005137 A1 WO2003005137 A1 WO 2003005137A1 GB 0202892 W GB0202892 W GB 0202892W WO 03005137 A1 WO03005137 A1 WO 03005137A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- state
- state machine
- parent
- child
- data processing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
- G06F9/4486—Formation of subprogram jump address
Definitions
- the invention relates to data processing and event handling.
- the invention relates to state machines.
- the invention provides a data processing system comprising a parent state machine and a child state machine each comprising a group of states interlinked by transitions, wherein the parent state machine comprises a parent exit state in which an appropriate event causes the execution of a parent exit transition to a state in the child state machine.
- the invention thus provides that a state machine can be decomposed into a hierarchy of interacting state machines.
- a complex system can be represented as a hierarchy of simpler state machines which facilitates efficient definition of the overall system.
- the data processing system according to the invention may also be arranged such that the parent exit transition is accompanied by deactivation of the parent state machine in favour of the child state machine. This means that the data processing system's resources need only be sufficient to run either the child or the parent state machine.
- the data processing system is arranged such that the parent exit transition is accompanied by storing of parameters defining the parent exit state used to depart the parent state machine into memory, e.g. a memory stack of the system.
- the parameters can be stored on the C-stack.
- the child state machine may comprise a child exit state in which an appropriate event causes the execution of a child exit transition to a state in the parent state machine.
- the data processing system can be adapted to provide a return path to the parent state machine.
- the child exit transition is accompanied by the deactivation of the child state machine in favour of the parent state machine, which means that the system resources need only be sufficient to run either the child or parent state machine at any one time.
- the child exit transition is accompanied by the retrieval from a memory e.g. a memory stack, of parameters defining the parent state machine state to which the child exit transition leads.
- the data processing system is arranged such that details of an event are saved into storage, e.g. a memory stack, if the event is not applicable to the state machine which is currently active.
- the data processing system may also be arranged such that details of an event saved in storage may be retrieved when a state machine to which the event applies becomes active in order to allow the event to be processed. For example, if, during operation of the child state machine, an event occurs which is applicable to the parent state machine, then the details of the event can be stored until such time as the parent state machine again becomes active, at which point the details of the event can be retrieved to allow the event to be processed by the parent state machine.
- the data processing system according to the invention may contain a hierarchy of more than two levels, i.e. more than just the "parent" and "child” levels discussed above.
- the child state machine may itself have a child state machine, and so on.
- the state machines in the hierarchy can be interlinked using exit transitions as discussed above.
- Figure 1 illustrates a state machine
- Figures 2 and 3 each illustrate a state machine implemented as a state-event matrix
- Figures 4 and 5 each illustrate state machines linked so as to call one another.
- the state machine of Figure 1 illustrates the simple case of an electric light operated by a push button switch.
- the system has two states A and B, in which the light is on and off respectively.
- the button When the button is pressed, the system toggles to the other one of its states. In other words, when the event of pressing the switch occurs, then, regardless of the current state, the "press" event triggers a transition to the other state. These transitions are indicated by the arrows in Figure 1.
- Figure 2 illustrates how the state machine of Figure 1 can be rendered as a state-event matrix.
- the state-event matrix of Figure 2 contains a column for each state and a row for each event.
- the state-event matrix comprises a single row for the "press” event and two columns, one each for the A and B states.
- the entries in the state-event matrix are populated with the necessary actions. If the current state is A, and the event is "press”, then the action is "go to state B". If the current state is B, and the event is "press”, then the action is "go to state A”.
- Figure 3 shows how the state-event matrix can be extended to arbitrary size, using the example of n columns for n states and m rows for m events.
- Figure 3 illustrates a state machine hierarchy according to an embodiment of the invention.
- the state machine hierarchy is implemented using a C-type programming language and comprises a parent state machine implemented as a parent state-event matrix 12 and a child state machine implemented as a child state-event matrix 10.
- a parent state machine is in a particular state, for example s m
- a particular event for example e n
- a sequence of actions are performed to call the child state machine.
- the parameter values defining state s m are saved onto the C-stack of the system, the parent state machine is closed, the child state machine is opened and a state of the child state machine, for example s p , is nominated as the active state.
- the active state moves around the child state event matrix 10 in accordance with whichever events occur.
- the child state machine is in a particular state, for example s r , and a particular event, for example, e q , occurs, then the active state is transferred back to the parent state machine.
- the child state machine is closed, the parameter values for the parent state machine are retrieved from the C-stack and the active state is assigned as the state in the parent state machine which is specified by the retrieved parameter values.
- the parent state machine or the child state machine is active at any given time. If an event occurs which cannot be processed by the state machine which is currently active, then it is saved onto the C-stack pending the activation of a state machine to which the event applies.
- the transitions between the state machines are shown by arrows 14 and 16.
- Figure 5 illustrates a state macliine hierarchy according to an embodiment of the invention being used to implement a controller for configuring telecommunications transceiver equipment, such as a mobile telephone.
- the state machine hierarchy is being used to configure a controller which works with a layered communications protocol, where inter-layer communication is achieved via signalling.
- layer N of a protocol is a controller layer which is responsible for configuring layers N-1 and N-2 in response to external signals.
- the parent state machine designated as an external signal handler in Figure 5 responds to the external signals by calling the layer N-1 or N-2 state machine to configure the N-1 and N-2 layers respectively.
- the child state machines each only contain state-event actions to handle responses from their respective layers, and do not respond to external signals. Any external signals received during the execution of a child state machine are saved for processing when the child state machine exits. This ensures that the state machine implementations are "clean", i.e. they only contain transitions relevant to their purpose.
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0116191.8 | 2001-07-02 | ||
GB0116191A GB2377285A (en) | 2001-07-02 | 2001-07-02 | State machine |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003005137A1 true WO2003005137A1 (en) | 2003-01-16 |
Family
ID=9917814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2002/002892 WO2003005137A1 (en) | 2001-07-02 | 2002-06-21 | Data processing |
Country Status (2)
Country | Link |
---|---|
GB (1) | GB2377285A (en) |
WO (1) | WO2003005137A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120282301A1 (en) * | 2005-12-06 | 2012-11-08 | Etex Corporation | Porous calcium phosphate bone material |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2929474B1 (en) * | 2008-03-28 | 2010-07-30 | Groupe Ecoles Telecomm | MULTI-LAYER HIERARCHISED COMPUTING ARCHITECTURE |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0570129A2 (en) * | 1992-05-02 | 1993-11-18 | Texas Instruments Incorporated | Improvements in or relating to state machines |
US5796752A (en) * | 1995-03-06 | 1998-08-18 | Motorola, Inc. | Method and apparatus for constructing verification test sequences by euler touring a test subsequence graph |
US6052455A (en) * | 1997-11-13 | 2000-04-18 | Northern Telecom Limited | Universal data structure for use with a concurrent state machine space in a telecommunications network |
WO2000038022A1 (en) * | 1998-12-22 | 2000-06-29 | Varian Semiconductor Equipment Associates, Inc. | Method and apparatus for controlling a system using hierarchical state machines |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01287739A (en) * | 1988-05-13 | 1989-11-20 | Matsushita Electric Ind Co Ltd | Automatic state transition table generating device |
US5721920A (en) * | 1994-08-05 | 1998-02-24 | Telefonaktiebolaget Lm Ericsson | Method and system for providing a state oriented and event driven environment |
IL119914A (en) * | 1996-12-25 | 2000-06-29 | Emultek Ltd | Device for implementing hierarchical state charts and methods and apparatus useful therefor |
-
2001
- 2001-07-02 GB GB0116191A patent/GB2377285A/en not_active Withdrawn
-
2002
- 2002-06-21 WO PCT/GB2002/002892 patent/WO2003005137A1/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0570129A2 (en) * | 1992-05-02 | 1993-11-18 | Texas Instruments Incorporated | Improvements in or relating to state machines |
US5796752A (en) * | 1995-03-06 | 1998-08-18 | Motorola, Inc. | Method and apparatus for constructing verification test sequences by euler touring a test subsequence graph |
US6052455A (en) * | 1997-11-13 | 2000-04-18 | Northern Telecom Limited | Universal data structure for use with a concurrent state machine space in a telecommunications network |
WO2000038022A1 (en) * | 1998-12-22 | 2000-06-29 | Varian Semiconductor Equipment Associates, Inc. | Method and apparatus for controlling a system using hierarchical state machines |
Non-Patent Citations (2)
Title |
---|
ANTONIAZZI S ET AL: "A methodology for control-dominated systems codesign", HARDWARE/SOFTWARE CODESIGN, 1994., PROCEEDINGS OF THE THIRD INTERNATIONAL WORKSHOP ON GRENOBLE, FRANCE 22-24 SEPT. 1994, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, PAGE(S) 2-9, ISBN: 0-8186-6315-4, XP010099865 * |
JIRACHIEFPATTANA A ET AL: "Verifying Estelle specifications: numerical Petri nets approach", NETWORK PROTOCOLS, 1993. PROCEEDINGS., 1993 INTERNATIONAL CONFERENCE ON SAN FRANCISCO, CA, USA 19-22 OCT. 1993, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, PAGE(S) 334-341, ISBN: 0-8186-3670-X, XP010095551 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120282301A1 (en) * | 2005-12-06 | 2012-11-08 | Etex Corporation | Porous calcium phosphate bone material |
US8545858B2 (en) * | 2005-12-06 | 2013-10-01 | Etex Corporation | Porous calcium phosphate bone material |
Also Published As
Publication number | Publication date |
---|---|
GB0116191D0 (en) | 2001-08-22 |
GB2377285A (en) | 2003-01-08 |
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