WO2003001532A3 - Current source and drain arrangement for magnetoresistive memories (mrams) - Google Patents

Current source and drain arrangement for magnetoresistive memories (mrams) Download PDF

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Publication number
WO2003001532A3
WO2003001532A3 PCT/US2002/003042 US0203042W WO03001532A3 WO 2003001532 A3 WO2003001532 A3 WO 2003001532A3 US 0203042 W US0203042 W US 0203042W WO 03001532 A3 WO03001532 A3 WO 03001532A3
Authority
WO
WIPO (PCT)
Prior art keywords
bit lines
mrams
current source
array
drain arrangement
Prior art date
Application number
PCT/US2002/003042
Other languages
French (fr)
Other versions
WO2003001532A2 (en
Inventor
Stefan Lammers
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/885,759 external-priority patent/US6594176B2/en
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Priority to DE60223161T priority Critical patent/DE60223161T2/en
Priority to CN028071743A priority patent/CN1535467B/en
Priority to JP2003507828A priority patent/JP4381803B2/en
Priority to KR1020037009795A priority patent/KR100565113B1/en
Priority to EP02723083A priority patent/EP1433181B1/en
Publication of WO2003001532A2 publication Critical patent/WO2003001532A2/en
Publication of WO2003001532A3 publication Critical patent/WO2003001532A3/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the cross-points in the array. A bit decoder and word decoder are coupled to the bit lines and word lines, respectively. A first series of switch circuits are coupled to and located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines such that a shortened programming current path is provided which results in decreased resistance across the device.
PCT/US2002/003042 2001-01-24 2002-01-25 Current source and drain arrangement for magnetoresistive memories (mrams) WO2003001532A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE60223161T DE60223161T2 (en) 2001-06-20 2002-01-25 POWER SOURCE AND DRAIN ARRANGEMENT FOR MAGNETORESITIVE STORAGE
CN028071743A CN1535467B (en) 2001-06-20 2002-01-25 Memory device, method for manufacturing memory device and method for programming the memory device
JP2003507828A JP4381803B2 (en) 2001-06-20 2002-01-25 Configuration of current supply unit and discharge unit of magnetoresistive memory device (MRAM)
KR1020037009795A KR100565113B1 (en) 2001-06-20 2002-01-25 Current source and drain arrangement for magnetoresistive memoriesmrams
EP02723083A EP1433181B1 (en) 2001-06-20 2002-01-25 Current source and drain arrangement for magnetoresistive memories (mrams)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US26399001P 2001-01-24 2001-01-24
US60/263,909 2001-01-24
US09/885,759 US6594176B2 (en) 2001-01-24 2001-06-20 Current source and drain arrangement for magnetoresistive memories (MRAMs)
US09/885,759 2001-06-20

Publications (2)

Publication Number Publication Date
WO2003001532A2 WO2003001532A2 (en) 2003-01-03
WO2003001532A3 true WO2003001532A3 (en) 2003-12-31

Family

ID=32095651

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/003042 WO2003001532A2 (en) 2001-01-24 2002-01-25 Current source and drain arrangement for magnetoresistive memories (mrams)

Country Status (1)

Country Link
WO (1) WO2003001532A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7193881B2 (en) * 2004-07-01 2007-03-20 Thin Film Electronics Asa Cross-point ferroelectric memory that reduces the effects of bit line to word line shorts

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682200A (en) * 1985-04-12 1987-07-21 Hitachi, Ltd. Semiconductor memory device with matched equivalent series resistances to the complementary data lines
US5811863A (en) * 1994-11-02 1998-09-22 Lsi Logic Corporation Transistors having dynamically adjustable characteristics
US6236611B1 (en) * 1999-12-20 2001-05-22 Motorola, Inc. Peak program current reduction apparatus and method
US20020003720A1 (en) * 2000-07-03 2002-01-10 Thomas Bohm MRAM configuration
US20020097602A1 (en) * 2001-01-24 2002-07-25 Infineon Technologies North America Corp. Current source and drain arrangement for magnetoresistive memories (MRAMS)

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682200A (en) * 1985-04-12 1987-07-21 Hitachi, Ltd. Semiconductor memory device with matched equivalent series resistances to the complementary data lines
US5811863A (en) * 1994-11-02 1998-09-22 Lsi Logic Corporation Transistors having dynamically adjustable characteristics
US6236611B1 (en) * 1999-12-20 2001-05-22 Motorola, Inc. Peak program current reduction apparatus and method
US20020003720A1 (en) * 2000-07-03 2002-01-10 Thomas Bohm MRAM configuration
US20020097602A1 (en) * 2001-01-24 2002-07-25 Infineon Technologies North America Corp. Current source and drain arrangement for magnetoresistive memories (MRAMS)

Also Published As

Publication number Publication date
WO2003001532A2 (en) 2003-01-03

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