WO2002103584A3 - Phase and generator based soc design and/or verification - Google Patents

Phase and generator based soc design and/or verification Download PDF

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Publication number
WO2002103584A3
WO2002103584A3 PCT/US2002/017368 US0217368W WO02103584A3 WO 2002103584 A3 WO2002103584 A3 WO 2002103584A3 US 0217368 W US0217368 W US 0217368W WO 02103584 A3 WO02103584 A3 WO 02103584A3
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WO
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Application
Patent type
Prior art keywords
design
verification
generation phase
phase
process
Prior art date
Application number
PCT/US2002/017368
Other languages
French (fr)
Other versions
WO2002103584A2 (en )
Inventor
Michael C Brouhard
Michael Y Chen
John Wilson
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/66IP blocks

Abstract

An EDA tool suite is equipped with the ability to responsively invoke a chain of one or more generators corresponding to one or more phases of a design/verification process to process to process design information of IP blocks forming a SOC design to transform the design information, as a result of each invocation, from one state to another state. In one embodiment , the phases may be one or more of a design generation phase, a simulation hardware logic generation phase, an embedded/diagnostic software generation phase, and a verification environment configuration script generation phase.
PCT/US2002/017368 2001-06-16 2002-05-31 Phase and generator based soc design and/or verification WO2002103584A3 (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
US29877201 true 2001-06-16 2001-06-16
US29877101 true 2001-06-16 2001-06-16
US29875101 true 2001-06-16 2001-06-16
US60/298,772 2001-06-16
US60/298,771 2001-06-16
US60/298,751 2001-06-16
US10132040 US20030005396A1 (en) 2001-06-16 2002-04-24 Phase and generator based SOC design and/or verification
US10/132,020 2002-04-24
US10132587 US6757882B2 (en) 2001-06-16 2002-04-24 Self-describing IP package for enhanced platform based SOC design
US10132020 US20030009730A1 (en) 2001-06-16 2002-04-24 Enhanced platform based SOC design including exended peripheral selection and automated IP customization facilitation
US10/132,040 2002-04-24
US10/132,587 2002-04-24

Publications (2)

Publication Number Publication Date
WO2002103584A2 true WO2002103584A2 (en) 2002-12-27
WO2002103584A3 true true WO2002103584A3 (en) 2004-08-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/017368 WO2002103584A3 (en) 2001-06-16 2002-05-31 Phase and generator based soc design and/or verification

Country Status (1)

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WO (1) WO2002103584A3 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0309528D0 (en) * 2003-04-25 2003-06-04 Beach Solutions Ltd Database population system
US7571414B2 (en) * 2006-06-15 2009-08-04 National Chip Implementation Center, National Applied Research Laboratories Multi-project system-on-chip and its method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841663A (en) * 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
WO1999042930A2 (en) * 1998-02-20 1999-08-26 Lsi Logic Corporation Method and apparatus for logic synthesis
US6226780B1 (en) * 1998-08-31 2001-05-01 Mentor Graphics Corporation Circuit design method and apparatus supporting a plurality of hardware design languages
WO2001042969A2 (en) * 1999-12-03 2001-06-14 Synchronicity, Software, Inc. Ip library management system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841663A (en) * 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
WO1999042930A2 (en) * 1998-02-20 1999-08-26 Lsi Logic Corporation Method and apparatus for logic synthesis
US6226780B1 (en) * 1998-08-31 2001-05-01 Mentor Graphics Corporation Circuit design method and apparatus supporting a plurality of hardware design languages
WO2001042969A2 (en) * 1999-12-03 2001-06-14 Synchronicity, Software, Inc. Ip library management system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BERGAMASCHI R ET AL: "Coral-automating the design of systems-on-chip using cores", PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE. (CICC 2000). ORLANDO, FL, MAY 21-24, 2000, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE.CICC, NEW YORK, NY: IEEE, US, vol. CONF. 22, 21 May 2000 (2000-05-21), pages 109 - 112, XP002186200, ISBN: 0-7803-5810-4 *

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