WO2002099809A3 - Method and device for masking out non-serviceable memory cells - Google Patents

Method and device for masking out non-serviceable memory cells Download PDF

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Publication number
WO2002099809A3
WO2002099809A3 PCT/EP2002/006145 EP0206145W WO02099809A3 WO 2002099809 A3 WO2002099809 A3 WO 2002099809A3 EP 0206145 W EP0206145 W EP 0206145W WO 02099809 A3 WO02099809 A3 WO 02099809A3
Authority
WO
WIPO (PCT)
Prior art keywords
physical
serviceable
memory
mapping
memory cells
Prior art date
Application number
PCT/EP2002/006145
Other languages
German (de)
French (fr)
Other versions
WO2002099809A2 (en
Inventor
Gerd Dirscherl
Heimo Hartlieb
Christian May
Holger Sedlak
Original Assignee
Infineon Technologies Ag
Gerd Dirscherl
Heimo Hartlieb
Christian May
Holger Sedlak
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Gerd Dirscherl, Heimo Hartlieb, Christian May, Holger Sedlak filed Critical Infineon Technologies Ag
Publication of WO2002099809A2 publication Critical patent/WO2002099809A2/en
Publication of WO2002099809A3 publication Critical patent/WO2002099809A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

The invention relates to a method for controlling the mapping of a logical address of a logical address space to a physical address of a physical address space (20). Said method involves the following steps: a first physical address and a corresponding memory cell, which are associated by the mapping (30) of a logical address, are determined; the memory cell is checked for serviceability; and the mapping (30) is modified if the check reveals that the memory cell is not serviceable, in such a way that the logical address is mapped to a second physical address in the physical address space (20). In this way, access to a physical memory is carried out by means of logical addresses which are mapped to the physical addresses of the physical memory, i.e. virtual memory addressing is used in order to mask out non-serviceable memory cells in a simple and effective manner.
PCT/EP2002/006145 2001-06-05 2002-06-04 Method and device for masking out non-serviceable memory cells WO2002099809A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2001127194 DE10127194B4 (en) 2001-06-05 2001-06-05 Method and device for hiding non-functional memory cells
DE10127194.8 2001-06-05

Publications (2)

Publication Number Publication Date
WO2002099809A2 WO2002099809A2 (en) 2002-12-12
WO2002099809A3 true WO2002099809A3 (en) 2003-10-23

Family

ID=7687205

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/006145 WO2002099809A2 (en) 2001-06-05 2002-06-04 Method and device for masking out non-serviceable memory cells

Country Status (3)

Country Link
DE (1) DE10127194B4 (en)
TW (1) TW559822B (en)
WO (1) WO2002099809A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004008180A1 (en) * 2004-02-19 2005-09-01 Giesecke & Devrient Gmbh Secure operating method for a portable data carrier, especially a chip card, in which operating parameter values are checked during a memory access or data output process to see if their values have been changed
KR100606173B1 (en) 2004-08-24 2006-08-01 삼성전자주식회사 Method and apparatus for verifying an initial state of non-volatile memory device
DE102004059206B4 (en) 2004-12-09 2016-03-31 Polaris Innovations Ltd. Memory device and addressing of memory cells
KR101011171B1 (en) * 2005-12-28 2011-01-26 후지쯔 가부시끼가이샤 Method, storage medium, and apparatus for controlling memory, and information processing apparatus
US7921263B2 (en) * 2006-12-22 2011-04-05 Broadcom Corporation System and method for performing masked store operations in a processor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999038066A1 (en) * 1998-01-22 1999-07-29 Memory Corporation Plc Flash memory system
US6163490A (en) * 1998-02-25 2000-12-19 Micron Technology, Inc. Semiconductor memory remapping

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999038066A1 (en) * 1998-01-22 1999-07-29 Memory Corporation Plc Flash memory system
US6163490A (en) * 1998-02-25 2000-12-19 Micron Technology, Inc. Semiconductor memory remapping

Also Published As

Publication number Publication date
WO2002099809A2 (en) 2002-12-12
DE10127194A1 (en) 2002-12-19
TW559822B (en) 2003-11-01
DE10127194B4 (en) 2008-08-21

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