WO2002095722A3 - Multi-channel, demand-driven display controller - Google Patents

Multi-channel, demand-driven display controller Download PDF

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Publication number
WO2002095722A3
WO2002095722A3 PCT/US2002/015807 US0215807W WO02095722A3 WO 2002095722 A3 WO2002095722 A3 WO 2002095722A3 US 0215807 W US0215807 W US 0215807W WO 02095722 A3 WO02095722 A3 WO 02095722A3
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
display
request
buffer
frame buffer
Prior art date
Application number
PCT/US2002/015807
Other languages
French (fr)
Other versions
WO2002095722A2 (en
Inventor
Michael A Wasserman
Michael G Lavelle
David C Kehlet
Nathaniel David Naegle
Steven Te-Chun-Yu
Glenn Gracon
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to EP02771850A priority Critical patent/EP1388047A2/en
Priority to JP2002592102A priority patent/JP2004536388A/en
Priority to AU2002308761A priority patent/AU2002308761A1/en
Publication of WO2002095722A2 publication Critical patent/WO2002095722A2/en
Publication of WO2002095722A3 publication Critical patent/WO2002095722A3/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Computer Graphics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Digital Computer Display Output (AREA)
  • Image Generation (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

A graphics system that may be shared between multiple display channels includes a frame buffer (22), two arbiters (805, 817), a pixel buffer (815), and several display output queues (821A, 821B). The first arbiter (805) arbitrates between the display channels' requests for display information from the frame buffer (22) and forwards a selected request to the frame buffer (22). The frame buffer (22) outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer (815). Each display channel has a corresponding display output queue (821A, 821B) that provides data to a display and generates a request for pixels from the pixel buffer (815). A pixel request arbiter (817) receives the pixel requests generated by the display output queues (821A, 821B), selects one of the pixel requests, and forwards the selected request to the pixel buffer (815). In response, the pixel buffer (815) outputs pixels to the display output queue (821A, 821B) that generated the selected pixel request.
PCT/US2002/015807 2001-05-18 2002-05-17 Multi-channel, demand-driven display controller WO2002095722A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP02771850A EP1388047A2 (en) 2001-05-18 2002-05-17 Multi-channel, demand-driven display controller
JP2002592102A JP2004536388A (en) 2001-05-18 2002-05-17 Multi-channel, demand-driven display controller
AU2002308761A AU2002308761A1 (en) 2001-05-18 2002-05-17 Multi-channel, demand-driven display controller

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/861,461 US6654021B2 (en) 2001-05-18 2001-05-18 Multi-channel, demand-driven display controller
US09/861,461 2001-05-18

Publications (2)

Publication Number Publication Date
WO2002095722A2 WO2002095722A2 (en) 2002-11-28
WO2002095722A3 true WO2002095722A3 (en) 2003-05-22

Family

ID=25335859

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/015807 WO2002095722A2 (en) 2001-05-18 2002-05-17 Multi-channel, demand-driven display controller

Country Status (5)

Country Link
US (1) US6654021B2 (en)
EP (1) EP1388047A2 (en)
JP (1) JP2004536388A (en)
AU (1) AU2002308761A1 (en)
WO (1) WO2002095722A2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030011534A1 (en) * 2001-07-13 2003-01-16 International Business Machines Corporation Display privacy for enhanced presentations with real-time updates
US6760032B1 (en) * 2002-03-14 2004-07-06 Nvidia Corporation Hardware-implemented cellular automata system and method
US6831658B2 (en) * 2002-07-22 2004-12-14 Sun Microsystems, Inc. Anti-aliasing interlaced video formats for large kernel convolution
US7245272B2 (en) * 2002-10-19 2007-07-17 Via Technologies, Inc. Continuous graphics display for dual display devices during the processor non-responding period
US7313764B1 (en) * 2003-03-06 2007-12-25 Apple Inc. Method and apparatus to accelerate scrolling for buffered windows
DE102004039932A1 (en) * 2004-08-17 2006-03-09 Phoenix Contact Gmbh & Co. Kg Method and device for bus connection of safety-relevant processes
US7542010B2 (en) * 2005-07-28 2009-06-02 Seiko Epson Corporation Preventing image tearing where a single video input is streamed to two independent display devices
US20090085928A1 (en) * 2006-05-12 2009-04-02 Nvidia Corporation Antialiasing using multiple display heads of a graphics processor
US8130227B2 (en) * 2006-05-12 2012-03-06 Nvidia Corporation Distributed antialiasing in a multiprocessor graphics system
US7876329B2 (en) * 2007-09-10 2011-01-25 Via Technologies, Inc. Systems and methods for managing texture data in a computer
US20100005494A1 (en) * 2008-07-01 2010-01-07 International Business Machines Corporation Administering digital media streams
WO2011049881A2 (en) * 2009-10-19 2011-04-28 Barnes & Noble, Inc. Apparatus and method for control of multiple displays from a single virtual frame buffer
KR102458124B1 (en) * 2013-03-15 2022-10-21 매직 립, 인코포레이티드 Display system and method
US10613811B2 (en) 2017-03-13 2020-04-07 Qualcomm Incorporated Driving multiple display devices with a single display port

Citations (5)

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Publication number Priority date Publication date Assignee Title
US6043798A (en) * 1996-06-26 2000-03-28 Canon Kabushiki Kaisha Display apparatus and data transfer apparatus for display device
US6118413A (en) * 1995-06-07 2000-09-12 Cirrus Logic, Inc. Dual displays having independent resolutions and refresh rates
US6204864B1 (en) * 1995-06-07 2001-03-20 Seiko Epson Corporation Apparatus and method having improved memory controller request handler
US6208325B1 (en) * 1993-10-01 2001-03-27 Cirrus Logic, Inc. Image rotation for video displays
US6215459B1 (en) * 1993-10-01 2001-04-10 Cirrus Logic, Inc. Dual display video controller

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Publication number Priority date Publication date Assignee Title
US5537128A (en) 1993-08-04 1996-07-16 Cirrus Logic, Inc. Shared memory for split-panel LCD display systems
DE69518778T2 (en) 1994-03-16 2001-02-01 Brooktree Corp Multimedia graphic systems with a constantly high clock rate
EP0791265B1 (en) 1994-11-10 2002-01-30 Brooktree Corporation System and method for generating video in a computer system
US5767866A (en) * 1995-06-07 1998-06-16 Seiko Epson Corporation Computer system with efficient DRAM access
US5805173A (en) 1995-10-02 1998-09-08 Brooktree Corporation System and method for capturing and transferring selected portions of a video stream in a computer system
US5754170A (en) * 1996-01-16 1998-05-19 Neomagic Corp. Transparent blocking of CRT refresh fetches during video overlay using dummy fetches
US5949437A (en) 1997-02-19 1999-09-07 Appian Graphics Corp. Dual video output board with a shared memory interface
US6020901A (en) 1997-06-30 2000-02-01 Sun Microsystems, Inc. Fast frame buffer system architecture for video display system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6208325B1 (en) * 1993-10-01 2001-03-27 Cirrus Logic, Inc. Image rotation for video displays
US6215459B1 (en) * 1993-10-01 2001-04-10 Cirrus Logic, Inc. Dual display video controller
US6118413A (en) * 1995-06-07 2000-09-12 Cirrus Logic, Inc. Dual displays having independent resolutions and refresh rates
US6204864B1 (en) * 1995-06-07 2001-03-20 Seiko Epson Corporation Apparatus and method having improved memory controller request handler
US6043798A (en) * 1996-06-26 2000-03-28 Canon Kabushiki Kaisha Display apparatus and data transfer apparatus for display device

Also Published As

Publication number Publication date
EP1388047A2 (en) 2004-02-11
AU2002308761A1 (en) 2002-12-03
JP2004536388A (en) 2004-12-02
US6654021B2 (en) 2003-11-25
WO2002095722A2 (en) 2002-11-28
US20030043155A1 (en) 2003-03-06

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