WO2002073681A1 - Method and composition for polishing by cmp - Google Patents

Method and composition for polishing by cmp Download PDF

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Publication number
WO2002073681A1
WO2002073681A1 PCT/US2001/007734 US0107734W WO02073681A1 WO 2002073681 A1 WO2002073681 A1 WO 2002073681A1 US 0107734 W US0107734 W US 0107734W WO 02073681 A1 WO02073681 A1 WO 02073681A1
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Prior art keywords
polishing
copper
polishing composition
high points
ions
Prior art date
Application number
PCT/US2001/007734
Other languages
French (fr)
Inventor
Terence M. Thomas
Qianquiu Ye
Joseph K. So
Wendy B. Goldberg
Wade Godfrey
Original Assignee
Rodel Holdings, Inc.
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Filing date
Publication date
Application filed by Rodel Holdings, Inc. filed Critical Rodel Holdings, Inc.
Priority to PCT/US2001/007734 priority Critical patent/WO2002073681A1/en
Priority to KR1020037011765A priority patent/KR100762424B1/en
Priority to EP01916557A priority patent/EP1380048A1/en
Priority to JP2002572628A priority patent/JP2004523123A/en
Publication of WO2002073681A1 publication Critical patent/WO2002073681A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F3/00Brightening metals by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]

Definitions

  • the invention pertains to polishing methods and slurry formulations used in the planarizafion of integrated circuit surfaces containing various films, most particularly those of a metal, a barrier or liner layer, and a dielectric layer on a semiconductor wafer.
  • U.S. Pat. No. 5,676,587 discloses a two-step polishing process to be used with Cu interconnect structures. The first step is performed to remove most of the overburden of Cu, and the second step is performed to remove the barrier or liner layer of Ta, TaN, Ti, or TiN. For the second step, a silica based slurry of near-neutral pH is disclosed.
  • One of the problems resulting from polishing a semiconductor wafer by CMP is that the copper interconnect structures, providing electrical circuit interconnects, have a surface roughness that exceeds acceptable limits as specified by manufacturing standards. It has been recognized that an excessive surface roughness occurs from the rigors of CMP polishing. A need has existed for a process of polishing a semiconductor wafer that smoothes the surface roughness to acceptable limits. Further, a need has existed for a polishing composition for polishing a semiconductor wafer with interconnects having a surface roughness within acceptable limits.
  • the invention includes a method for polishing a semiconductor wafer, includes the steps of: providing a fluid polishing composition with chloride ions, polishing a barrier layer on the semiconductor wafer with the fluid polishing composition to remove the barrier layer and to polish high points on copper interconnects and solublize copper ions in the polishing composition, and replating the copper ions from solution in the fluid polishing composition to smooth the surface of the copper interconnects, while the chloride ions migrate near the high points to deter replating of copper ions onto the high points. By deterring such copper replating from the high points, the surface of the copper interconnects become smoothed to have a surface roughness within acceptable limits as specified by manufacturing standards.
  • the invention includes a polishing composition for polishing a semiconductor wafer includes a source of chloride ions in solution that migrate to high points on copper interconnects that are below a polished surface of the semiconductor wafer to deter replating of copper ions from solution onto the high points.
  • a semiconductor wafer is constructed of three different films or layers: a conductive metal layer, a barrier or liner layer between the conductive metal layer and a dielectric layer, and the dielectric layer.
  • a semiconductor wafer is constructed with, a conductive copper layer, a barrier layer of tantalum or tantalum nitride, and a dielectric layer of silicon dioxide. Polishing by performing CMP removes the Cu and Ta/TaN barrier layer as fast as possible, while removing the SiO 2 dielectric layer as slow as possible. Further, It is critical to retain conductive circuit interconnects recessed below the surface being polished. Removal of Cu within the interconnect structure is undesirable, and is known as “dishing”. Removal of the SiO 2 dielectric layer within the interconnect structure is undesirable, and is known as "erosion”.
  • chloride ions will bond to a semiconductor surface, and is present as a mobile species able to rapidly move over the surface. These mobile species will equilibrate to specific sites to minimize the energy of the system. These same localized high surface energy sites are the sites where defects initiate. The presence of the chloride ions at these sites decreases the surface energy at these sites to make them essentially indistinguishable from the surface energy at any other site. The uniform surface energy negates localized non-uniform processes and variations in the surface condition of the wafer. Since this is a surface phenomenon, the amount of a compound providing chloride ions necessary to cause this negation of localized variations may be as low as 5 ppm. Preferably the amount of compound used is between 7 and 2000 ppm. Most preferably between 10 and 1000 ppm.
  • compositions useful in polishing copper typically comprise a complexing agent providing copper ions in solution in the composition, such as citric acid; an inhibitor of initial corrosion, such as benzotriazole; and an organic polymer, such as polyvinyl pyrrolidone.
  • the composition includes an abrasive in the form of colloidal silica particles in fluid suspension, to be used with a polishing pad that is without abrasives.
  • the abrasive is absent from the composition, such that the composition is abrasive free to be used with a polishing pad that itself has abrasives.
  • compositions A and B were made comprising colloidal silica, citric acid, BTA (benzotriazole), and PVP (polyvinyl pyrrolidone). Further, composition B was made to include 5 to 10000 ppm, parts per million of ammonium chloride and 0.01% of ammonium perchlorate, all being in weight per cent. Patterned wafers comprising copper interconnects were polished on an IPEC Westech 372 polisher under standard conditions using compositions A and B. Surface roughness was measured using an AFM (Atomic Force Microscope) available from Digital Instruments, Inc.
  • AFM Anamic Force Microscope
  • the table discloses the improvement in roughness when a small amount of chloride ions are added to a polishing composition.
  • Such chloride ions are present in a polishing composition to improve surface roughness of the copper interconnects as a result of first step polishing and/or second step polishing.
  • first step polishing is performed, with a polishing pad and a polishing composition, according to a known CMP process to remove excess copper metal from an underlying barrier layer, while leaving patterned copper in a pattern of trenches below the polished surface of the barrier layer.
  • the patterned copper provides the electrical circuit interconnects in the trenches.
  • first step polishing tends to leave the patterned copper with a surface roughness that exceeds allowable limits that are specified by manufacturing standards.
  • Surface roughness can be considered as having high points on the surface of the patterned copper. Some of the high points can be quite sharp. Others are less sharp, but nonetheless, exceed the allowable limits for surface roughness.
  • the surface roughness could have been avoided by providing chloride ions in the polishing composition that accompanies first step polishing.
  • excessive surface roughness that results from first step polishing is reduced in roughness by performing second step polishing with a polishing composition containing chloride ions.
  • Such high points can be considered as being high energy areas, as in a situation wherein the patterned copper is wetted by the polishing composition and carries an electrical charge, resulting in an electrical field concentrating at the high points.
  • second step polishing is performed by a known CMP process to remove the barrier layer from an underlying dielectric layer, and to leave the copper interconnects in the trenches that are recessed below a polished surface of the dielectric layer.
  • chloride ions provided in a fluid polishing composition, reduces surface roughness of the copper interconnects, such that the surface roughness is within the allowable limits.
  • Second step polishing by a known CMP process is performed with a fluid polishing composition that, either has an oxidizer that is selective to removal of the material forming the barrier layer and selective to removal of copper, or that is without an oxidizer that is selective to removal of copper while being selective to removal of the barrier layer.
  • Second step polishing is performed to remove the barrier layer by polishing action, and to a lesser extent, to remove high points of copper by the polishing action and provide copper ions that solublize, in solution with the fluid polishing composition.
  • chloride ions are provided in the fluid polishing composition.
  • the chloride ions tend to migrate to the high energy areas, and tend to null the electrical field and prevent replating of copper ions, and the formation of nodules and/or dendrites, on the high energy areas.
  • the chloride ions replate evenly over the surface of the interconnects, which reduces the surface roughness to within acceptable limits.
  • polishing During polishing, migration of the chloride ions to the high points, nulls the electrical field concentrated at the high energy areas, which deters the attraction of copper ions for replating from solution onto the high points on the patterned copper. Copper ions replate from solution in a distributed manner on the copper surface, and less preferably accumulate on the high points. Further, polishing with or without an oxidizer in the polishing composition, polishes the high points, and removes copper therefrom.
  • polishing the high points serves to remove the high energy areas, such that copper ions replate from solution in a distributed manner, which contributes to smoothing the surface roughness to be within acceptable limits.
  • Second step polishing removes oxidized copper from the high points, and, as known in the field of CMP polishing, removed oxide ions tend to remain in solution with the fluid polishing composition.
  • the oxidizer contributes to removal of high points on the copper surface, which contributes to smoothing the surface roughness to be within acceptable limits.
  • a balance is struck by the concentration of the oxidizer and the concentration of chloride ions, such that chloride ions are present in a concentration sufficient to be near to each of the high energy areas, and deter the attraction of copper ions for replating from solution onto the high energy areas.
  • the chloride ions in the polishing composition are mobile species of ions.
  • the high energy areas are substantially eliminated, and the chloride ions in the polishing composition are mobile and free of attraction to high energy areas.
  • the mobile chloride ions are readily displaced by agitation away from the polished surface, which allows polishing to operate without interference by the chloride ions.

Abstract

A polishing composition for polishing a semiconductor wafer includes a source of chloride ions in solution, which reduces surface roughness of copper interconnects that are recessed in the wafer. High points on the copper interconnects are polished during a polishing operation, while the chloride ions migrate to electric fields concentrated at the high points. The chloride ions at the high points deter replating of copper ions from solution onto the high points. The copper ions replate evenly over the surface on the interconnects, which reduces the surface roughness of the interconnects.

Description

METHOD AND COMPOSITION FOR POLISHING BY CMP
The invention pertains to polishing methods and slurry formulations used in the planarizafion of integrated circuit surfaces containing various films, most particularly those of a metal, a barrier or liner layer, and a dielectric layer on a semiconductor wafer. U.S. Pat. No. 5,676,587 discloses a two-step polishing process to be used with Cu interconnect structures. The first step is performed to remove most of the overburden of Cu, and the second step is performed to remove the barrier or liner layer of Ta, TaN, Ti, or TiN. For the second step, a silica based slurry of near-neutral pH is disclosed.
One of the problems resulting from polishing a semiconductor wafer by CMP, is that the copper interconnect structures, providing electrical circuit interconnects, have a surface roughness that exceeds acceptable limits as specified by manufacturing standards. It has been recognized that an excessive surface roughness occurs from the rigors of CMP polishing. A need has existed for a process of polishing a semiconductor wafer that smoothes the surface roughness to acceptable limits. Further, a need has existed for a polishing composition for polishing a semiconductor wafer with interconnects having a surface roughness within acceptable limits.
The invention includes a method for polishing a semiconductor wafer, includes the steps of: providing a fluid polishing composition with chloride ions, polishing a barrier layer on the semiconductor wafer with the fluid polishing composition to remove the barrier layer and to polish high points on copper interconnects and solublize copper ions in the polishing composition, and replating the copper ions from solution in the fluid polishing composition to smooth the surface of the copper interconnects, while the chloride ions migrate near the high points to deter replating of copper ions onto the high points. By deterring such copper replating from the high points, the surface of the copper interconnects become smoothed to have a surface roughness within acceptable limits as specified by manufacturing standards.
Further the invention includes a polishing composition for polishing a semiconductor wafer includes a source of chloride ions in solution that migrate to high points on copper interconnects that are below a polished surface of the semiconductor wafer to deter replating of copper ions from solution onto the high points.
Embodiments of the invention will now be described by way of example with reference to the following detailed description. One of the requirements in the production of increasingly complex and dense semiconductor structures is the ability to planarize, without which ability, the complexity and density of the structures constructed on a semiconductor wafer are greatly limited. Chemical-Mechanical Planarization, or CMP, has proved to be the most effective method to planarize surface films on semiconductor substrates.
A semiconductor wafer is constructed of three different films or layers: a conductive metal layer, a barrier or liner layer between the conductive metal layer and a dielectric layer, and the dielectric layer. For example, a semiconductor wafer is constructed with, a conductive copper layer, a barrier layer of tantalum or tantalum nitride, and a dielectric layer of silicon dioxide. Polishing by performing CMP removes the Cu and Ta/TaN barrier layer as fast as possible, while removing the SiO2 dielectric layer as slow as possible. Further, It is critical to retain conductive circuit interconnects recessed below the surface being polished. Removal of Cu within the interconnect structure is undesirable, and is known as "dishing". Removal of the SiO2 dielectric layer within the interconnect structure is undesirable, and is known as "erosion".
According to an aspect of the invention, chloride ions will bond to a semiconductor surface, and is present as a mobile species able to rapidly move over the surface. These mobile species will equilibrate to specific sites to minimize the energy of the system. These same localized high surface energy sites are the sites where defects initiate. The presence of the chloride ions at these sites decreases the surface energy at these sites to make them essentially indistinguishable from the surface energy at any other site. The uniform surface energy negates localized non-uniform processes and variations in the surface condition of the wafer. Since this is a surface phenomenon, the amount of a compound providing chloride ions necessary to cause this negation of localized variations may be as low as 5 ppm. Preferably the amount of compound used is between 7 and 2000 ppm. Most preferably between 10 and 1000 ppm.
Addition of chloride ions to an aqueous solution composition used for CMP is particularly useful for semiconductor wafers comprising a metal, and is particularly effective when the metal is copper. Compositions useful in polishing copper typically comprise a complexing agent providing copper ions in solution in the composition, such as citric acid; an inhibitor of initial corrosion, such as benzotriazole; and an organic polymer, such as polyvinyl pyrrolidone. Further, the composition includes an abrasive in the form of colloidal silica particles in fluid suspension, to be used with a polishing pad that is without abrasives. Alternatively, the abrasive is absent from the composition, such that the composition is abrasive free to be used with a polishing pad that itself has abrasives.
EXAMPLE
Compositions A and B were made comprising colloidal silica, citric acid, BTA (benzotriazole), and PVP (polyvinyl pyrrolidone). Further, composition B was made to include 5 to 10000 ppm, parts per million of ammonium chloride and 0.01% of ammonium perchlorate, all being in weight per cent. Patterned wafers comprising copper interconnects were polished on an IPEC Westech 372 polisher under standard conditions using compositions A and B. Surface roughness was measured using an AFM (Atomic Force Microscope) available from Digital Instruments, Inc. A Digital Instrument Dimension®5000 instrument using TappinMode® was used to determine PN (peak to valley roughness), RMS (root mean square roughness), and Ra (arithmetic average roughness). Table 1 below shows the roughness values obtained when the patterned wafers were polished with composition A and composition B.
Table 1
Figure imgf000004_0001
The table discloses the improvement in roughness when a small amount of chloride ions are added to a polishing composition. Such chloride ions are present in a polishing composition to improve surface roughness of the copper interconnects as a result of first step polishing and/or second step polishing.
By way of example, first step polishing is performed, with a polishing pad and a polishing composition, according to a known CMP process to remove excess copper metal from an underlying barrier layer, while leaving patterned copper in a pattern of trenches below the polished surface of the barrier layer. The patterned copper provides the electrical circuit interconnects in the trenches.
However, first step polishing, especially as performed with rough abrasives, tends to leave the patterned copper with a surface roughness that exceeds allowable limits that are specified by manufacturing standards. Surface roughness can be considered as having high points on the surface of the patterned copper. Some of the high points can be quite sharp. Others are less sharp, but nonetheless, exceed the allowable limits for surface roughness. The surface roughness could have been avoided by providing chloride ions in the polishing composition that accompanies first step polishing. However, excessive surface roughness that results from first step polishing is reduced in roughness by performing second step polishing with a polishing composition containing chloride ions.
Such high points can be considered as being high energy areas, as in a situation wherein the patterned copper is wetted by the polishing composition and carries an electrical charge, resulting in an electrical field concentrating at the high points.
Following the first step polishing operation, second step polishing is performed by a known CMP process to remove the barrier layer from an underlying dielectric layer, and to leave the copper interconnects in the trenches that are recessed below a polished surface of the dielectric layer. According to the invention, chloride ions, provided in a fluid polishing composition, reduces surface roughness of the copper interconnects, such that the surface roughness is within the allowable limits.
Second step polishing by a known CMP process is performed with a fluid polishing composition that, either has an oxidizer that is selective to removal of the material forming the barrier layer and selective to removal of copper, or that is without an oxidizer that is selective to removal of copper while being selective to removal of the barrier layer. Second step polishing is performed to remove the barrier layer by polishing action, and to a lesser extent, to remove high points of copper by the polishing action and provide copper ions that solublize, in solution with the fluid polishing composition.
When no oxidizer of copper is present in the fluid polishing composition that is to be used for polishing, either by first step polishing or by second step polishing, copper ions tend to migrate to the high energy areas that are present, and replate from solution to form unwanted nodules and/or dendrites. According to the invention, chloride ions are provided in the fluid polishing composition. The chloride ions tend to migrate to the high energy areas, and tend to null the electrical field and prevent replating of copper ions, and the formation of nodules and/or dendrites, on the high energy areas. The chloride ions replate evenly over the surface of the interconnects, which reduces the surface roughness to within acceptable limits. During polishing, migration of the chloride ions to the high points, nulls the electrical field concentrated at the high energy areas, which deters the attraction of copper ions for replating from solution onto the high points on the patterned copper. Copper ions replate from solution in a distributed manner on the copper surface, and less preferably accumulate on the high points. Further, polishing with or without an oxidizer in the polishing composition, polishes the high points, and removes copper therefrom.
Accordingly, polishing the high points serves to remove the high energy areas, such that copper ions replate from solution in a distributed manner, which contributes to smoothing the surface roughness to be within acceptable limits.
When an oxidizer, for example, a quantity of ammonium perchlorate, is present in the fluid polishing composition that is to be used for second step polishing, the oxidizer tends to oxidize the high points on the surface of the patterned copper. (Further, the oxidizer tends to oxidize spots of residual copper left behind on the underlying barrier layer when first step polishing has stopped prematurely.) Second step polishing removes oxidized copper from the high points, and, as known in the field of CMP polishing, removed oxide ions tend to remain in solution with the fluid polishing composition. The oxidizer contributes to removal of high points on the copper surface, which contributes to smoothing the surface roughness to be within acceptable limits. A balance is struck by the concentration of the oxidizer and the concentration of chloride ions, such that chloride ions are present in a concentration sufficient to be near to each of the high energy areas, and deter the attraction of copper ions for replating from solution onto the high energy areas.
The chloride ions in the polishing composition are mobile species of ions. When the surface of the patterned copper is sufficiently smooth, or has become smooth during a polishing operation, the high energy areas are substantially eliminated, and the chloride ions in the polishing composition are mobile and free of attraction to high energy areas. The mobile chloride ions are readily displaced by agitation away from the polished surface, which allows polishing to operate without interference by the chloride ions. Although the invention has been described relative to second step polishing, the invention advantageously provides a process for a single step polishing operation with a polishing composition that is selective to removal of both copper and an underlying barrier layer, both of which is removed by polishing in a single step with the polishing composition according to the invention.

Claims

Claims:
1. A method for polishing a semiconductor wafer, comprising the steps of: providing a fluid polishing composition with chloride ions, polishing a barrier layer on the semiconductor wafer with the fluid polishing composition to remove the barrier layer and to polish high points on copper interconnects and solublize copper ions in the polishing composition, and replating the copper ions from solution with the fluid polishing composition to smooth the surface of the copper interconnects, while the chloride ions migrate near the high points to deter replating of copper ions onto the high points.
2. A method for polishing a semiconductor wafer, as recited in claim 1, wherein the step of providing the polishing composition with chloride ions, further comprises the step of, providing the polishing composition with solublized ammonium chloride as a source of chloride ions.
3. A method for polishing a semiconductor wafer, as recited in claim 1, and further comprising the steps of: providing the fluid polishing composition with an oxidizer that is selective to removal of copper, and polishing the high points on the copper interconnects with the fluid polishing composition to remove the high points, while the while the chloride ions migrate near the high points to deter replating of copper ions onto the high points.
4. A method for polishing a semiconductor wafer, as recited in claim 3, wherein the step of providing the fluid polishing composition with an oxidizer, further comprising the step of: providing the fluid polishing composition with an ammonium perchlorate as the oxidizer.
5. A method for polishing a semiconductor wafer, as recited in claim 4, wherein the step of providing the polishing composition with chloride ions, further comprises the step of, providing the polishing composition with solublized ammonium chloride as a source of chloride ions.
6. A polishing composition for polishing a semiconductor wafer, the composition comprising: a solution of a complexing agent for producing copper ions in solution in the polishing composition, and an inhibitor of corrosion, and a polymer and a source of chloride ions that migrate to high points on copper interconnects that are below a polished surface of the semiconductor wafer to deter replating of copper ions onto the high points.
7. A polishing composition as recited in claim 6 wherein, the source of chloride ions is ammonium chloride.
8. A polishing composition as recited in claim 6, and further comprising: an oxidizer that is selective to removal of copper while the chloride ions migrate to the high points on the copper interconnects to deter replating of copper ions onto the high points.
9. A polishing composition as recited in claim 8, wherein the oxidizer is ammonium perchlorate.
10. A polishing composition as recited in claim 9 wherein, the source of chloride ions is ammonium chloride.
PCT/US2001/007734 2001-03-12 2001-03-12 Method and composition for polishing by cmp WO2002073681A1 (en)

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PCT/US2001/007734 WO2002073681A1 (en) 2001-03-12 2001-03-12 Method and composition for polishing by cmp
KR1020037011765A KR100762424B1 (en) 2001-03-12 2001-03-12 Method and composition for polishing by CMP
EP01916557A EP1380048A1 (en) 2001-03-12 2001-03-12 Method and composition for polishing by cmp
JP2002572628A JP2004523123A (en) 2001-03-12 2001-03-12 Methods and compositions for CMP polishing

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Publication number Priority date Publication date Assignee Title
US8728934B2 (en) 2011-06-24 2014-05-20 Tessera, Inc. Systems and methods for producing flat surfaces in interconnect structures
US9123703B2 (en) 2011-06-24 2015-09-01 Tessera, Inc. Systems and methods for producing flat surfaces in interconnect structures
US9318385B2 (en) 2011-06-24 2016-04-19 Tessera, Inc. Systems and methods for producing flat surfaces in interconnect structures
US9558998B2 (en) 2011-06-24 2017-01-31 Tessera, Inc. Systems and methods for producing flat surfaces in interconnect structures
US9812360B2 (en) 2011-06-24 2017-11-07 Tessera, Inc. Systems and methods for producing flat surfaces in interconnect structures
US10199275B2 (en) 2011-06-24 2019-02-05 Tessera, Inc. Systems and methods for producing flat surfaces in interconnect structures
US10804151B2 (en) 2011-06-24 2020-10-13 Tessera, Inc. Systems and methods for producing flat surfaces in interconnect structures

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