WO2002069644A2 - Method of video transmission over a synchronous network - Google Patents
Method of video transmission over a synchronous network Download PDFInfo
- Publication number
- WO2002069644A2 WO2002069644A2 PCT/IL2002/000113 IL0200113W WO02069644A2 WO 2002069644 A2 WO2002069644 A2 WO 2002069644A2 IL 0200113 W IL0200113 W IL 0200113W WO 02069644 A2 WO02069644 A2 WO 02069644A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- video
- frames
- clock
- mapping
- frame
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
- H04N21/23602—Multiplexing isochronously with the video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
- H04N21/2381—Adapting the multiplex stream to a specific network, e.g. an Internet Protocol [IP] network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
- H04N21/4342—Demultiplexing isochronously with video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/80—Generation or processing of content or additional data by content creator independently of the distribution process; Content per se
- H04N21/83—Generation or processing of protective or descriptive data associated with content; Content structuring
- H04N21/845—Structuring of content, e.g. decomposing content into time segments
- H04N21/8458—Structuring of content, e.g. decomposing content into time segments involving uncompressed content
Definitions
- the invention is in the field of transmission of video signals over a synchronous transmission technology network, and equipment therefor.
- JP 6098196-A proposes a simple method of reproducing, at a receiving side, the same television frame frequency as at a transmitting side, by extraction a transmission path clock (for example, clock of an SDH network).
- the SDH clock is used for producing a so-called black-burst signal to synchronize the originally analog video signal. More particularly, the source of analog video signal is synchronized and then the signal is converted into a digital form to be coded and transmitted via the SDH network.
- the SDH clock serves just a synchronizing signal used for transmitting a video signal in a closed system.
- a video monitor is synchronized with the same black burst signal restored from the SDH clock.
- SDI video signals are delivered as a bit serial stream at various bit rates including inter alia 270 Mbps SDI signals, 360 Mbps SDI signals and 1.5 Gbps SDI signals.
- One of the main problems is preserving stability of a video signal incoming a transport network up to the moment it leaves the transport network to be processed at a receiving side.
- SDH and SONET are adapted to synchronize incoming signals having clock different from the internal SDH/SONET clock by inserting stuffing bytes into a standard SDH/SONET frame. Quantity of such stuffing bytes changes from frame to frame, and in the case of transmitting video leads to appearance of a "wander effect" in the outgoing signal. To remove this effect, quite complex equipment is required, which might introduce its own distortions into the signal.
- Object of the invention it is therefore an object of the invention to propose a method and a system for synchronizing an uncompressed digital video signal to be transmitted via a transport network such as SONET or SDH, which would resolve the problems outlined above.
- a method of synchronizing a digital video signal for transmitting it in the uncompressed form via a synchronous hierarchy network having its internal clock, by standard frames of said network comprising steps of: obtaining the video signal as a Serial Digital Interface (SDI) signal having its initial video clock and representing succession of video frames, storing said video signal, using the video clock, in a buffer memory having capacity of one or more complete video frames, reading said video signal from the buffer memory, preferably by bytes, using a so-called transport clock derived from the internal clock of said network.
- SDI Serial Digital Interface
- the buffer memory has capacity of a single complete video frame.
- the previous video frame will be read from the buffer memory for the second time without creating problems at a receiving end.
- the reason may reside in deviation of at least one of the clocks from its standard (the video and/or the SONET/SDH clock). Without the complete frame buffer memory such a situation would cause noticeable distortions in the received video picture.
- the reading from the buffer memory may be accomplished in various ways (by bits, by bytes, by two bytes, in a number of steps using additional buffers, etc.). However, since the digitized video signal should be finally mapped by bytes into the standard frames of the synchronous network, the reading is preferably performed by bytes.
- the transport clock is selected based on the bit rate of a data stream of said network, suitable for transmitting the digitized video signal of a particular bit rate. For example, for transmitting one SDI channel of 270 Mbps via an SDH network, two STM- 1 components of the STM-4 data stream are required. It stems from the fact that a digital video signal transmitted as an 270 mbps SDI signal cannot be mapped into one basic SDH data stream STM-1 having the bit rate 155.52 Mbps, so theoretically, two STM-1 data streams would be necessary to carry this SDI signal.
- the second level hierarchical data stream is STM-4 comprising four STM-1 signals and having the bit rate of 622.08 Mbps which will be considered the SDH internal clock for this case.
- STM-4 comprising four STM-1 signals and having the bit rate of 622.08 Mbps which will be considered the SDH internal clock for this case.
- transport clock selection will be presented in the detailed description.
- the synchronizing of the digitized video signal according to the proposed method causes appearance of a periodically repeating mapping/stuffing pattern of the digitized video signal in the standard frames.
- the repeating mapping pattern should appear automatically, though it may have quite a long and hardly determinable period.
- a periodic pattern would be unknown and therefore not used.
- additional synchronizing bytes are usually inserted to indicate the beginning and the end of the informational bytes in the
- the Inventors further proposed to fulfil the above-described method with a step of mapping the digitized video signal into said standard frames using a pre-selected periodically repeating pattern known at both the transmitting and the receiving side.
- it can be implemented by indicating a mapping pattern data used in each specific standard frame by means of a predetermined byte of said standard frame.
- Such a predetermined byte can be called a video header byte.
- the video header byte may comprise data on the exact area in the payload occupied by the video bytes, for example by indicating the video standard used, a type of mapping of this specific frame, the current number of the video frame and the like.
- pre-selected periodically repeating pattern should be understood as a pre-selected order of inserting a particular integer number B of video bytes into payloads of an integer number S of the synchronous hierarchy standard frames, where B video bytes represent information comprised in an integer number V of video frames.
- the pre-selected periodically repeating pattern is performed for mapping an integer number V of video frames into an integer number S of said network frames, provided by integer number B of bytes.
- the number and location of video bytes and stuffing bytes in each particular frame among said S frames can be selected arbitrary, though it repeats itself each cycle comprising N of the standard frames, being equal to k*S frames, where k is either a positive integer number or a value inverse to a positive integer number.
- the method may include arbitrary selecting a mapping pattern type for each particular frame among the S frames, the mapping pattern type being a number and location of video bytes and stuffing bytes in said particular frame, and repeating the arbitrary selected mapping pattern types each cycle comprising N of the standard frames.
- the pre-selected periodical mapping pattern is formed in N said standard successive frames by a limited number of the mapping pattern types, each frame from said N standard successive frames being assigned to a particular mapping pattern type.
- the above-described method is advantageous for synchronizing a multi-channel video transmission.
- the method will then comprise steps of : obtaining at least one additional video signal in the digital form, each having its video clock, storing each of said additional video signals, using its corresponding video clock, in a buffer memory having a capacity of one or more complete video frames and associated with this particular additional video signal; reading each of said additional video signals from its associated buffer memory, using said transport clock derived from the internal clock of said network, thereby synchronizing different video signals initially having their corresponding video clocks by one and the same transport clock.
- the above method also comprises the mapping of each of said additional video signals using its corresponding predetermined periodic mapping pattern.
- the video signals may therefore be obtained according to different standards (PAL, NTSC, etc) and transmitted with different bit rates .
- PAL PAL, NTSC, etc
- the synchronizing is provided at each video channel of a multi-channel system. All video signals, upon passing their corresponding synchronizer acquire equal bit rates and can then be multiplexed say, for transmitting in a higher order data stream (such as
- SDI Serial Digital Interface
- the synchronous transmission technology should be presently understood as the SONET or SDH synchronous hierarchy.
- the buffer memory has the capacity of a single video frame, in this case dropping or adding of one complete video frame would be minimally perceivable for the human eye.
- the read address generator is preferably designed for reading the video information by bytes from the buffer memory.
- said read address generator further serves as a mapper for mapping the video information into said standard frames of the network by using a pre-selected periodic mapping pattern information preliminarily introduced in said read address generator. It goes without saying, that the same pre-selected pattern should be known at a receiving side for de-mapping.
- the read address generator serving as the mapper can be designed for indicating a mapping pattern data used in each specific standard frame by means of a predetermined byte of said standard frame.
- the read address generator comprises a counter of frames of said SDI video signal, a counter of the synchronous technology frames and bytes therein, a control unit capable of processing data obtained from said two frame counters and data on the pre-selected periodic mapping pattern to issue read request signals, said generator further comprises a read address counter synchronized by the transport clock and capable of processing said read request signals for producing a read address to be used for the reading from the buffer memory according to said pre-selected periodic mapping pattern.
- the system comprises a plurality of buffer memories, each associated with its write address generator and its read address generator, and each being adapted for buffering a particular SDI video signal belonging to a corresponding video channel.
- said system with the plurality of the buffer memories is adapted for a respective plurality of SDI video signals having their particular bit rates, the system being capable of synchronizing and mapping said video signals into respective SDH/SONET data streams, and is further provided with a multiplexer for multiplexing the plurality of said data streams into one or more higher order SDH/SONET data streams.
- Fig. 1 is a block-diagram schematically illustrating the inventive method and system of the present invention.
- Fig. 2 is a block diagram of one embodiment of the read address generator shown in Fig. 1.
- Fig. 3a illustrates a standard STM-4 frame of the SDH synchronous hierarchy technology (prior art).
- Fig. 3b schematically illustrates an example of a pre-selected periodic mapping pattern which is proposed for transmitting a digitized 270 Mbps PAL video signal via SDH, according to the invention.
- Fig. 3c schematically illustrates an example of a pre-selected periodic mapping pattern which can be used for transmitting via SDH a digitized 270 Mbps NTSC video signal according to the invention.
- Fig. 1 schematically illustrates a system 10 implementing the method of video synchronization and transmission according to the invention.
- the system 10 actually presents a transmitting portion of a complete combined system which includes, at a receiving end thereof, a structure (not shown in this figure) analogous but inverse to system 10.
- at least one SDI video signal (marked 12) is applied to a Buffer Memory 14 to be stored therein according to a signal produced by a Write Address Generator (WAG) 16 which works in synchronism with the clock of the SDI video signal 12 (so-called initial video clock 13).
- WAG Write Address Generator
- the WAG 16 produces a continuous succession of addresses 15 for recording the digitized video signal, from the beginning of a video frame, into the block 14.
- the Buffer Memory presents an asynchronous dual port memory and preferably has a capacity of one video digitized frame.
- the video frames are read from the Buffer Memory according to another clock (so-called transport clock schematically marked 20) derived from the internal clock 19 of the synchronous transmission technology network (in this figure, SDH), which is applied to A Read Address Generator 18.
- transport clock schematically marked 20
- SDH synchronous transmission technology network
- the SDI video signal has the bit rate of 270 Mbps and thus can be mapped into two STM-1 components of an SDH data stream STM-4.
- Tc can be used, which is obtained by dividing the internal SDH clock by a divisor being a multiple of 8.
- the transport clock for other standard rates of the SDI video signals can be selected in an analogous manner.
- the Read Address Generator 18 has a function of a mapper, since it receives information 21 on a video frame start and produces not only the transport clock 20, but also:
- - read address signal 24 which calculates the address for reading data from the buffer memory according to a particular result of the previous read request (e.g., if there was no read request in a previous moment of time stated by the transport clock, the read address remains the same as at the previous moment, and if there was such a request - the read address should be increased by one).
- the video signal 26 which is finally read from the buffer memory 14, is synchronized with the SDH internal clock 19 and ready for being mapped, in a predetermined manner, into a selected transport data stream of an SDH network 28.
- the mapping pattern per se will be explained with reference to Figs. 3a, 3b, 3c.
- the receiving portion (not shown) of the complete system will perform the inverse transformation of the SDH signal.
- the receiving portion will comprise the elements analogous to those of the transmitting portion (i.e., the WAG, RAG and a buffer memory).
- the WAG of the receiving portion will work with the same clock and rules as the RAG of the transmitting portion, while the RAG of the receiving portion operates using the video clock formed from the transport clock ,and using the rules of the WAG of the transmitting portion.
- Fig. 2 is a schematic block-diagram describing, in more detail, one embodiment 30 of the Read Address Generator units shown Fig. 1.
- the unit 30 performs the following functions using the following blocks: block 32 for generating the transport clock (Tc) 33 based on the SDH internal clock; blocks 34, 36 and 38 responsible for counting columns of an SDH frame
- Final State Machine block 42 which, being synchronized by the transport clock Tc, receives data from the blocks 34, 36, 38 and 40, and instructions on the selected periodic mapping pattern 41 which depends on the video transmitting system (PAL, NTSC, or another) to produce a signal of read request 43.
- PAL video transmitting system
- NTSC NTSC
- This signal refers to those specific places of the SDH frames to which bytes of the video information stored in the buffer memory are to be mapped according to the selected periodic mapping pattern;
- Address counter block 44 synchronized by the transport clock Tc, which produces each new read address 45 for reading data from the buffer memory upon receiving a new read request 43; moreover, upon receiving a signal 39 of a new video frame, block 44 performs reset and starts counting the read addresses from the beginning of the buffer memory;
- the Read Address Generator 30 acts not only as a synchronizer, but also as a mapper, since when a Tc clock signal is not accompanied by the read request, a stuffing byte is mapped into the SDH frame, and when a Tc clock is "enabled" by the read request, a video byte is read from the buffer memory to the SDH frame.
- Fig. 3a schematically illustrates a standard frame of an STM-4c data stream of the SDH transmitting technology.
- STM-4c data stream is composed by byte-interleaving multiplexing of four STM-1 data streams into one synchronous payload envelope.
- a standard STM-1 frame is shown with four-fold numbers of bytes forming various sections of the STM-4c frame. Such a four- fold frame is transmitted each 125 microseconds, like the basic STM-1 frame.
- the standard basic SDH frame STM-1 (or the SONET frame STS-3) repeats itself each 125 microseconds and looks as follows: it has 270 columns and 9 rows of bytes divided into a payload portion and an overhead portion.
- the overhead portion comprises the following areas: section overhead SOH, AU (administrative unit) pointers, and path overhead POH.
- the shadowed area to the right of the POH in the frame is its informational payload, which can be filled with the digitized video information from the buffer memory. Bytes of the payload (the shadowed area) can be occupied by any digital information, including the video information.
- Fig. 3b One 270 Mbps video signal occupies two STM-1 data streams being components of one STM-4 data stream.
- the drawing refers to this case, and the illustrated frames are therefore marked by two-fold numbers of bytes in the columns.
- the Inventors proposed two types (type A and type B) of mapping the STM-1 standard frames.
- the shadowed portions schematically illustrate bytes of the payload, occupied by the digitized video information (so-called main portion of the payload).
- the section VH is a Video Header byte containing information on the video standard, and information on the mapping pattern for a decoder placed at the receiving side.
- the remaining portion of the payload is a stuffing portion.
- the best mode of the method is achieved when loading the binary video information of V complete video frames into payloads of S complete SDH frames by an integer number B of video bytes, whenever at least one of the three numbers is minimal.
- the information may be spread between the stuffing and the main portions of the payload in a pre-selected manner, and this manner may periodically repeat in a succession of frames.
- the obtained number is the average number of video bytes in the payload of one SDH standard frame. It can be seen that this number is not integer.
- Fig. 3b illustrates the mapping pattern for the European PAL video transmission system which is calculated as follows: l.
- the SDH 8-frame structure period may contain: seven SDH frames of the mapping type A, where the video bytes are mapped in the payload as follows: ⁇ [(234*2*8 rows) + (237*2)]*7 ⁇ bytes, and one SDH frame of the mapping type B: [(234*2* ⁇ rows) + (240*2)] bytes,
- the selected mapping pattern can be seen in the shadowed (main) portion of the frames marked "type A” and "Type B” in the drawing.
- the SDH frame has 9 rows. In 8 of them, the payload is mapped by short 234 byte-long sections in each of two STM-ls (remember that four STM-1 can be loaded in one frame of STM-4). In the ninth row of STM-1 there is a long 237 byte-long mapping in 2 STM-ls say, for the first 7 frames, and a long 240-byte mapping in 2 STM-ls for the last I SDH frame.]
- Fig. 3c illustrates one proposed example of the pre-selected periodical mapping of video bytes of one NTSC 270 Mbps signal onto two STM-1 data streams. As can be seen, it is performed using three types of mapped frames : Type A, Type C and Type D. The mapping is calculated as follows:
- the mapping pattern in the SDH frames can be selected as follows: For the first 29 video frames, 266 SDH frames shall use type A of the mapping, and one frame - type C of the mapping, i.e.: [(234*2*8 +237*2)*266 + (246*2*8 +240*2)] *29; For the last 30-th video frame, 234 SDH frames shall use type A of the mapping, and one frame - type D of the mapping, i.e.: (234*2*8 + 237*2)264 + (249*2*9).
- the total number of bytes in the above mapping pattern is equal to 33,783,750 (can be obtained also as 4,218.75 * 8,008 SDH frames).
- This integer number of bytes can be mapped into 8008 SDH frames, thus forming the STNC pre-selected pattern cycle for 30 video frames.
- the numbers 266+1 and 264 +1 of the SDH frames were selected to use integer numbers instead of the non-integer number 266.933(3) reflecting the average number of SDH frames needed for transmitting one NTSC video frame].
- the period of the mapping pattern always comprises an integer number B of video bytes and an integer number S of SDH frames.
- the integer number V of video frames may be equal to the mapping pattern period or be evenly divisible by the period of mapping pattern.
- the integer number V can be also a multiple of the mapping pattern period.
- mapping pattern can be selected in the analogous manner.
- the 360 Mbps SDI video signal occupies three STM-1 components of the STM-4 data stream, so the calculations should be modified accordingly.
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02712215A EP1362483A2 (en) | 2001-02-25 | 2002-02-14 | Method of video transmission over a synchronous network |
US10/468,821 US20040070688A1 (en) | 2001-02-25 | 2002-02-14 | Method of video transmission over a synchronous transmission technology network |
AU2002232091A AU2002232091A1 (en) | 2001-02-25 | 2002-02-14 | Method of video transmission over a synchronous network |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IL14163201A IL141632A (en) | 2001-02-25 | 2001-02-25 | Method of and system for video transmission over asynchronous transmission technology network |
IL141632 | 2001-02-25 |
Publications (2)
Publication Number | Publication Date |
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WO2002069644A2 true WO2002069644A2 (en) | 2002-09-06 |
WO2002069644A3 WO2002069644A3 (en) | 2003-01-03 |
Family
ID=11075170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/IL2002/000113 WO2002069644A2 (en) | 2001-02-25 | 2002-02-14 | Method of video transmission over a synchronous network |
Country Status (5)
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US (1) | US20040070688A1 (en) |
EP (1) | EP1362483A2 (en) |
AU (1) | AU2002232091A1 (en) |
IL (1) | IL141632A (en) |
WO (1) | WO2002069644A2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040148437A1 (en) * | 2002-12-12 | 2004-07-29 | Koji Tanonaka | Synchronous network establishing method and apparatus |
US7653924B1 (en) * | 2003-10-01 | 2010-01-26 | Cisco Technology, Inc. | Digital video streaming over optical network |
US8606949B2 (en) | 2005-04-20 | 2013-12-10 | Jupiter Systems | Interconnection mechanism for multiple data streams |
US8547997B2 (en) * | 2005-04-20 | 2013-10-01 | Jupiter Systems | Capture node for use in an audiovisual signal routing and distribution system |
US20090279572A1 (en) * | 2008-05-07 | 2009-11-12 | Canon Kabushiki Kaisha | Transmission apparatus and method |
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GB2275852A (en) * | 1993-03-05 | 1994-09-07 | Sony Broadcast & Communication | Signal synchroniser with resynchronise control |
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EP0902590A2 (en) * | 1997-09-12 | 1999-03-17 | Eci Telecom Ltd. | Integrated communication system |
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EP1069780A2 (en) * | 1994-06-27 | 2001-01-17 | Sony Corporation | Digital serial data interface |
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JPH06268625A (en) * | 1993-03-12 | 1994-09-22 | Matsushita Electric Ind Co Ltd | Digital signal transmitting method, transmitter receiver, and transmitting device |
US5841771A (en) * | 1995-07-07 | 1998-11-24 | Northern Telecom Limited | Telecommunications switch apparatus and method for time switching |
DE19545675A1 (en) * | 1995-12-07 | 1997-06-12 | Sel Alcatel Ag | Synchronous digital transmission system |
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EP0935362A3 (en) * | 1998-02-06 | 2005-02-02 | Alcatel | Synchronisation device for a synchronous digital transmission system and method for generating a synchronous output signal |
IL131461A0 (en) * | 1999-08-18 | 2001-01-28 | Eci Telecom Ltd | Inter-chip port and method for supporting high rate data streams in sdh and sonet transport networks |
-
2001
- 2001-02-25 IL IL14163201A patent/IL141632A/en not_active IP Right Cessation
-
2002
- 2002-02-14 WO PCT/IL2002/000113 patent/WO2002069644A2/en not_active Application Discontinuation
- 2002-02-14 AU AU2002232091A patent/AU2002232091A1/en not_active Abandoned
- 2002-02-14 EP EP02712215A patent/EP1362483A2/en not_active Withdrawn
- 2002-02-14 US US10/468,821 patent/US20040070688A1/en not_active Abandoned
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GB2275852A (en) * | 1993-03-05 | 1994-09-07 | Sony Broadcast & Communication | Signal synchroniser with resynchronise control |
EP0743790A2 (en) * | 1994-01-21 | 1996-11-20 | Sony Corporation | Image data transmission apparatus |
EP1069780A2 (en) * | 1994-06-27 | 2001-01-17 | Sony Corporation | Digital serial data interface |
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SAWADA K ET AL: "Coding and transmission of HDTV at the STM-1 rate of SDH" PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. SAN DIEGO, MAY 10 - 13, 1992, PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. (ISCAS), NEW YORK, IEEE, US, vol. 4 CONF. 25, 3 May 1992 (1992-05-03), pages 200-203, XP010061067 ISBN: 0-7803-0593-0 * |
Also Published As
Publication number | Publication date |
---|---|
US20040070688A1 (en) | 2004-04-15 |
IL141632A (en) | 2005-12-18 |
WO2002069644A3 (en) | 2003-01-03 |
EP1362483A2 (en) | 2003-11-19 |
IL141632A0 (en) | 2002-03-10 |
AU2002232091A1 (en) | 2002-09-12 |
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