WO2002069182A1 - Fourier transform device - Google Patents

Abstract

A Fourier transform device of which pipeline width does not depend on the number of the transform points of individual pipeline FFT circuits in each stage, and which comprises a front stage and a rear stage, wherein each stage has, as transform means, a (submultiple of M) pieces of M (power of 2) point, base 2 pipeline FFT circuits (1, ....) each having an equal number of transform points for parallel inputting/outputting, and also has a data rearranging means for supplying data to transform means in each stage, whereby rendering the pipeline width of the Fourier transform device independent of the number of transform points of respective pipeline FFT circuits in each stage.

Description

 Specification

 Fourier Transformer Technical Field

 The present invention relates to a Fourier transform device that performs a discrete Fourier transform at high speed,

-Regarding a Fourier transform device that divides the Fourier transform device into two stages, the former stage and the latter stage, and arranges the same number of radix-2 Fourier transform pipelines (radix-2 pipeline FFT) in each stage. It is. Background art

M (2 ^m : hereinafter referred to as 2 * * m) The point radix-2 pipeline FFT is known as an arithmetic pipeline composed of m stages of data rearrangement and arithmetic operations. It is described in the section “Radix 2 Pipeline FFT” on page 604 in AND APPLICATION OF DIGITAL SIGNAL PROCESSING by Lawrence R. Rabiner, Bernard Gold, published by PRENTICE HALLj.

 If the number of transformation points can be decomposed into N = LXM in the Fourier transform, the L point FFT operation is performed M times according to the principle of FFT, and the obtained N data are multiplied by a torsional coefficient, and then the M point FFT By performing the operation L times, the Fourier transform can be performed. In this way, several methods for configuring a pipeline using the decomposition of the N-point Fourier transform have been disclosed.

 One of them is that if the number of conversion points N can be expressed as N = LXL, an L-point parallel type Fourier transform circuit (input and output is equal to the number of conversion points L) is placed in the front and rear stages, and the corner turner is used for data supply. Are arranged before each L-point parallel Fourier transform circuit.

 The same configuration can be adopted when the number of conversion points N is N = LXM (L = PXM, where P is an integer greater than 1), and the parallel width is L in each case.

 The corner turner is a circuit that transposes and outputs two-dimensional data as a matrix (see Japanese Patent Application Laid-Open No. 59-087575).

In the other case, if the number of conversion points N can be expressed as N = (2 * * m) XA, 2 parallel input / output 2 * * m points, A radix-2 pipeline FFT circuits are arranged in parallel, and 2 parallel A point parallel type Fourier transform circuits (pipeline width A points) are arranged in parallel. It is. In this case, the overall parallel width is 2 XA.

 In the above-described Fourier transform apparatus, in the configuration method in which the parallel type Fourier transform circuits are arranged at the front and rear stages, the number of input parallel points or the pipeline width becomes a value equal to or larger than the square root of the number of Fourier transform points N, and is smaller than the square root of the number of transform points N. There is a disadvantage that the pipeline width cannot be obtained (see Japanese Patent Application Laid-Open No. 63-36553).

 Another parallel configuration in which two parallel input / output radix-2 pipelined FFT circuits are arranged in the first stage and two parallel Fourier transform circuits are arranged in the second stage is to convert the number of input parallel points or pipeline width to the number of Fourier transform points. Can be decided without much influence. However, the input parallelism or the number of conversion points of the subsequent parallel Fourier transform circuit is equal to the number A of two parallel input / output radix-2 pipeline FFTs arranged in the preceding stage (that is, half of the pipeline width of the device). Therefore, when the pipeline width of the device is large, there is a disadvantage that the parallel-type Fourier transform circuit at the subsequent stage becomes a pin-neck due to spatial parallelism, which makes implementation difficult. See Japanese Patent Application Publication No.

 The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a free-wheel converter in which the pipeline width of the device does not depend on the number of conversion points of each pipeline FFT circuit in each stage. The purpose is. Disclosure of the invention

In order to solve the above-described problem, the present invention provides a Fourier transform apparatus that performs a discrete Fourier transform, and has two parallel input / outputs in which the maximum number of transform points is M (= 2 ** m, m> = 2). A first-stage conversion means having a number of a radix-2 pipeline FFT circuit corresponding to a divisor of the maximum number M of conversion points, and first data for supplying input data to the first-stage conversion means in a first predetermined order Supply means; two parallel input / output M points of the same number as the previous conversion means; a second conversion means having a radix-2 pipeline FFT circuit; and a second conversion means for inputting the input data to the second conversion means. A second data supply unit that supplies the data in a predetermined order; and a torsion coefficient multiplication unit that is provided between the conversion unit at the preceding stage and the conversion unit at the subsequent stage and that multiplies a torsion coefficient. It is assumed that. FIG. 1 shows an example of this apparatus.

 Further, in the Fourier transform apparatus of the present invention, the first data supply means switches between a first memory circuit having a two-bank configuration and a bank of the first memory circuit, and alternately sequentially inputs data. Writing means for writing every M pieces of data, and reading means for simultaneously reading data at corresponding positions of the two banks of the first memory circuit and supplying the data to the preceding conversion means. is there. Fig. 2 shows an example of this device.

 Further, in the Fourier transform device of the present invention, the first data supply means is configured to include first and second data reordering units for reordering data in a predetermined order in two stages, A second and third memory circuit in which the first and second data rearranging units store data, and a read or write address generation circuit according to a predetermined logic of each of the second and third memory circuits. A corner turner for rearranging the data read from the second and third memory circuits, respectively.The second data supply means includes a third data rearranging unit, and stores the data. A fourth memory circuit, a read or write address generation circuit according to a predetermined logic of the fourth memory circuit, and a corner turner for rearranging data read from the fourth memory circuit. Those characterized by comprising. This device is shown in Fig. 4 and Fig. 5 as an example.

Further, in the Fourier transform apparatus of the present invention, when the number a of the pipeline FFT circuits included in the transform units of the preceding and succeeding stages is 2, the first data supply unit includes a fourth and a fifth data rearranging unit. And a fifth memory circuit in which each data rearrangement unit stores data, and a read or read operation according to a predetermined logic of each of the fifth and sixth memory circuits. A write address generation circuit; and a corner turner for rearranging the data read from the fifth memory circuit.The second data supply means includes a sixth data rearrangement unit, and converts the data. A seventh memory circuit for storing, and a read or write address generation circuit according to a predetermined logic of the seventh memory circuit are provided. This apparatus corresponds to, for example, one in which the corner turners 324 are omitted in FIGS. 4 and 5. Further, in the Fourier transform apparatus of the present invention, when the number a of the pipeline FFT circuits included in the first and second conversion units is 1, the first data supply unit includes a seventh and an eighth data rearrangement unit. The seventh data rearrangement unit is configured to include: an eighth memory circuit that stores data; a read or write address generation circuit that follows a predetermined logic of the eighth memory circuit; And a parallel-in-serial-art circuit for rearranging the data read from the memory circuit.The eighth data rearrangement unit described above alternately writes and reads M data units at the time of storage. A ninth memory circuit, each of which is composed of two banks so that corresponding data of the corresponding M-point data set can be simultaneously read, and reading according to a predetermined logic of the ninth memory circuit. An output or write address generation circuit, wherein the second data supply means alternately writes M data at the time of storage, and simultaneously reads the corresponding data of the corresponding M point data set at the time of reading. Further, the present invention is characterized in that it comprises a 10th memory circuit each composed of two banks, and a read or write address generation circuit according to a predetermined logic of the 10th memory circuit. An example of this device is shown in FIGS. 8 and 9, for example.

 In addition, the present invention arranges the above-mentioned Fourier transform devices in parallel to a power of 2 and assigns the time-series input data to each Fourier transform device by the maximum number of Fourier transform points N (two MXM), and continuously assigns them. It is characterized in that it comprises a data distribution and rearrangement means for supplying each Fourier transform device with a set of M points and one set of two sets each in two parallels, a total of 2a in parallel. The present device is described in the section (parallel arrangement) in the best mode for carrying out the invention.

 Further, in the Fourier transform device of the present invention, the data distribution / rearrangement means follows a first memory circuit for storing data for the Fourier transform devices arranged in parallel, and a predetermined logic of the first memory circuit. A read or write address generation circuit; and a corner turner that rearranges data read from the first memory circuit and outputs data in parallel to each of the Fourier transform devices arranged in parallel. It is assumed that. An example of this device is shown in FIG.

Further, the Fourier transform apparatus of the present invention further comprises: And a bypass means for bypassing the bypass. This apparatus has been described in the bypass process in the best mode for carrying out the invention. The processing can be easily speeded up by using a double buffer memory for each memory circuit.

 As described above, in the present invention, the apparatus is divided into two stages, a front stage and a rear stage, and each stage is provided with the same number of M points of two parallel input / outputs and a radix-2 pipeline FFT circuit (with a pipeline width of 2). Place and perform Fourier transform of MXM points. The overall pipeline width is adjusted by the number a of pipeline FFT circuits arranged in parallel. However, if M = 2 * * m and the number a is a divisor of M, the Fourier transform of M points handled by each pipeline FFT circuit becomes (M ÷ a) pairs, and the control of data distribution etc. Becomes easier.

 Each 2-parallel I / O radix-2 pipeline FFT circuit has a pipeline width of at most 2, and there is little signal complication in it, and it does not become a pin-neck in mounting. However, a data rearranging means for supplying data is required for each stage. The same device can be used because the number of Fourier transform points can be halved by bypassing only the operation of the pipeline stage of the radix-2 pipeline FFT circuit from the top at M points of the two parallel input / outputs in the preceding stage. MXM, (M / 2) XM, · · · · · 2 XM points can be converted as a whole by changing the mode setting in the configuration. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a block diagram showing a Fourier transform device of the present invention.

 FIG. 2 is a block diagram of a first example of a data rearrangement section in the preceding stage.

 FIG. 3 is a block diagram showing an example of a first read address generation circuit.

 FIG. 4 is a block diagram showing a data rearrangement unit at the preceding stage when a is 2 or more.

 FIG. 5 is a block diagram showing a data rearrangement unit at the subsequent stage when a is 2 or more.

FIG. 6 is a block diagram showing a second read address generation circuit. FIG. 7 is a block diagram showing a third read address generation circuit.

 FIG. 8 is a block diagram showing a data rearranging unit at the preceding stage when a is 1. FIG. 9 is a block diagram showing a data rearrangement unit at the subsequent stage when a is 1. FIG. 10 is a block diagram showing a fourth read address generation circuit when a is 1.

 FIG. 11 is a block diagram showing a fifth read address generation circuit when a is 1.

 FIG. 12 is a block diagram showing a configuration of a data distribution / reordering unit.

 FIG. 13 is a block diagram showing a sixth read address generation circuit when a is 2 or more.

 FIG. 14 is a block diagram showing a sixth read address generation circuit when a is 1.

 FIG. 15 is a block diagram showing a 64 point FFT.

 FIG. 16 is a block diagram showing a data rearranging section at a stage preceding the 64 point FFT. FIG. 17 is a block diagram showing a data rearrangement section at the subsequent stage of the 64 point FFT.

BEST MODE FOR CARRYING OUT THE INVENTION

 FIG. 1 is a block diagram showing a basic configuration diagram of an embodiment of the present invention. The FFT 100 shown in Fig. 1 is composed of a pre-stage A and a post-stage B. As the pre-stage and post-stage conversion circuits, a number of 2 parallel input / output M points, radix-2 pipeline FFT circuits 1 and 2, each pipeline It is provided immediately after the first-stage and second-stage data rearrangement units 3 and 4 and the second-stage data rearrangement unit 4 as first and second data supply means for supplying data to the circuits 1 and 2, respectively. It comprises a 2a complex multiplying circuit 5 and a torsion coefficient multiplying section 7 having a coefficient memory 6 for storing torsion coefficients. The torsion coefficient multiplying unit 7 may be provided immediately before the rear-stage data rearranging unit 4 by changing the order of supplying the torsion coefficient.

 (Method of rearranging data 1)

Fig. 2 shows the first example of the pre-stage data reordering unit as the pre-stage data supply means. FIG. 2 is a block diagram showing a method 1) .In the data rearrangement unit 3A of FIG. 2, the buffer memory 301 has a double buffering configuration for simultaneous write and read access, and also has a read It has a two-bank configuration having banks 301A and 301B so that data groups belonging to two different sets can be read simultaneously. Hereinafter, in this specification, the term “buffer memory” or “memory” means double buffer memory. The input address is written by the write address circuit 302 by sequentially switching the banks alternately every M units. In reading, by reading the data at the corresponding positions of the two banks at the same time by the first read address generation circuit 303, it is possible to obtain every two M data, that is, two parallel data. it can.

 (Method 2 for rearranging data)

 FIGS. 4 and 8 are block diagrams showing a second example (method 2) of the data rearrangement unit as the data supply means at the preceding stage. FIG. 4 shows a case where a is 2 or more, and FIG. 1 shows a preferred example in the case of 1. The data rearranging section 3B shown in each of FIGS. 4 and 8 has a two-stage configuration of the first half and the second half, and the first data rearranging circuits 310 and 330 in the first half first generate time-series parallel data. From M data units to 2 parallel input / output M points each, corresponding to the radix-2 pipeline FFT circuit, that is, to a column platoon (in each M unit, it becomes 2 columns platoon) The second data rearrangement circuits 320 and 340 in the second half fetch data one by one from blocks arranged in column a in units of M generated in the first half. In this case, the data is rearranged so that M data sets, which are every M data when viewed as time series data, are obtained.

 (Method 2 for rearranging data: when a≥2)

First, when a≥2, that is, as shown in FIG. 4, when the number of pipeline FFTs in each stage is two or more, the first data rearrangement circuit 310 constituting the first half is composed of a memory and a corner turner. The memory has a buffer memory 311 which is storage means having an input / output width of the number of data points corresponding to the input data width, a write address generation circuit 312, and a second read address generation circuit, The corner turner 314 is composed of two sets 314a and 314b corresponding to odd-numbered and even-numbered input data. The second data rearrangement circuit 320 constituting the second half of the data rearrangement section of the first stage is composed of a memory and a corner turner, like the first data rearrangement circuit 310 of the first half, and the memory is the pipeline width of the conversion section. A buffer memory 321, a write address generation circuit 322, and a third lead address generation circuit 323, which are storage means having an input / output width of the number of data points corresponding to The output line of the data group of every third line output from the first line of the list, the data of every third line output from the third line, and the data of every third line output from the second line The group consists of four sets of 3 2 4a to 3 2 4d that input and rearrange the data groups of every third line output from the fourth line.

 In particular, when a = 2, the input to the corner turner is only one data, so no operation is required, the circuit for the corner turner is not necessary, and the data is simply routed from the memory.

 (Pre-stage data sorting method 2: a = l)

 When a = l, that is, when the number of pipeline FFTs in each stage is one, as shown in Fig. 8, the first data rearrangement circuit 330 in the first half of the data rearrangement unit 3C in the previous stage is The memory comprises a buffer memory 331 as a storage means having an input / output width of the number of data points corresponding to the input data width, a write address generation circuit 332, and a fourth read address generation circuit 3. The corner turner is composed of two sets of parallel-in / parallel ports 334a and 334b corresponding to odd-numbered and even-numbered input data.

 The second data rearrangement circuit 340 in the second half is composed of two banks of buffer memories, 3A and 3141B, so that two different data groups can be read at the same time. It has a circuit 342 and a fifth read address generation circuit 343, which is a simpler case where b = l and a = l in FIG.

 (Method of rearranging data)

The data reordering unit 4 in the latter stage shown in FIG. 1 is configured as shown in FIG. 5 when a≥2, and is configured as shown in FIG. 9 when a == l. In other words, the data reordering units 4A and 4B at the subsequent stage shown in FIGS. 5 and 9 correspond to the ones shown in FIGS. 4 and 8. _It has the same configuration as that of the _2- de-evening reordering circuit (the latter half), and omits the explanation here. However, it rearranges the FFT output of the preceding stage so that every Mth Try to get a pair.

 (Operation explanation)

 Next, the operation of the embodiment will be described.

 First, the number of conversion points of the a individual 2-parallel input / output, radix-2 pipeline FFT circuit 1 that constitutes the conversion means of the preceding stage is the maximum, that is, the conversion number of the a individual pipeline FFT circuits of the subsequent stage is Finally, we explain the case where the number of conversion points in the previous stage is less than M, that is, 2 ** p, (p = l to ml).

 In N-point discrete Fourier transform

 X (n) = ∑x (k) W * * (nXk) (0)

 Where W = e xp (-2 π j / N)

 n, k = 0 to N— 1

 If the number of conversion points can be decomposed into N = MXM (where M = 2 * * m), then n = MX n 1 + n 0

 k = MXk 1 + k 0

 Where n 1, n 0 = 0 to M_ 1

 k 1, k 0 = 0 to M_ 1

 Then, the equation (0) of the discrete Fourier transform becomes

 M-1 M-1

 X (nl, ηθ) = ∑∑x (kl, kO) XWM * * (nOxkl)

 kO = 0, kl = 0

 XW * * (nOxkO) XWM * * (nlxkO)

 Where WM = e xp (-2 π j / M)

 It can be broken down into the following steps:

 XI (n0, kO) = ∑x (kl, kO) XWM * * (nOxkl)-(1) kl = 0 to M-1

X2 (n0, kO) = X1 (n0, kO) XW * * (nOxkO) (2) X3 (n0, nl) = ∑X2 (n0, kO) XWM ** (nlxkO) (3) kO = 0 ~ M_l In equation (1), if kO is fixed, this is the DFT of M points. Which can be processed by a radix-2 pipelined FFT circuit with M points. Since kO = 0 to M_l, it indicates that M sets of separate DFTs are performed. These can be processed continuously without interruption if a is a divisor of M, using a radix-2 pipeline FFT circuit with a number of M points.

 Equation (2) multiplies each obtained by equation (1) by a torsion coefficient, and can be processed by a torsion coefficient multiplication circuit group. In equation (3), if ηθ is fixed, this is the DFT equation at M points, which can be processed by the radix-2 pipeline FFT circuit at M points. Since nO = 0 to M-1, it indicates that M sets of separate DFTs are performed. Equation (1) Similarly, if a is a divisor of M using a radix-2 pipeline FFT circuit of a M points, processing can be performed continuously without interruption.

 In particular, since equation (1) is k = MX k 1 + k 0, kO is fixed to a certain value, and if kl moves from 0 to M−1, M It indicates that it is necessary to take the data every other time and supply it to the pipeline, and the data rearrangement circuit in the previous stage is the part that performs this operation.

 In equation (3), the index of X2 is MXn 0 + k0, so if ηθ is fixed at a certain value and k0 moves from 0 to M−1, the index must be a continuous value. Since the output of the previous stage has M jumps with respect to the index, it is necessary to rearrange the obtained output so that it is continuous with respect to the index, and supply it to the pi-brain. In other words, it is necessary to supply every Mth output from the output sequence in the previous stage. The data rearranging unit at the subsequent stage is a unit for performing this operation.

Hereinafter, a rearrangement process performed by the data rearrangement unit in the preceding / subsequent stages will be described. If the time series data {x (t): t = 0 to 2 * * m—1} is generally input in parallel by 2b units, the continuous data of each input data line is grouped into B units. If these are summarized across each input data line, they can be divided into M groups each consisting of M point data as shown in Table 1 below. (table 1)

 Group 1 Group 2 Group a + 1 Group M

Input data "-data line 1;

 {x (2bj)} {x (M + 2bj)} {x (aM + 2bj)} {x ((M-fine bj)} j = 0-Bl j = 0-Bl j = 0-Bl j = 0 ~ B- 1

Input data line 2;

 ix (2bj + l)} {x (MI2bj + l)}, {x (aM + 2bj + l)} {x ((Ml) M + 2bj + l)} j = 0-Bl j = 0-B— lj = 0 to B—lj = 0 to Bl

Input data, -taline 3;

 ix (2bj + 2)} {x (M + 2bj + 2)}, {x (a + 2bj + 2)}, {x ((Ml) + 2bj + 2)} j = 0 to B— 1 j = 0 ~ B-1] · = 0 ~ Β-1 j = 0 ~ B-1 Input data "-data line 2b;

 {x (2bj + 2b-l)}, {x (MI2bj + 2b-l)}, {x (aM + 2bj + 2b-l)}, {x ((Ml) M + 2bj + 2b-l)} j = 0-Bl j = 0-B-1 j = 0-Bl j = 0-Bl Here, the first input data line,..., the second b data input line are shown in order from the top. However, when B = MZ2 b and the degree of parallelism is 2b, the number of input counts until the data becomes M point data, 2b = the degree of parallelism of input, and therefore M must be divisible, so b is a power of 2 , A = the number of pipeline FFT circuits in each of the preceding and succeeding stages, which is a divisor of M and is also a power of two.

 In particular, for the pre-stage data reordering unit, we show a method that performs it in one stage (method 1) and a method that performs it in two stages (method 2). The latter half of the method performed in two stages has the same configuration as the rearrangement in the latter stage.

 (Reordering method 1 in the first stage)

In the reordering method 1 in the previous stage, each of the above groups is a data set consisting of time-series continuous M-point data, so if data at the corresponding positions of these M groups are collected one by one, A data set consisting of M data sets can be obtained. But, Since each pipeline FFT circuit has two parallel inputs, it is necessary to read out simultaneously from two data groups. The memory is divided into banks so that simultaneous access is possible, and the odd-numbered groups and the even-numbered groups are stored in separate bank memories.

 A is read from each bank in order from the head of each group, and two data at the corresponding positions on the two banks are two parallel inputs of one pipeline FFT. Normally 2 b> = 2 a, so if 2 b ÷ a = c (where c is a power of 2) Of the 2 b column data of each group, a is required simultaneously for each a, so the rest is Discarded, so each column of each group will be read c times (if 2 b <2 a, the input data can be demultiplexed and treated the same as 2 b = 2 a ). In the method 1 shown in FIG. 2, the data rearrangement unit 3A in the preceding stage converts the data input in parallel by 2b data into one of the banks 301A and 301B of the double buffer memory, Each time the number of banks becomes M, two banks are alternately stored while alternately switching, and two banks are simultaneously read from two banks of the other memory, and the necessary a out of the two b is transmitted. It is.

 FIG. 3 is a block diagram showing a configuration example of the first read address generation circuit 303. Note that, depending on the memory element configuration, a configuration in which useless reading is avoided can be adopted.

 The group number counter 3 0 3 1 (M72 counter) and column number counter 3 0 3 2 (B counter) in the figure are means for specifying each of the groups and columns in the group in the above description of reordering, and the row group number. The counter 303 (C counter) is a means of selecting adjacent a data in column data (consisting of 2 b data).

 The read address of the column data has a configuration in which the bits of the group number counter 3 031 and the column number counter 3 0 32 are simply connected in this order. The value of the row group number counter 3 0 3 3 is a selection signal for the target data a in the column. The carrier of the group number counter 3 0 3 1 updates the row group number counter 3 0 3 3, and the update of the row group number counter 3 0 3 3 updates the column number counter 3 0 3 2 By connecting, a series of data at the corresponding position of each group (that is, the column to which the position in each group is relatively the same and the position in the column is the same) are successive in time series. Is read.

(Reordering method 2 at the previous stage: When a≥2) The method 1 shown in FIG. 2 performs the reordering in one stage, whereas the method 2 shown in FIGS. 4 and 8 performs the reordering in two stages.

 First, the case where a≥2, that is, the case where the number a of the pipeline FFT circuits is 2 or more, will be shown, and then the case where a = l.

 As described above, the first data rearrangement circuit 310 rearranges the data set M consisting of M points in the time series, which are continuous from each other, so as to be in column a. In particular, each dataset is rearranged so that it is in two columns. The following is the procedure.

 The M groups are divided into A clusters of A groups, and processed as follows. Here, A = M / a, and is the number of M-point data sets processed by one FFT circuit.

 For each group in the first cluster, a column consisting of b data of the even index (odd number) of the first column and a column consisting of b data of the odd index (even number) are created. E, Even-number data is transposed as bX a matrix. Create a column consisting of b odd-numbered data and b columns of even-numbered data in the second column of each group of the first cluster, and transpose odd-numbered data and even-numbered data as a bx a matrix, respectively. Position next to the transpose from the first row. In the same manner, a column consisting of b odd-numbered data and a column consisting of b data of even-numbered data in the B-th column of each group of the first class are created in the same manner, and odd-numbered data and even-numbered data are formed. Transpose each as a bX a matrix, and place it next to the transpose from column B-1. Odd-numbered data — matrix of size a Xb obtained from evening a X (b * B) [= a X (M / 2)] consisting of B matrices Each row of the matrix is an odd-numbered line, and the even-numbered The following first group force is obtained with each row of the size aX (M / 2) matrix obtained from the data as even-numbered lines. In the same manner, when the procedure is performed for each group in the second class, the following second group is obtained. In the same manner, finally, the second group in the second class is obtained from the second class evening.

 (Table 2)

 Group 1 Group 2 Group 3 Group A

 {x (2i)}, {x (aM + 2i)}, {x (2aM + 2i)}, {x (a (Al) M + 2i)} i = 0-M / 2-li = 0-M / 2- 1 i = 0 ~ M / 2- 1 i = 0 ~ M / 2-l

ix (2i + l)}, {x (aM + 2i + l)}, {x (2aM + 2i + l)}, {x (a (Al) MI2i + l)} i = 0-M / 2- 1 i = 0-M / 2-1 i = 0-M / 2-1 i = 0-M / 2- 1

{x (M + 2i)}, {x ((a + l) M + 2i)}, {x ((2a + l) M + 2i)}, {x ([a (A-ll] M + 2i )} i = 0-M / 2- 1 i = 0-M / 2-li = 0-M / 2-l 0-M / 2-1

{x (M + 2i + l)}, {x ((a + l) M + 2i + D, {x ((2a + l) M + 2i + l)}, {x ([a (Al) + l] M + 2i + l)} i = 0-M / 2-li = 0-M / 2- 1 i = 0-M / 2- 1 i = 0-M / 2-l

{x (2M + 2i)}, {x ((a + 2) M + 2i)}, {x ((2a + 2) M + 2i)}, {x ([a (Al) +2] M + 2i)} i = 0-M / 2- 1 i = 0-M / 2-li = 0-M / 2-li = 0-M / 2-l

{x (2M + 2i + l)}, {x ((a + 2) M + 2ill)}, {x ((2a + 2) M + 2i + l)}, {x ((a (Al) + 2] MI2i + l)} i = 0 ~ M / 2-1 i = 0 ~ M / 2-li = 0 ~ M / 2- 1 i = 0 ~ M / 2-l

{x ((a-l) M + 2i)}, {x ((2a-l) M + 2i)}, {x ((3a-l) M + 2i)}, {x ([a (Al) + al] M + 2i)} i = 0 ~ M / 2- 1 i = 0 ~ M / 2- 1 i = 0 ~ M / 2-li = 0 ~ M / 2-l

{x ((al) M + 2i + l)}, {x ((2a-fine i + l)}, {x ((3a-l) M + 2i + l)}, {x ([a (Al ) + a-M + i + l)} i = 0 ~ M / 2- 1 i = 0 ~ M / 2- 1 i = 0 ~ M / 2- 1 i = 0 ~ M / 2-l There is no need to wait until all the data up to Group A is obtained by rearranging as described above.After reading the column consisting of b odd-numbered data and the column consisting of b even-numbered data from the memory, Output processing can be started immediately after the transposition operation.

 The first data rearrangement circuit 310 shown in FIG. 4 sequentially stores 2b pieces of data input in parallel by 2b pieces into one of the double buffer memories 311 in accordance with the above reading order from the other memory. It reads out 2 b pieces in parallel, and sends out 2 a pieces each of a pieces from each of the two corner turners.

FIG. 6 is a configuration example of the second read address generation circuit 313. In the figure, the group cluster number counter 3131 (counter A), the group number counter 3132 (counter a), and the column number counter 3133 (counter B) are the clusters, groups in the cluster, and columns in the group in the above reordering description. Address 313 4 is a configuration in which these bits are simply connected in this order.

 The second read address generation circuit 313 exchanges the carrier connection between the group number counter 3132 and the column number counter 3133 and carries out the carrier connection so that the column number counter 3133 is updated by the carrier of the group number counter 3132. Therefore, the reading of the column at the corresponding position in each group is continuous in time series within the class evening.

 Next, in the second half of the rearrangement method 2 in the first stage, that is, in the second data rearrangement circuit 320, based on the result of the first half (first data overnight rearrangement circuit 310), the input to the a pipeline FFT circuits is performed. In this way, a data set consisting of M data points separated by M points in time series is created. That is, it is necessary to rearrange them so that they are in column a. Since each pipeline FFT circuit has two parallel inputs, the overall configuration is 2a column.

 In the first data rearrangement circuit 310, a set of M-point data that is continuous in time series (within a two-column platoon) is organized into a-column platoon. By collecting one by one, a data set consisting of M data separated by M points in time series can be obtained. Since the set has two columns, each column in the group contains two data points belonging to the same set of consecutive M points, and if the column is the unit of reading, two The data of the pipeline FFT is obtained. For a pipeline FFT circuits, the reading process may be performed in a / 2 column unit.

 Each group is divided into A classes if the two-row unit is a cluster (from (M / 2) ÷ (a / 2) = A).

 Hereafter, each group will be processed as follows on a class evening basis.

For each of the columns of the first cluster of the first group (i = 0 to a / 2-l), data taken every third from the top aZ2 columns a / 2, every third from the third Data taken az Two rows a / 2 consisting of 2 pieces, data taken every 3rd from the second row a / 2 pieces consisting of a / 2, Data taken every 3rd from the fourth Transpose each column aZ2 consisting of a / 2 as a Z2) X (aX2) matrix.Data taken every third column from the top for each column of the first cluster of the second group a / 2 A column consisting of two aZ, 3rd force, etc.Data taken every third a / 2 columns aZ consisting of two, data taken every second from three aZ2 columns consisting of aZ2, Fourth power, Transpose each column aZ2 consisting of the data aZ2 taken every third as a (a / 2) X (a / 2) matrix, and place it next to the transpose from the first group.

 Similarly, for each of the columns in the first class of Group A, every third column of data from the beginning, data az2 every 3 rows from the beginning, and every third row of data aZ2 A column consisting of a / 2, data taken every third from the second aZ2 a column consisting of two a, and data taken every third from the fourth a / 2 columns aZ each consisting of ( aZ2) Transpose as an X (a / 2) matrix, and place it next to the transpose from group A-1. For the four (a / 2) X (M / 2) matrices obtained in this manner, each row of the first matrix is sequentially assigned to the 4h + 1 (h = 0 to aZ2−1) line, Each row of matrix 2 is 4h + 2 (h = 0 to aZ2—l) line, each row of third matrix is 4h + 3 (h = 0 to aZ2—1) line, By setting each row to the number 4h + 4 (h = 0 to aZ2-1), the first group shown in Table 3 below can be obtained.

 Again, the same procedure is applied to each of the columns (i = aZ2 to a_l) of the next cluster in the first group, and transposed as (a / 2) X (a / 2) matrices. The same is done for each of the columns (i = aZ2 to a-1), transposed as (a / 2) X (a / 2) matrices, and placed next to the transpose from the first group. Similarly, for group A, the same procedure is performed for each of the columns of the next class (i = aZ2 to a-l), and transposed as a / 2) X (a / 2) matrix. Place next to transposition from group one. For the four (a / 2) X (M / 2) matrices obtained in this manner, each row of the first matrix is sequentially assigned to line 4h + 1 (h = 0 to aZ2-1), Each row of the matrix 2 is assigned to the 4h + 2 (h = 0 to aZ2_l) line, each row of the third matrix is assigned to the 4h + 3 (h = 0 to a / 2-1) line, By making each row of the matrix a line of number 4 + 4 (h = 0 to aZ2-1), the following second group is obtained. Hereinafter, a third group is obtained in the same manner.

In the same way, take the last class of the first group to the A group in the same procedure ((A-1) a Z 2 to Aa / 2-1 (= Μ / 2-1)) and take (aZ2) Transpose as an X (a / 2) matrix, similarly construct four (aZ2) X (M / 2) matrices, and replace each row of the first matrix with 4h + l (h = 0 to aZ2 1) line, each row of the second matrix is 4 Line h + 2 (h = 0 to a / 2—l), each row of the third matrix is replaced by line 4h + 3 (h = 0 to aZ2—1), and line 4h + 4 of the fourth matrix ( By setting the line of h = 0 to a / 2-1), the following group A is obtained.

 (Table 3)

 Group 1 Group 2… Group A

 {x (2j * M + 2 * 0)}, {x (2j * M + 2 * (a / 2))}, {x (2j * M + 2 * (a / 2 (Al)))} { x ((2j + l) * M + 2 * 0)}, {x ((2j + l) * M + 2 * (a / ¾), {x ((2j + l) * M + 2 * (a / 2 (Al)))} j = 0 ~ M / 2-lj = 0 ~ M / 2-lj = 0 ~ M / 2-l {x (2j * M + l + 2 * 0)}, {x (2j * M + l + 2 * (a / 2))}, {x (2j * M + l + 2 * (a / (Al)))}

{x ((2j + l) * M + H2 * 0)}, {x ((2] '+ l) * M + l + 2 * (a / 2))}, {x ((2j + l) * M + l + 2 * (a / 2 (Al)))) j = 0 ~ M / 2-lj = 0 ~ M / 2- 1 j = 0 ~ M / 2- 1

{x (2j * M + 2 * l)}, {x (2j * M + 2 * (a / 2 + 1))}, {x (2j * M + 2 * (a / 2 (Al) + l ))) {x ((2j + l) * M + 2 * l)}, {x ((2j + l) * M + 2 * (a / 2 + 1))}, {x ((2j + l ) * M + 2 * (a / 2 (A-1) +1))) j = 0 ~ M / 2- 1 j = 0 ~ M / 2-l j = 0 ~ M / 2-l

{x (2j continued +2)}, {x (2j * M + H2 * (a / 2 + 1))}, {x (2j continued + 2 * (a / 2 (All))} {x ( (2j + l) * M + l + 2 * l)}, {x ((2j + l) * M + l + 2 * (a / 2 + 1))}, {x ((2j + l) * M + l + 2 * (a / 2 (A-) + l))) j = 0 ~ M / 2-lj = 0 ~ M / 2-lj = 0 ~ M / 2-1

{x (2j * M + 2 * 2)}, {x (2j * M + 2 * (a / 2 + 2))}, {x (2j * M + 2 * (a / 2 (A-1) +2))} i ((2 j H) view * 2)}, {x ((2 j +1) * M + 2 * (a / 2 + 2))}, {x ((2j + l) View * (a / 2 (A-1) 12))} j = 0 ~ M / 2- 1 j = 0 ~ M / 2-l j = 0 ~ M / 2-l

{x (2j * M + l + 2 * 2)}, {x (2j * M + l + 2 * (a / 2 + 2))}, {x (2j * M + l + 2 * (a / 2 (A-1) +2)))} {x ((2j + l) * M + l + 2 * 2)}, {x ((2 j +1) (a / 2 + 2))}, { x ((2 j +1) \ m (a / 2 (Al) +2))} j = 0-M / 2_l j = 0-M / 2-lj = 0-M / 2-l {x (2j (a / 2-1))}, {x (2j * M + 2 * (a / 2 + a / 2-l))}, {x (2j (a / 2 (A-1) + a / 2-l))} {x ((2j + l) 2 * (a / 2-l))}, {x ((2j + l) 2 * (a / 2 + a / 2- l ))), {X ((2j + l) 2 * (a / 2 (A_l) + a / 2-l))} j = 0 ~ M / 2-1 j = 0 ~ M / 2-1 j = 0 to M / 2—l

 j = 0 ~ M / 2-l j = 0 ~ M / 2- 1 j = 0 ~ M / 2-l Each of the obtained lines, in order from the top, forms two parallel inputs of each pipeline FFT circuit I do. Actually, it is not necessary to wait until all the data is obtained up to the group A by rearranging as described above, and the data taken every third from the top a / 2 columns a Z 2

3rd power ^ et al. Data taken every 3rd a Z 2 rows a 2 Data taken every 3rd from the second a2 2 rows aZ 2x, Data taken every 3rd from the fourth a After reading a / 2 columns a / 2 from memory, output processing can be started immediately by transposing (a / 2) X (a / 2) rows and columns, respectively.

The second data reordering circuit 320, which is the second half of the pre-stage data reordering unit 3B (method 2) in FIG. In this way, 2a pieces are read in parallel from the other memory according to the above reading order while the pieces are sequentially stored, and two sets of aZ are sent out from four sets of corner turners, for a total of 2a pieces. In particular, when a = 2, the transpose operation is a 1 X 1 matrix, and the cornerer function is not required, and only data is routed. FIG. 7 is a configuration example of the third read address generation circuit 323. In the figure, the group number counter 3231 (A counter), column cluster number counter 3232 (A counter), and column number counter 3233 (aZ2 counter) are the groups, column clusters in the group, An address is simply a concatenation of these bits in this order. The group number counter 323 1 and the column class number counter 3232 are exchanged, and a carrier is connected so that the column cluster number counter 3232 is updated by the carrier of the group number counter 3231, and the column cluster at the corresponding position of each group is updated. Reading is continuous in time series. Next, the operation performed by the data rearrangement unit in the subsequent stage is exactly the same as the latter half of the rearrangement method 2 in the previous stage. The output of the pipeline FFT in the preceding stage is arranged as shown in Table 4 below. Each line corresponds to the output line from the previous stage (that is, two lines each correspond to one pipeline output).

 (Table 4)

 Group 1 Group 2 Group A

{XI (2 side)}, {XI (2j = f = M + 2 * (a / 2))}, {XI (2j * M + 2 * (a / 2 (Al))))} ΐ ((2 ] +1) * Μ + 2 * 0)}, {Xl ((2j + l) * M + 2 * (a / 2))}, Oil ((2j + l) * M + 2 * (a / 2 (A-1)))} j = 0-M / 2- 1 j = 0-M / 2- 1 j = 0-M / 2_l 1 (2) · + 2 * 0)}, {Xl ( 2] '* M + l + 2 * (a / 2))}, {XI (2j * M + l + 2 * (a / 2 (Al)))}

{Xl ((2j + l) * M + l + 2 * 0)}, {Xl ((2j + l) * M + l + 2 * (a / 2))}, {XI ((2j + l) * M + l + 2 * (a / 2 (Al)))) j = 0 ~ M / 2-lj = 0 ~ M / 2-lj = 0 ~ M / 2-l

{XI (2j * M + 2 * l)}, {XI (2j * M + 2 * (a / 2 + 1))}, {XI (2j * M + 2 * (a / 2 (Al) + l ))} l ((2j + l) * M + 2 * l)}, l ((2j + l) * M + 2 * (a / 2 + l))}, {Xl ((2j + l) * M + 2 * (a / 2 (Al) + l))) j = 0-M / 2- 1 j = 0-M / 2_l j = 0-M / 2- 1 (Xl (2j * M + l + 2 * l)}, {XI (2j * M + l + 2 * (a / 2 + 1))}, {XI (j * M + l + 2 * (a / 2 (Al) + l))} {Xl ((2j + l) * M + l + 2 * l)} ₎ {Xl ((2j + l) * M + l + 2 * (a / 2 + l))}, {XI ((2j + l) * M + H2 * (a / 2 (Al) H))) j = 0 ~ M / 2-lj = 0 ~ M / 2-lj = 0 ~ M / 2-l

{Xl (2j * M + 2 * 2)}, {XI (2j¾ + * (a / 2 + 2))}, {XI (2j * M + 2 = i = (a / 2 (Al) +2) )} {xi ((2j + i) m)}, {xi ((2j +1) (a / 2 + 2))}, {xi ((2] +1) lake * (a / 2 (AI ) +2))} j = 0 ~ M / 2-lj = 0 ~ M / 2- 1] = 0 ~ Μ / 2- 1

{XI (2 j * M + l + 2 * 2)}, {XI (2j * M + l + 2 * (a / 2 + 2))}, {XI (2 j * M + l + 2 * ( a / 2 (Al) +2))} {Xl ((2j + l) * M + l + 2 * 2)}, (Xl ((2j + l) * M + l + 2 * (a / 2 + 2))), {XI ((2j + l) * M + l + 2 * (a / 2 (Al) +2))} j = 0-M / 2- 1 j = 0-M / 2- 1 j = 0-M / 2-l

{XI (2j mm (a / 2-1))}, {XI (2j mm (a / 2 + a / 2-1))}, {XI (2j * M + 2 * (a / 2 (A- 1) + a / 2- 1))}

 (a / 2-1))), {Xl ((2i + l) «2 * (a / 2 + a / 2-l))}, {Xl ((2jll) e2 * (a / 2 (Al) ½ / 2-l))) j = 0 ~ M / 2- 1 j = 0 ~ M / 2-lj = 0 ~ M / 2- 1

{XI (2 j * M + l + 2 * (a / 2-1))}, {XI (2 j * M + l + 2 * (a / 2 + a / 2-l))}, {XI (2j * MH + 2 * (a / 2 (A- 1) ½ / 2-l))} j = 0 ~ MZ2-l j = 0 ~ M / 2-lj = 0 ~ M / 2-l

(Sheet rearrangement method 2: When a≥2)

 The data rearranging unit 4A in the subsequent stage shown in FIG. 5 creates a data set consisting of M data units M points apart from the output sequence of the previous stage FFT and rearranges them so that they are in a column. In particular, within each set of data sequences, two columns should be used. In the output of the previous stage, a set of M point data (two columns in the set) are arranged in a column, so if one set of data at the corresponding position of each set is collected, data M points apart It is possible to obtain a data set consisting of individual data.

 Since the group consists of two columns, each column in the group contains two sets of data belonging to the same M-point data set. Since the data of the FT circuit can be obtained, it is sufficient to read and rearrange in a / 2 column units for a pipeline FFT circuits. Each group can be divided into A clusters consisting of a 2 columns, where a / 2 column unit is one cluster.

Hereinafter, each group is processed as follows in cluster units. First class of the first group Evening column (i = 0 to aZ2-1) Data taken every 3rd from the beginning For each column a / 2 consisting of 2 aZ, taken every 3rd from the third Data aZ 2 rows a / 2 pieces, 2nd force ^ 3 rows of data a 2 rows of 2 rows a, 2 rows, data taken every 3rd row from 4 a Z 2 rows Transpose the two columns a as two (a / 2) X (a / 2) matrices, and from the az2 data taken every third column from the beginning for each column in the first class of the second group The sequence aZ2, from the third to the third Data taken every other row a / 2 rows of aZ2, data taken every 3rd from the second a 2 rows a / 2 each of 2 rows, taken every 3rd from the fourth Transpose each column a / 2 of data a / 2 as (aZ2) X (a / 2) matrix, and place it next to the transpose from the first group.

 Similarly, for every column of the first cluster in group A, the data taken every 3rd from the beginning a / 2 rows of a / 2, the third force, and the data taken every 3rd aZ 2 columns a / 2, data taken every 3rd from the second aZ2 columns a2 Data taken every 2th, 3rd from the fourth a / 2 columns a Transpose each of them as (aZ2) X (a / 2) matrix, and place them next to Transpose from group A-1. Regarding the four (aZ2) X (M / 2) matrices obtained in this way, the rows of the [; matrix are sequentially replaced by the 4h + 1 (h = 0 to a / 2-1) line, Each row of the second matrix is the line of 4h + 2 (h = 0 to aZ2_l), each row of the third matrix is the line of 4h + 3 (h = 0 to aZ2-1), and the row of the fourth matrix is The first group in Table 5 below can be obtained by setting each row to the number 4h + 4 (h = 0 to aZ2-1).

 Again, we take the same procedure for the next class column (i = aZ2 ~ a-1) of the first group, transpose each as an (a / 2) X (a / 2) matrix, and Column (i = aZ2 ~ a-1), transpose it as (aZ2) X (a / 2) matrix, and place it next to the transpose from the first group.

 Similarly, for the group A, the next class column (i = aZ2 to a-1) is similarly taken and transposed as a (a / 2) X (aZ2) matrix, and the group A-1 Place next to the transpose from. For the four (a / 2) X (M / 2) matrices obtained in this way, each row of the first matrix is sequentially assigned to line 4h + 1 (h = 0 to aZ2-1), and the second Each row of the matrix is the 4h + 2 (h = 0 to aZ2—l) line, each row of the third matrix is the 4h + 3 (h = 0 to aZ2—1) line, and each row of the fourth matrix is The second group in Table 5 can be obtained by setting the row to the line of 4h + 4 (h = 0 to aZ2-1).

The third group is obtained in the same manner as described below, and the same procedure is used for the last class of the first group to the A group Evening column (i = (A-1) aZ2 to Aa2 21 (= M / 2- 1 )) The transposes as a (aZ2) X (a / 2) matrix to form (aZ2) X (M / 2) matrices, which are similarly associated to obtain Group A in Table 5.

(Table 5)

 Group 1 Group 2 Group 3 Group A

{XI (2Ϊ)}, {Xl (aM + 2i)} {XI (2aM + 2i)} {Xl ((Al) aMI2i)} {XI (2iH)}, {Xl (aM + 2i + l)} { XI (2aM + 2i + l)} {Xl ((Al) aMI2i + l)} i = 0-M / 2-li = 0-M / 2-li = 0-M / 2- 1 i = 0-M / 2-1 {Xl (M + 2i)}, {x ((a + l) M + 2i)}, {XI ((2a + l) M + 2i)}, {XI (((Al) a + l) M + 2i)} {XI (M + 2i + l)}, {x ((a + l) M + 2i + l)}, {XI ((2a + l) M + 2i + l)}, {XI (((Al) a + l) M + 2i + l)} i = 0-M / 2-1 i = 0-M / 2- 1 i = 0-M / 2-li = 0-M / 2-l

{XI (2M + 2i)}, {x ((a + 2) M + 2i)}, {XI ((2a + 2) M + 2i)}, {XI (((Al) a + 2) M + 2i)} {XI (2Μ + 2Ϊ + 1)}, {x ((a + 2) M + 2i + l)}, {XI ((2a + 2) M + 2ill)}, {XI (((Al ) a + 2) M + 2i + l)) i = 0 ~ M / 2-li = 0 ~ M / 2-1 i = 0 ~ M / 2- 1 i = 0 ~ M / 2-1

{Xl ((al) M + 2i)}, (x ((2a-l) M + 2i)}, {XI ((3a-l) M + i)}, {XI (((Al) a½-l) M + 2i)} {Xl ((al) M + 2i + l)}, {x ((2a-l) M + 2i + l)}, {XI ((3a-l) M + 2iH)}, { XI (((Al) a + al) M + 2i + l)} i = 0-M / 2-li = 0-M / 2-1 i = 0-M / 2-1 i = 0-M / 2 — 1 In each of the obtained lines, the top two lines form two parallel inputs of each pipeline FFT circuit in actuality.In practice, it is necessary to rearrange as above and wait until all the units in Group A are obtained. But data taken every 3rd from the beginning aZ2 columns aZ2, data taken every 3rd from the third aZ2 columns aZ2 data taken every 3rd from the second a / 2 columns aZ2, data taken every third from the fourth a / 2 columns aZ read from memory, transpose each (a / 2) X (a / 2) matrix The output process can be started immediately upon operation. The rear-stage data rearranging section 4A in FIG. 5 stores the data input in parallel by 2a at a time in the double buffer memory in the same manner as the second data rearranging circuit 320, which is the latter half of method 2 of the front-stage data rearranging section. In this manner, 2a pieces are sequentially stored in the other memory, and 2a pieces are read out in parallel from the other memory according to the above reading order, and a / 2 pieces are sent out from a set of four co-catalogers in total of 2a pieces each. The read address generation circuit 323 is the same as that of the second data rearrangement circuit.

 (Multiplying of torsion coefficient)

 Following the rearrangement of the data, the torsional coefficient multiplied by the torsional coefficient multiplier is as shown in Table 6. Equation (1), which is the first step of the N = MXM point Fourier transform, is an M point DFT equation for k1 when k0 is fixed. When processed by the radix-2 pipeline FFT, the output index order Has a bit-reverse relationship with the index order obtained by the DFT equation. Therefore, when the torsion coefficient multiplication in equation (2) is performed according to the output index order of the radix-2 pipeline FFT, it is necessary to use a bit-reversed value for the torsion coefficient index n 0.

 In the rearrangement for input of the pipeline FFT in the latter stage described above, the data array is in a one-dimensional expression, but in a two-dimensional expression, that is, in a matrix expression, a value multiplied by M is a row index. Yes, the rest are column indexes. It is necessary to use the bit reverse value of this row index as the index of the torsion coefficient. Since there are a pipeline FFT circuits, the rows of the data array are divided into a sets of two rows each, and each set is subdivided into A pieces with M point data. From the viewpoint of columns, the whole is divided into A groups.

 Therefore, assuming that the bit reverse operation is BR [], the data input and the arrangement of the corresponding torsion coefficients are as follows. However, BR [] is a bit reverse operation in which [] is regarded as m bits.

 (Table 6)

 Group 1 torsion coefficient Group 2 torsion coefficient ... Group A torsion coefficient

{W «(BR [0] x (2i))}, {W ** (BR [a + 0] x (2i))}, {W ** (BR [(A-l) a + 0] x (2i))} {W «(BR [0] x (2i + l))}, {W ** (BR [a + 0] x (2i + l))}, {W ** (BR [( A-1) a + 0] x (2i + l))} i = 0 ~ M / 2-li = 0 ~ M / 2-li = 0 ~ M / 2-1

{W ^ (BR [l] x (2i))}, {W «(BR [a + l] x (2i))}, {W ** (BR [(A-1) a + 1] x ( 2i))) {W «(BR [l] x (2i + l))}, {W« (BR [a + l] x (2i + l))}, {W «(BR [(A-1 ) a + 1] x (2i + l))) i = 0-M / 2—1 i = 0-M / 2—1 i = 0-M / 2_l

{W ** (BR [2] x (2i))}, {W ** (BR [a + 2] x (2i))}, {W ** (BR [(A_1) a + 2] x ( 2i))} {W «(BR [2] x (2i + l))}, {W« (BR [a + 2] x (2i + l))}, {W «(BR [(A-1 ) a + 2] x (2i + l))) i = 0-M / 2-li = 0-M / 2-li = 0-M / 2_l

{W «(BR [al] x (2i))}, {* (BR [a + a—l] x (2i))}, {« (BR [(Al) a + al] x (i)) } {W ** (BR [al] x (2i + l))} _; {W = f = * (BR [a + al] x (2i + l))}, {W «(BR [(Al) ala-l] x (2i + l))} i-0 ~ M / 2-li = 0 ~ M / 2-li = 0 ~ M / 2—1 (Data sorting method 2: a = l)

 Next, the case where a = 1, ie, one pipeline FFT circuit at each stage is shown. As in the case of a≥2, the input time-series data {x (t): t = 0 to 2 * * m—1} is assumed to be input in 2b units in parallel. If they are grouped individually and they are grouped across the input data line, they can be divided into M groups each consisting of M point data as shown in Table 7. Here, B is the number of input counts until M point data when B = MZ 2b and the parallelism is 2b, and 2b is the input parallelism.

(Table 7)

 Group 1 Group 2 Group 3 Group M

{x (2bj)}, {x (M + 2bj)} {x (2M + 2bj)} {x ((Ml) M + 2bj)} j = 0 to B—lj = 0 to B—1 j = 0 ~ B- 1 j = 0 ~ B— 1 Input data line 2;

 {x (2bj + D), {x (M + 2bj + l)}, {x (2M + 2bj + l)} {x ((Ml) M + 2bj + l)} j = 0 to B— 1 j = 0 to Bl j = 0 to B— 1 j = 0 to B— 1 Input T-line 3;

 {x (2bjl2)}, ix (M + 2bj + 2)}, {x (2MI2bj + 2)} {x ((Ml) M + 2bj + 2)} j = O ^ Bl j = 0〜B— 1 j = 0 ~ B— 1 j = 0 ~ Bl Input data "-Taline 2b;

 {x (2bj + 2b-l)}, {x (M + 2bj + 2b-l)}, {x (2M + 2bj! 2b-l)}, {x ((Ml) M + 2bj + 2b-l )} j = 0-Bi j = 0-B— 1 j = 0-B—lj = 0-B— 1

(Pre-stage data sorting method 2: a = l)

 First, the first data rearrangement circuit 330 shown in FIG. 8 rearranges the data so that M sets of data consisting of M points in time series are arranged in a single column. In particular, each data set is rearranged so that it has two columns in it. The following is the procedure. The M groups are processed as follows.

 Create a column consisting of b odd-numbered data columns and b columns of even-numbered data columns in the first column of the first group. Transpose. Next, create a column consisting of b odd-numbered data and a column consisting of b even-numbered data in the second column of the first group, and consider the odd-numbered data and even-numbered data as b x 1 matrices, respectively. Transpose and place next to the transpose from the first row.

In the same manner, a column composed of b odd-numbered data and a column composed of b even-numbered data in the B column of the first group is formed, and the odd-numbered data and the even-numbered data are represented by bX, respectively. Transpose as one matrix, and place it next to the transpose from column B-1. An IX (bXB) [= 1X (M / 2)] matrix consisting of B matrices of size 1 Xb obtained from odd-numbered data is taken as odd-numbered lines, and is obtained from even-numbered data. The first group in Table 8 below is obtained by taking the rows of the matrix IX (M / 2) matrix as even-numbered lines. Can be

 Similarly, when the second group is performed, the second group shown in Table 8 is obtained. Similarly, finally, the M-th group in Table 8 is obtained from the M-th group. Actually, there is no need to wait until all the data up to the M-th group is obtained by rearranging as described above.After reading the column consisting of b odd-numbered data and the column consisting of b even-numbered data from the memory, bX Output processing can be started immediately after transposing the l matrix.

 (Table 8)

 Group 1 Group 2 Group 3 Group M

{x (2i)}, {x (M + 2i)} {x (2M + 2i)} {x ((Ml) M + 2i)} {x (2i + l)}, {x (M + 2i + l)} {x (2M + 2i + l)} {x ((Ml) MI2i + l)} i = 0-M / 2-li = 0-M / 2-li = 0-M / 2-1 i = 0 to M / 2- 1 The first data rearranging circuit 330 of FIG. 8 stores the data input in parallel by 2 b in units of 2 b in one side of the double buffer memory while sequentially storing the data in the other side. The data is read out from the memory in parallel in the order of 2 b above in accordance with the above reading order, and two pieces are sent out one by one from each of the two sets of corners (in this case, the parallel-in / serial-out circuit). is there.

 FIG. 10 is a configuration example of the fourth read address generation circuit 333. Group number counter (M counter) 3331 and column number counter (B counter) 3332 in the figure are means for specifying each of the groups and columns in the group in the above description of reordering. It is a configuration simply connected in order.

 Next, the second-stage data reordering circuit 340 in the preceding stage generates a data set consisting of M data separated by M points in time series so as to be input to one pipeline FFT circuit based on the results of the first half. make. That is, it is necessary to rearrange them so that they become one column.

In the first data reordering circuit 330 in the preceding stage, a set of M-point data that are continuous in time series (two columns in the group) are organized in a single column, and after that, the corresponding position of each group is If data is collected one by one, a data set consisting of M data separated by M points in time series can be obtained. Since the group has two columns, 2 Data belongs to another set as M sets of data separated by M points. If the entire column is the read unit, the pipeline FFT circuit is one set, so the other is not needed immediately and must be read again. However, the pipelined FFT circuit has two parallel inputs and outputs, and requires another data of the same set of M data separated by M points. That is, it is necessary to read from two groups simultaneously.

 The configuration for this may be the same as the method 1 of the data reordering unit 3A in the preceding stage shown in FIG. That is, the data group obtained from the first data rearrangement circuit 330 stores the odd-numbered and even-numbered groups in separate banks in a buffer memory divided into two banks. Two banks, one each from the top of the corresponding group from each bank, are the two parallel inputs of the pipeline FFT circuit. For each group in the bank, read one data at the corresponding position for each group, such as one head data of the first group, one head data of the next group, and one head data of the next group. Group (MZ 2nd group) and the first group in Table 9 is obtained. The next one after the first group, the next one after the second group, and so on until the data of each group are exhausted, and up to the Mth group in Table 9 are obtained. After that, it switches to another buffer bank and performs the same processing.

 (Table 9)

 Group 1 Group 2 Group 3… Group M

{x (M (2j))}, {x (M (2j) ll)}: {x (M (2j) +2)}, {x (M (2j) + M-1)} ix (M ( 2j + l)}, {x (M (2j + l) H)} _; {x (M (2j + l) +2)}}, {x (M (2j + l) + Ml)} j = 0 ~ M / 2-lj = 0 ~ M / 2-lj = 0 ~ M / 2-lj = 0 ~ M / H The two lines of each group obtained are two parallel inputs of the pipeline FFT circuit. There is no need to wait until all the data up to the M-th group is obtained by rearranging as described above, and the data is read from the two banks and immediately output to the pipeline FFT circuit.

The second data rearrangement circuit 340 in FIG. 8 stores two data, which are input in parallel two by two, in one of the double buffer memories while alternately switching banks each time the number of data becomes M, and stores the two data in the other memory. Read two each from the bank simultaneously Then, two of the required ones are sent out each.

 FIG. 11 shows a configuration example of the fifth read address generation circuit 343. The group number counter 3431 (MZ2 counter) and column number counter 3432 (M / 2 counter) in the figure are means for specifying each of the groups and columns in the group in the above description of reordering, and the row number counter 3433 (2 The counter) is a means for selecting one data item in the column data (consisting of two data items). The read address of the column data has a configuration in which the bits of the group number counter 3431 and the column number counter 3432 are simply connected. The value of the row number counter 3433 is a selection signal for one target data in the column. The row number counter is updated with the carrier of the group number counter 3431, and the carrier connection is performed so that the column number counter is updated with the carrier of the row number counter 3433, and one carrier at the corresponding position of each group is The data (that is, the column to which it belongs, and the position in each group is relatively the same and the position in the column is also the same) is read out continuously in chronological order.

 (Second stage data sorting method 2: a = l)

 The operation performed by the rearrangement unit 4B shown in FIG. 9 is exactly the same as the operation performed by the second data rearrangement circuit 340 (the latter half of Method 2) of the rearrangement unit. The output of the pipeline FFT in the preceding stage is as shown in Table 10. Each line corresponds to the output order of data from the preceding FFT output line.

(Table 10)

 Group 1 Group 2 Group 3 Group M

{xl ((2j))}, {xl (M (2j) + l)}, {xl (M (2j) +2)}, {xl (M (2j) + M-1)} {xl (M (2j + l)}, {xl (M (2jll) + l)}, {xl (M (2j + l) +2)}, {xl (M (2j + 1) + M-1)} j = 0 ~ M / 2- 1 j = 0 ~ M / 2-lj = 0 ~ M / 2-lj = 0 ~ M / 2-l Data rearrangement unit 4 B at the subsequent stage is Μ point away from the FFT output dataデ ー タ Create a data set consisting of 換 え pieces and rearrange them so that they are in a single column. In particular, the data in each group should be in a two-column form. (Two columns in a group) are arranged in a single column, so the corresponding position of each group By collecting the data at each position, a data set consisting of M data separated by M points can be obtained.

 Since the inside of the group is a two-column column, the two data in each column in the group are different sets as data M sets separated by M points, and if the column is the unit of readout, Since the pipeline FFT circuit is one set, the other is not needed immediately and needs to be read again. However, the pipeline FFT circuit has two parallel inputs and outputs, and requires another set of data that is the same as M sets of data separated by M points. That is, it is necessary to read from two groups simultaneously. The configuration for this may be the same as the rearrangement unit 3A in the first stage of Method 1. That is, the data group obtained from the preceding pipeline FFT circuit stores the odd-numbered and even-numbered groups separately in the buffer memory divided into two banks (bank A and bank B). Two banks, one each from the top of the corresponding group from each bank, are the two parallel inputs of the pipeline FFT circuit.

 Each group in the bank has one head data of the first group, one head data of the next group, and one head data of the next group. After reading out and reaching the last group (M / 2th group), the following first group is obtained. Again, the next one of the first group, the next one of the second group, etc. are performed until the data of each group runs out, and up to the M-th group in Table 11 below is obtained. After that, it switches to another buffer bank and performs the same processing. (Table 11)

 Group 1 Group 2 Group 3 Group M

{xl (2i)}, ixl (M + 2i)}: {xl (2M + 2i)}, {xl ((Ml) M + 2i)} {xl (2i + l)} _; {xl (M + 2i) + l)} _; {xl (2M + 2i + l)}, {xl ((Ml) M + 2i + l)} i = 0 to M / 2-1 i = 0 to M / 2-li = 0 to M / 2-li = 0 to M / 2- 1 The resulting lines of each group form two parallel inputs of the pipelined FFT circuit. In practice, there is no need to wait until all the data up to the M-th group is obtained by rearranging as described above, and the data can be read from the second bank and immediately output to the pipeline FFT. The rear-stage data rearranging section 4B shown in FIG. 9 stores data input in parallel two by two in the same manner as the second data rearranging circuit 340 (method 2) of the front-stage data rearranging section 3C in one of the double buffer memories. Then, each time the number of banks becomes M, the banks 341 A and 341 B 'are alternately switched and stored two by two, and two banks are simultaneously read out from the two banks of the other memory, and one of the necessary ones is read out. It is sent out. The fifth read address generation circuit 343 'is the same as the fifth read address generation circuit 343 of the second data rearrangement circuit 340 of the preceding data rearrangement section 330.

(Multiplication of torsional coefficient: when a = l)

 The torsion coefficient multiplied by the torsion coefficient multiplication unit following the rearrangement of the data at the subsequent stage is as follows: if there is one pipeline FFT in each stage, that is, if a = 1, then if a≥2, then a = l, A = M Table 12 below. However, BR [] is a bit reverse operation in which [] is regarded as m bits.

(Table 12)

 Torsion coefficient of group 1 Torsion coefficient of group 2-torsion coefficient of group M

 {W ** (BR [0] x (2i))}, {W ** (BR [l] x (2i))}, {«(BR [(MD] x (2i))} {W ** (BR [0] x (2i + l))}, {W ** (BR [l] x (2i + l))}, {W «(BR [(MD] x (2i + D)} i = 0 ~ M / 2-li = 0 ~ M / 2-li = 0 ~ M / 2-1

(Parallel configuration)

When the device alone cannot support the data input rate due to restrictions on mounting, for example, the data input rate is equal to the operation rate of the device, and the input parallelism 2b> total pipeline FFT The pipeline width may be 2a. As a countermeasure for this, there is a method of arranging devices in parallel. As a simple configuration, it is only necessary to combine the data line and each device with a demultiplexer. In the case of method 2 for rearranging data at the first stage, the first data, which is the first half of the data rearranging unit (method 2) at the previous stage of each device, is used. Integrated reordering circuit and demultiplexed by reading from buffer memory In some cases, it is advantageous to perform control and downsizing.

 FIG. 12 shows the configuration of the data distribution / rearrangement unit 8.

 In such a configuration, the pre-stage data rearrangement unit of each device has the same configuration as the latter half of the pre-stage data rearrangement unit in Method 2. Therefore, the rearrangement of the data at the rear stage of each device has the same configuration as that of the data rearrangement unit at the front stage as can be understood from the above description. At this time, the number e of parallel-arranged devices should be (2b) ÷ (2a) = b ÷ a, which is a power of 2.

 The size (the number of words) of the integrated buffer memory is the number of devices to be arranged in parallel with the number of Fourier transform points, and the amount allocated to each device is the number of Fourier transform points (the number is doubled if buffering is included). In addition, the size of the corner turner for overnight sorting is also multiplied by the number of devices arranged in parallel. Writing to this integrated buffer is performed in order for each device, in units of the number of Fourier transform points. However, as described in the first half of the data rearrangement (method 2) in the previous stage, the data is read out in parallel 2 times in 2b units, that is, for a column, and output to the corner turner. In the two sets of corner turners, the transposition operation is performed when the number of devices arranged in parallel, that is, (bXaXe) = bXaX (b ÷ a) bXb data is buffered, The data is simultaneously output to each device in a-parallel (a total of 2a parallel for odd / even output lines per device, 2b parallel in total).

 The sixth read address generation circuit 82 corresponding to the demultiplexer control of data reading in the data distribution / reordering unit 8 is as shown in FIG. 13, and a device counter 824 is added, which is used for each device area on the buffer memory. Control the selection. The group cluster number counter 821 (A counter), group number counter 822 (a counter), and column number counter 823 (B counter) in the figure are the explanations of the first rearrangement circuit (first half) of the rearrangement method 2 in the preceding stage. Is a means for specifying each of the clusters, the groups within the clusters, and the columns within the groups, and the device counter is a means for specifying the target data (cluster) of each device. The address is configured by simply connecting the bits of the device counter 824, group cluster number counter 821, group number counter 822, and column number counter 823 in this order.

In the above configuration, the group counter 822 is used to carry the device counter 824. By carrying out the carrier connection so that the column number counter 823 is updated by the carrier of the device counter 824 and the group class number counter 821 is updated by the carrier of the column number counter 823, each group in the cluster is updated. When the reading of the column at the corresponding position (that is, a total of a columns) is continuous in time series, and when the a columns of the data to be processed by a specific device are read, the data to be processed by the next device is read. Address generation is performed so that a columns are read out overnight.

 Note that the sixth read address generation circuit in the case of a = 1 is A M in FIG. 13, and FIG. 14 is obtained by removing the a counter.

 (Bypass processing)

 Until now, the description has been made assuming that the number of Fourier transform points in the former stage is the same as the number of transform points in the subsequent stage. However, if the number of conversion points can be changed by changing the mode with the same device configuration, the versatility of the device will increase. According to Japanese Patent No. 2848134, in the radix R pipeline FFT circuit for R parallel input / output M points (= R * * m), the number of conversion points MZ ( R ** l) MZ (R ** 2) MZ (R ** 3) ···· It is disclosed that the Fourier transform of the R point can be performed.

The following is a brief description of R = 2, a radix-2 pipeline FFT. A parallel input / output M point (= 2 ** m), radix-2 pipeline FFT circuit is a circuit that performs a Fourier transform on data with M number of Fourier transform points. This is to divide the M input data into two parts, and divide the input data into two parts. The circuit is input to the basic circuit of the fast Fourier transform (FFT), and the basic circuit of the two parallel input / output is made into one stage, and m stages are arranged in series to perform the Fourier transform. In the data rearrangement circuit, the input data points M are compared with the data that is MZ (2 ** 1) apart in the first stage, and the data that is MZ (2 * * 2) apart in the second stage. In the third stage, data that is (2 ** 3) apart are rearranged, and in the final stage, data that is one away from each other are rearranged so that they constitute two parallel inputs of the operation unit. Multiply one of the parallel inputs by the torsion coefficient, and perform a butterfly operation (to obtain the sum and difference of the two inputs) on the result and the other input. In Japanese Patent No. 2848134, in a fast Fourier transform circuit at point M (= 2 ** m) consisting of m stages of the above basic circuit, data is rearranged, but a bypass process of directly outputting without performing calculations is performed in one stage. It is shown that the Fourier transform with the number of data points of M / (2 ** K) is performed by performing the data processing and re-arranging and performing the operations in the subsequent steps. And Κ is a positive integer and K <m). It is shown below that the input data to be given is the maximum number of conversion points, and that even if the above-mentioned bypass function is applied, the conversion result can be obtained in a rounded form by the number of conversion points determined by the setting of the bypass function.

 First, an example of data rearrangement for the radix-2 case will be described. After that, it will be shown from the rearrangement method that even if the bypass function is applied, the conversion result can be obtained in a group of conversion points. When the ports of the two parallel inputs of the data reordering unit of the basic circuit are named x and y, and the ports of the two parallel outputs are named a and b, the first stage demultiplexes one M-point time-series data. Is given to two input ports, or the time series data of M points is divided at exactly half, and the first half of MZ (2 ** 1) time series continuous data When port X receives late second half MZ (2 ** 1) time-series consecutive data to port y, it outputs MZ (2 ** 1) consecutive times earlier to port a as output. Reorder the data so that port b has M / (2 ** 1) consecutive data that are slower in time.

 In the second stage, first, the MZ (2 ** 1) data from the input port X is divided into two, and the first half of M / (2 ** 2) data that is earlier in time is output to the output port a. The latter half MZ (2 ** 2) data is output to the output port b, and then the M / (2 ** 1) data from the input port y is divided into two, and the first half MZ ( Rearrange 2 ** 2) data to output port a and output the latter half MZ (2 ** 2) data to output port b.

In the third stage, first, the first M / (2 ** 2) data from the input port X is divided into two, and the first half MZ (2 ** 3) data that is earlier in time is output to the output port a. The latter half outputs M / (2 ** 3) data to output port b, and then divides the first M / (2 ** 2) data from input port y into two The first M / (2 ** 3) data in the first half of the time are output to output port a, and the last M / (2 ** 3) data in the second half Data is output to the output port b to the output port b, and the next remaining MZ (2 ** 2) data from the input port X is again divided into two, and the first half MZ (2 * * 3) outputs the data to output port a, and outputs the latter half MZ (2 ** 3) data to output port b, and returns the next remaining M nodes (2 ** 2) from input port y again Data is divided into two parts, and the first half of the data is output to the output port a in the first half MZ (2 ** 3), and the last half M / (2 ** 3) data is output to the output port b Rearrange it as you like. Subsequent 4 steps, 5 steps · · · · Subdivided and output in the same way. In the above sort, the data appearing at output ports a and b in the first stage are exactly MZ (2 ** 1) apart in time series. In the second stage, continuous M / (2 ** 1) data is divided into two and output to output ports a and b, so that their distance is half of M / (2 ** 1). M / (2 ** 2) pieces. In the third stage, continuous MZ (2 ** 2) data is divided into two and output to output ports a and b, so the distance between them is also half of M / (2 ** 2) MZ (2 ** 3) pieces.

 In the m-th stage, MZ (2 ** m) = MZM = 1 apart, which fulfills the data alignment to be given to the operation unit as required by the FFT algorithm.

 In a fast Fourier transform circuit having a basic circuit including a data rearrangement unit in each stage employing the above rearrangement method, bypass processing, that is, data rearrangement is performed, but the operation is not performed and the bypass function is passed to the next stage as it is. If applied to the first stage, from the reordering description above, in the second stage, of the M consecutive data, first, the first half of MZ (2 ** 1) is divided into two and passed to the calculation unit, and then the second half Since the MZ (2 ** 1) points are divided into two and passed to the operation unit, it can be seen that the MZ (2 ** 1) point Fourier transform result is obtained by separating M / (2 ** 1) points at a time. . If the bypass function is applied to the second stage, from the above description of the rearrangement, the third stage processes consecutive M / (2 ** 2) units of data from each input port in the order of time, that is, divides it into two. It is found that the MZ (2 ** 2) point Fourier transform result is obtained by separating MZ (2 ** 2) pieces at a time. In the same way, it can be seen that the conversion result can be obtained in a rounded form by the number of conversion points even when the bypass function is applied.

With the radix-2 pipeline FFT circuit of the former stage disclosed in this patent 2848134 Then, by using the radix-2 pipeline FFT circuit in which each stage has the above bypass function and applying the bypass function from the first stage to the required stage, NZ2 = (MZ 2) XM, NZ (2 * * 2) = {MZ (2 * * 2)} XM, NX (2 * * 3) = {MZ (2 * * 3)} XM, ··· {N / (M ÷ 2)} XM = 2 XM points It is shown as follows that the Fourier transform of can be performed.

 Since the number of these Fourier transform points is represented by XM, the data supplied to the pipeline FFT in the preceding stage may be supplied to the pipeline FFT circuit by supplying α data every M data to the pipeline FFT circuit. In the radix-2 pipeline FFT of Patent 2848 1 34, when と pieces (= Q! X (M / a)) are supplied at a time, they are separated and point FFTs are sequentially performed in the pipeline FFT, and (Μ / α ) Set output. This is because the columns of each group of the input data {XI (η)} of the post-stage data rearrangement section in the description of the pre-stage and post-stage data rearrangement sections are virtually divided into M / 2 groups by a / 2 columns. The output order is exactly the same as that of the MXM point pipeline FFT, and the input of the subsequent pipeline FFT is one data from the corresponding position of each of the M groups (M total This will be the data rearrangement itself in the latter stage described above. Furthermore, when bypassing to the last operation in the previous stage, the input data sequence of the previous stage pipeline FFT itself comes out in that order, so through the rearrangement of data, after all, successive M points in the original time series You can get a de night.

 If this is given to the subsequent pipeline FFT, the result of M point FFT will be obtained in order. The rearrangement uses the radix-2 pipeline FFT with the same bypass function as the previous stage, and performs the data rearrangement itself. However, if the operation is bypassed from the top in order, the FFT result of MZ 2 points or less can be obtained. As described above, in this patent, a function that can perform Fourier transform up to two points NZ2 by adopting a radix-2 pipeline FFT with a function of bypassing the operation itself of each stage at the front stage Z It is also possible to configure a Fourier transform device having.

 (64-point fast Fourier transform device)

FIG. 15 shows the configuration of an embodiment in which a 64-point FFT is performed. The data input parallelism is 4, the pipeline width is 4 in total, and the data reordering method of the pre-stage data reordering unit 103 follows Method 2 described above. 64-point F FT decomposes to 8 x 8 Then, as shown below, both the first and second stages are discrete Fourier transforms with the number of conversion points M = 8.

 63

 Y (n) = ∑y (k) W * * (nXk) (0)

 k = 0

 Where W = exp (-2 T j / 64)

 n, k = 0 to 63

 Where n = 8Xn l + nO

 k = 8Xk l + kO

 Where n l, n 0 = 0 to 7

 k l, k0 = 0-7

 Then, the discrete Fourier transform equation (0) becomes

 77

 Y (nl, ηθ) = ∑∑y (kl, kO) XW8 ** (nOxkl)

 XW * * (nOxkO) XW8 ** (nlxkO) where W8 = exp (-2; rj / 8)

 Can be broken down into steps;

 Yl (nO, kO) = ∑y (kl, kO) XW8 * * (nOxkl) (1) kl = 0 to 7

 Y2 (nO, kO) = Y1 (nO, kO) XW * * (nOxkO) (2)

Y3 (nO, nl) = ∑Y2 (nO, kO) XW8 * * (nlxkO) (3) kO = 0 to 8 8-point Fourier transform Yl (nO, kO) (k0 = 0 , 2, 4, 6) are calculated by the preceding 8-point radix-2 pipeline FFT circuit 101A in ascending order of k0. The 8-point Fourier transform Yl (nO, kO) (k 0 = 1, 3, 5, 7) is calculated by the preceding 8-point radix-2 pipeline FFT circuit 101B in ascending order of k O.

Equation (2) is calculated by the torsion coefficient multiplication unit 107. The multiplication unit 107 includes a complex multiplication circuit 105 and a coefficient memory 106. 8-point Fourier in equation (3) The transformation Y3 (n0, nl) (n0 = 0, 2, 4, 6) is calculated by the subsequent 8-point radix-2 pipeline FFT circuit 102A in ascending order of n0. Also, the 8-point Fourier transform Y 3

(n0, nl) (n0 = 1, 3, 5, 7) are calculated by the subsequent 8-point radix-2 pipelined FFT circuit 102B in ascending order of n0. The order in which data is output according to the conversion is shown below by data rearrangement.

 First, time-series input data y (k) is input in four parallels. Omit the variable name y and show only the index value. Assuming that the parameters in Table 1 described above are M = 8, b = 2, B = 8Z4 = 2,

 (Table 13)

 Group 1 Group 2 Group 3 Group 4 Group 5 Group 6 Group 7 Group 8

0, 4 8, 12 16, 20 24, 28 32, 36 40, 44 48, 52 56, 60 1,5 9, 13 17, 21 25, 29 33, 37 41, 45 49, 53 57, 61

1, 6 10, 14 18, 22 26, 30 34, 38 42, 46 50, 54 58, 62 3, 7 11, 15 19,23 27, 31 35, 39 43, 47 51, 55 59, 63 Y (k) is rearranged as shown in Table 14 in the first half 103 a of the data rearrangement section 103 according to the data rearrangement method 2 (see FIG. 16 for details). Assuming that the parameters in Table 2 are M = 8, a = 2, A = 8Z2 = 4 (Table 14)

 Group 1 Group 2 Group 3 Group 4

 0, 2, 4, 6, 16, 18, 20, 22, 32, 34, 36, 38, 48, 50, 52, 54

1, 3, 5, 7, 17, 19, 21, 23, 33, 35, 37, 39, 49, 51, 53, 55 8, 10, 12, 14, 24, 26, 28, 30, 40, 42 , 44, 46, 56, 58, 60, 62 9, 11, 13, 15, 25, 27, 29, 31, 41, 43, 45, 47, 57, 59, 61, 63 (See Fig. 16 for details.) In the latter half 103 b, y (k) is rearranged as shown in Table 15 below. Here, the read address generation circuits 103 a-1 and 103 b_1 correspond to those shown in FIGS. 6 and 7, respectively. However, in the rearrangement read address generation circuit 103b-1 in the second half of the figure, the number of the column number counters in the class is one, so the column number counters in the cluster are deleted. (Table 15)

 Group 1 Group 2 Group 3 Group 4

 0, 16, 32, 48, 2, 18, 34, 50, 4, 20, 36, 52, 6, 22, 38, 54

8, 24, 40, 56, 10, 26, 42, 58, 12, 28, 44, 60, 14, 30, 46, 62 (or more, the preceding eight-point radix 2 serial relay FFT circuit 2 parallel inputs to 101A) ) 1, 17, 33, 49, 3, 19, 35, 51, 5, 21, 37, 53, 7, 23, 39, 55

9, 25, 41, 57, 11, 27, 43, 59, 13, 29, 45, 61, 15, 31, 47, 63 (2 or more parallel inputs to the preceding 8-point radix-2 serial FFT circuit 101B) Indicates the order of the two parallel output data Y 1 (8n0 + k 0) from the 8-point radix-2 serial FFT circuit 101A at the preceding stage (only the index 8110 + 1?: 0 value of 丫 1 is displayed). 0, 16, 32, 48, 2, 18, 34, 50, 4, 20, 36, 52, 6, 22, 38, 54 8, 24, 40, 56, 10, 26, 42, 58, 12, 28 , 44, 60, 14, 30, 30, 46, 62 Indicates the order of the two parallel output data Y 1 (8n0 + k 0) from the 8-point radix 2 serial FFT circuit 101 B in the preceding stage (index 8110+ Only 1 ^ 0 value is displayed).

1, 17, 33, 49, 3, 19, 35, 51, 5, 21, 37, 53, 7, 23, 39, 55 9, 25, 41, 57, 11, 27, 43, 59, 13, 29 , 45, 61, 15, 31, 47, 63 For the Y1 data obtained as described above, it is necessary to perform further overnight reordering for conversion to obtain Y3. 104 (Details in Fig. 17) Y (k) is in the order shown in Table 16 below. Note that the read address generation circuit 104-1 in the figure corresponds to the read address generation circuit in FIG. 7, but in FIG. Number counters have been deleted.

 (Table 16)

 Group 1 Group 2 Group 3 Group 4

0, 2, 4, 6, 16, 18, 20, 22, 32, 34, 36, 38, 48, 50, 52, 54 1,3,5,7,17,19,21,23,33,35,37,39,49,51,53,55 (8 points radix in the latter stage) 2 Parallel input to serial FFT circuit 102A )

8, 10, 12, 14, 24, 26, 28, 30, 40, 42, 44, 46, 56, 58, 60, 62

9, 11, 13, 15, 25, 27, 29, 31, 41, 43, 45, 47, 57, 59, 61, 63 (2 or more parallel inputs to the subsequent 8-point radix-2 serial FFT circuit 102B) These are multiplied by the torsional coefficients by four torsional coefficient multiplying circuits, respectively, and then input to the subsequent 8-point radix-2 serial FFT circuits 102A and 102B, and the Y3 data is obtained in two parallel in this order. .

 The coefficients multiplied by the torsional coefficient multiplication unit 105 are as follows: Table 6 shows the parameters in Table 6 where M = 8, a = 2, and 8 = 1 ^ [/ & = 872 = 4. It looks like 7.

 (Table 17)

Exponent of coefficient

 Group 1 Group 2 Group 3 Group 4

 0, 0, 0, 0 0> 4, 8, 12 0, 2, 4, 60, 6> 12, 18

 0, 0, 0, 0 2, 6, 10, 14 1, 3, 5, 7 3> 9> 15, 21

 (The above is the data input to the 8-point radix-2 pipeline FFT circuit 102 A at the subsequent stage.

 0, 8, 16, 24 0, 12, 24, 36 0> 10, 20, 30 0, 14, 28, 42

 4, 12, 20, 28 6, 18, 30, 42 5, 15, 25, 35 7, 21, 35, 49

 (The above is the data of the input to the 8-point radix-2 pipeline FFT circuit 102 B at the subsequent stage.

 As described above in detail, the present invention relates to a configuration of a Fourier transform apparatus composed of a former stage and a latter stage, wherein each stage serves as a transforming means and has an equal number of parallel input / output conversion points M (power of 2) points. Since each radix-2 pipeline FFT circuit has a (multiple of M) FFT circuits and has a data rearrangement means for supplying data to the conversion means at each stage, the pipeline width of the device is The effect is that it does not depend on the conversion points of the individual pipeline FFT circuits of the stage.

Claims

The scope of the claims

 1. A Fourier transform device for performing a discrete Fourier transform,

A conversion unit at the preceding stage that has a number of parallel input / output, radix-2 pipeline FFT circuits with the maximum number of conversion points being M (= 2 ^m , m> = 2) points a, which is a divisor of the maximum number of conversion points M ,

 First data for supplying input data to the preceding conversion means in a first predetermined order;

—Evening supply means,

 A post-conversion means having the same number of 2 parallel input / output M points as the pre-conversion means and a radix-2 pipeline FFT circuit;

 Second data supply means for supplying input data to the subsequent conversion means in accordance with a second predetermined order;

 A Fourier transform device, comprising: a torsion coefficient multiplying means provided between the first and second converting means and multiplying the torsion coefficient.

 2. In the Fourier transform apparatus according to claim 1,

 The first data supply means includes a first memory circuit having a two-bank configuration, a bank for the first memory circuit, and a writing means for alternately sequentially writing M pieces of input data every M data. A Fourier transform device comprising: a read unit that simultaneously reads data at positions corresponding to two banks of the first memory circuit and supplies the read data to the conversion unit in the preceding stage.

3. In the Fourier transform apparatus according to claim 1,

 The first data supply means includes first and second data reordering units for reordering data in a predetermined order in two stages, and the first and second data reordering units store data. A second or third memory circuit, a read or write address generation circuit according to a predetermined logic of each of the second and third memory circuits, and a read or write address from the second or third memory circuit. And a corner turner to sort the data respectively.

The second data supply means is provided with a third data rearrangement unit, and stores a fourth memory circuit for storing data, and a readout circuit according to a predetermined logic of the fourth memory circuit. Alternatively, the read address is read from the write address generation circuit and the fourth memory circuit. And a corner turner for rearranging the data.

4. In the Fourier transform apparatus according to claim 1,

 When the number a of pipeline FFT circuits included in the conversion means of the preceding and subsequent stages is 2,

 The first data supply means is configured to include a fourth and a fifth data reordering unit in two stages, and a fifth and a sixth memory circuit in which each data reordering unit stores data. A read or write address generation circuit according to a predetermined logic of each of the fifth and sixth memory circuits, and a corner turner for rearranging the data read from the fifth and sixth memory circuits, respectively. ,

 The second data supply means includes a sixth data rearrangement unit, and stores a seventh memory circuit for storing data, and reads or writes data according to a predetermined logic of the seventh memory circuit. Fourier characterized by comprising an address generation circuit.

5. In the Fourier transform apparatus according to claim 1,

 When the number a of pipeline FFT circuits included in the conversion means of the preceding and subsequent stages is 1,

 The first data supply means includes a seventh and an eighth data reordering unit, and the seventh data reordering unit includes an eighth memory circuit for storing data, A read or write address generation circuit according to a predetermined logic of the memory circuit, and a parallel in-serial-out circuit for rearranging the data read from the eighth memory circuit. A ninth memory circuit, each of which is composed of two banks so that M data can be alternately written and read at the time of storage and corresponding data of a corresponding M-point data set can be simultaneously read at the time of reading; A read or write address generation circuit that follows a predetermined logic of the memory circuit;

The second data supply means includes first and second banks, each of which is composed of two banks so that M data can be alternately written at the time of storage and corresponding data of a corresponding M-point data set can be simultaneously read at the time of reading. 0 memory circuit, and the 10 th memory A Fourier transform apparatus comprising a read or write address generation circuit according to a predetermined logic of the circuit.

 6. The Fourier transform devices according to any one of claims 1 to 5 are arranged in parallel in a power of 2 and the time series input data is converted into the maximum number of Fourier transform points N (= MXM ) Are assigned to each Fourier transform device, and a set of data distribution and rearrangement means is provided to supply each of the successive M-point data sets to each Fourier transform device in 2a parallel for each set, 2 sets each for 2 sets in parallel. Fourier converter.

 7. The Fourier transform apparatus according to claim 6, wherein the data distribution-parallel conversion means includes: a first memory circuit that stores data of Fourier transform apparatuses arranged in parallel; A read or write address generation circuit that follows a predetermined logic of the first memory circuit; and rearranges data read from the first memory circuit, and outputs data in parallel to each of the Fourier transform devices arranged in parallel. A Fourier transform device, comprising:

8. In the Fourier transform apparatus according to any one of claims 1 to 7,

 A Fourier transform apparatus, comprising: bypass means for bypassing the calculation by the transform means of the preceding and succeeding stages.