WO2002057909A3 - Value speculation on an assist processor to facilitate prefetching for a primary processor - Google Patents

Value speculation on an assist processor to facilitate prefetching for a primary processor

Info

Publication number
WO2002057909A3
WO2002057909A3 PCT/US2002/000643 US0200643W WO2002057909A3 WO 2002057909 A3 WO2002057909 A3 WO 2002057909A3 US 0200643 W US0200643 W US 0200643W WO 2002057909 A3 WO2002057909 A3 WO 2002057909A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
processor
executable
primary
code
system
Prior art date
Application number
PCT/US2002/000643
Other languages
French (fr)
Other versions
WO2002057909A2 (en )
Inventor
Shailender Chaudhry
Marc Tremblay
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
    • G06F9/383Operand prefetching
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
    • G06F9/383Operand prefetching
    • G06F9/3832Value prediction for operands; operand history buffers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3842Speculative instruction execution

Abstract

One embodiment of the present invention provides a system that prefetches from memory by using an assist processor that performs data speculation and that executes in advance of a primary processor. The system operates by executing executable code on the primary processor while simultaneously executing a reduced version of the executable code on the assist processor. This allows the assist processor to generate the same pattern of memory references that the primary processor generates in advance of when the primary processor generates the memory references. While executing the reduced version of the executable code, the system predicts a data value returned by a long latency operation within the executable code. The system subsequently uses the predicted data value to continue executing the reduced version of the executable code without having to wait for the long latency operation to complete.
PCT/US2002/000643 2000-05-04 2002-01-09 Value speculation on an assist processor to facilitate prefetching for a primary processor WO2002057909A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/761,360 2001-01-16
US09761360 US6772321B2 (en) 2000-05-04 2001-01-16 Method and apparatus for using an assist processor and value speculation to facilitate prefetching for a primary processor

Publications (2)

Publication Number Publication Date
WO2002057909A2 true WO2002057909A2 (en) 2002-07-25
WO2002057909A3 true true WO2002057909A3 (en) 2003-08-07

Family

ID=25061970

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/000643 WO2002057909A3 (en) 2000-05-04 2002-01-09 Value speculation on an assist processor to facilitate prefetching for a primary processor

Country Status (1)

Country Link
WO (1) WO2002057909A3 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9898445B2 (en) 2012-08-16 2018-02-20 Qualcomm Incorporated Resource prefetching via sandboxed execution
US20140053056A1 (en) * 2012-08-16 2014-02-20 Qualcomm Incorporated Pre-processing of scripts in web browsers
US20140053064A1 (en) 2012-08-16 2014-02-20 Qualcomm Incorporated Predicting the usage of document resources

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996020440A1 (en) * 1994-12-23 1996-07-04 The Victoria University Of Manchester Dual processor decoupling
US5996060A (en) * 1997-09-25 1999-11-30 Technion Research And Development Foundation Ltd. System and method for concurrent processing
WO2001052061A2 (en) * 2000-01-14 2001-07-19 Sun Microsystems, Inc. Method and apparatus for using an assist processor to pre-fetch data values for a primary processor
WO2001093029A2 (en) * 2000-05-31 2001-12-06 Sun Microsystems, Inc. Speculative program execution with value prediction

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996020440A1 (en) * 1994-12-23 1996-07-04 The Victoria University Of Manchester Dual processor decoupling
US5996060A (en) * 1997-09-25 1999-11-30 Technion Research And Development Foundation Ltd. System and method for concurrent processing
WO2001052061A2 (en) * 2000-01-14 2001-07-19 Sun Microsystems, Inc. Method and apparatus for using an assist processor to pre-fetch data values for a primary processor
WO2001093029A2 (en) * 2000-05-31 2001-12-06 Sun Microsystems, Inc. Speculative program execution with value prediction

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SAKALAY F E: "STORAGE HIERARCHY CONTROL SYSTEM", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 15, no. 4, 1 September 1972 (1972-09-01), pages 1100 - 1101, XP002002415, ISSN: 0018-8689 *
SATHE R ET AL: "AVAILABLE PARALLELISM WITH DATA VALUE PREDICTION", PROCEEDINGS. INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, XX, XX, 17 December 1998 (1998-12-17), pages 194 - 201, XP001001139 *

Also Published As

Publication number Publication date Type
WO2002057909A2 (en) 2002-07-25 application

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