WO2002045385A3 - Methods and devices for caching method frame segments in a low-power stack-based processor - Google Patents

Methods and devices for caching method frame segments in a low-power stack-based processor Download PDF

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Publication number
WO2002045385A3
WO2002045385A3 PCT/US2001/043829 US0143829W WO0245385A3 WO 2002045385 A3 WO2002045385 A3 WO 2002045385A3 US 0143829 W US0143829 W US 0143829W WO 0245385 A3 WO0245385 A3 WO 0245385A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
devices
low
based processor
frame segments
Prior art date
Application number
PCT/US2001/043829
Other languages
French (fr)
Other versions
WO2002045385A2 (en
Inventor
Michael Majid
Zohair Sahraoui
Thomas Bottomley
Guillaume Comeau
Original Assignee
Zucotto Wireless Inc
Michael Majid
Zohair Sahraoui
Thomas Bottomley
Guillaume Comeau
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zucotto Wireless Inc, Michael Majid, Zohair Sahraoui, Thomas Bottomley, Guillaume Comeau filed Critical Zucotto Wireless Inc
Priority to AU2002226968A priority Critical patent/AU2002226968A1/en
Priority to PCT/US2001/043829 priority patent/WO2002045385A2/en
Priority to AU2002241505A priority patent/AU2002241505A1/en
Priority to PCT/US2001/044031 priority patent/WO2002071211A2/en
Priority to AU2002230445A priority patent/AU2002230445A1/en
Priority to PCT/US2001/043444 priority patent/WO2002042898A2/en
Priority claimed from PCT/US2001/043957 external-priority patent/WO2002048864A2/en
Priority claimed from PCT/US2001/043444 external-priority patent/WO2002042898A2/en
Priority to AU4150502A priority patent/AU4150502A/en
Publication of WO2002045385A2 publication Critical patent/WO2002045385A2/en
Publication of WO2002045385A3 publication Critical patent/WO2002045385A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G06F9/45508—Runtime interpretation or emulation, e g. emulator loops, bytecode interpretation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44557—Code layout in executable memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4488—Object-oriented
    • G06F9/449—Object-oriented method invocation or resolution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/48—Indexing scheme relating to G06F9/48
    • G06F2209/481—Exception handling

Abstract

An apparatus and method are provided to cache local variables and stack operands of a current method frame.
PCT/US2001/043829 2000-11-20 2001-11-20 Methods and devices for caching method frame segments in a low-power stack-based processor WO2002045385A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
AU2002226968A AU2002226968A1 (en) 2000-11-20 2001-11-20 Data processor having multiple operating modes
PCT/US2001/043829 WO2002045385A2 (en) 2000-11-20 2001-11-20 Methods and devices for caching method frame segments in a low-power stack-based processor
AU2002241505A AU2002241505A1 (en) 2000-11-20 2001-11-20 Methods and devices for caching method frame segments in a low-power stack-based processor
PCT/US2001/044031 WO2002071211A2 (en) 2000-11-20 2001-11-20 Data processor having multiple operating modes
AU2002230445A AU2002230445A1 (en) 2000-11-20 2001-11-20 Interpretation loop for object oriented processor
PCT/US2001/043444 WO2002042898A2 (en) 2000-11-20 2001-11-20 Interpretation loop for object oriented processor
AU4150502A AU4150502A (en) 2000-11-20 2001-11-21 Methods and devices for caching method frame segments in a low-power stack-basedprocessor

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
US25217000P 2000-11-20 2000-11-20
US60/252,170 2000-11-20
US25655000P 2000-12-18 2000-12-18
US60/256,550 2000-12-18
US27069601P 2001-02-22 2001-02-22
US60/270,696 2001-02-22
US27637501P 2001-03-16 2001-03-16
US60/276,375 2001-03-16
US29052001P 2001-05-11 2001-05-11
US60/290,520 2001-05-11
US32302201P 2001-09-14 2001-09-14
US60/323,022 2001-09-14
US09/956,130 2001-09-20
PCT/US2001/043957 WO2002048864A2 (en) 2000-11-20 2001-11-20 System registers for an object-oriented processor
PCT/US2001/043444 WO2002042898A2 (en) 2000-11-20 2001-11-20 Interpretation loop for object oriented processor
PCT/US2001/043829 WO2002045385A2 (en) 2000-11-20 2001-11-20 Methods and devices for caching method frame segments in a low-power stack-based processor

Publications (2)

Publication Number Publication Date
WO2002045385A2 WO2002045385A2 (en) 2002-06-06
WO2002045385A3 true WO2002045385A3 (en) 2003-09-12

Family

ID=27792424

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/043829 WO2002045385A2 (en) 2000-11-20 2001-11-20 Methods and devices for caching method frame segments in a low-power stack-based processor

Country Status (1)

Country Link
WO (1) WO2002045385A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1387247A3 (en) * 2002-07-31 2007-12-12 Texas Instruments Inc. System and method to automatically stack and unstack java local variables
US9734059B2 (en) * 2012-11-21 2017-08-15 Advanced Micro Devices, Inc. Methods and apparatus for data cache way prediction based on classification as stack data
GB2518022B (en) * 2014-01-17 2015-09-23 Imagination Tech Ltd Stack saved variable value prediction

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997027539A1 (en) * 1996-01-24 1997-07-31 Sun Microsystems, Inc. Methods and apparatuses for stack caching
US6138210A (en) * 1997-06-23 2000-10-24 Sun Microsystems, Inc. Multi-stack memory architecture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997027539A1 (en) * 1996-01-24 1997-07-31 Sun Microsystems, Inc. Methods and apparatuses for stack caching
US6138210A (en) * 1997-06-23 2000-10-24 Sun Microsystems, Inc. Multi-stack memory architecture

Also Published As

Publication number Publication date
WO2002045385A2 (en) 2002-06-06

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