WO2002041339A3 - Verfahren zur herstellung ferroelektrischer kondensatoren und integrierte ferroelektrische halbleiterspeicheranordnung - Google Patents

Verfahren zur herstellung ferroelektrischer kondensatoren und integrierte ferroelektrische halbleiterspeicheranordnung Download PDF

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Publication number
WO2002041339A3
WO2002041339A3 PCT/DE2001/004248 DE0104248W WO0241339A3 WO 2002041339 A3 WO2002041339 A3 WO 2002041339A3 DE 0104248 W DE0104248 W DE 0104248W WO 0241339 A3 WO0241339 A3 WO 0241339A3
Authority
WO
WIPO (PCT)
Prior art keywords
ferroelectric
semiconductor memory
integrated
producing
memory arrangement
Prior art date
Application number
PCT/DE2001/004248
Other languages
English (en)
French (fr)
Other versions
WO2002041339A2 (de
Inventor
Zvonimir Gabric
Walter Hartner
Matthias Kroenke
Guenther Schindler
Original Assignee
Infineon Technologies Ag
Zvonimir Gabric
Walter Hartner
Matthias Kroenke
Guenther Schindler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Zvonimir Gabric, Walter Hartner, Matthias Kroenke, Guenther Schindler filed Critical Infineon Technologies Ag
Publication of WO2002041339A2 publication Critical patent/WO2002041339A2/de
Publication of WO2002041339A3 publication Critical patent/WO2002041339A3/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zur Herstellung eines ferroelektrischen Kondensators insbesondere in hochintegrierten nichtflüchtigen Halbleiterspeichern und eine integrierte ferroelektrische Halbleiterspeicheranordnung. Um eine Schädigung des Ferro- bzw. Paralektrikums (6) zu vermeiden, wird eine TaSixNy-Barriereschicht (7) über dem Kondensatormodul (1) abgeschieden. Das TaSixNy-Material besitzt Barriereeigenschaften gegenüber Wasserstoffdiffusion und Ti-Diffusion.
PCT/DE2001/004248 2000-11-14 2001-11-13 Verfahren zur herstellung ferroelektrischer kondensatoren und integrierte ferroelektrische halbleiterspeicheranordnung WO2002041339A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10056295A DE10056295A1 (de) 2000-11-14 2000-11-14 Verfahren zur Herstellung ferroelektrischer Kondensatoren
DE10056295.7 2000-11-14

Publications (2)

Publication Number Publication Date
WO2002041339A2 WO2002041339A2 (de) 2002-05-23
WO2002041339A3 true WO2002041339A3 (de) 2002-08-22

Family

ID=7663188

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/004248 WO2002041339A2 (de) 2000-11-14 2001-11-13 Verfahren zur herstellung ferroelektrischer kondensatoren und integrierte ferroelektrische halbleiterspeicheranordnung

Country Status (2)

Country Link
DE (1) DE10056295A1 (de)
WO (1) WO2002041339A2 (de)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0911871A2 (de) * 1997-10-24 1999-04-28 Sharp Kabushiki Kaisha Halbleiter-Speicherbauteil mit ferroelektrischem Dünnfilm
EP0915522A2 (de) * 1997-10-31 1999-05-12 Nec Corporation Halbleiteranordnung die eine Kapazität enthält und Verfahren zur Herstellung
JPH11233734A (ja) * 1998-02-18 1999-08-27 Sharp Corp 半導体メモリ素子及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0911871A2 (de) * 1997-10-24 1999-04-28 Sharp Kabushiki Kaisha Halbleiter-Speicherbauteil mit ferroelektrischem Dünnfilm
EP0915522A2 (de) * 1997-10-31 1999-05-12 Nec Corporation Halbleiteranordnung die eine Kapazität enthält und Verfahren zur Herstellung
JPH11233734A (ja) * 1998-02-18 1999-08-27 Sharp Corp 半導体メモリ素子及びその製造方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
HARTNER W ET AL: "INTEGRATION OF H2 BARRIERS FOR FERROELECTRIC MEMORIES BASED ON SRBI2TA2O9 (SBT)", INTEGRATED FERROELECTRICS, NEW YORK, NY, US, vol. 31, 12 March 2000 (2000-03-12), pages 273 - 284, XP001051370, ISSN: 1058-4587 *
IN SEON PARK ET AL: "Ultra-thin EBL (encapsulated barrier layer) for ferroelectric capacitor", ELECTRON DEVICES MEETING, 1997. TECHNICAL DIGEST., INTERNATIONAL WASHINGTON, DC, USA 7-10 DEC. 1997, NEW YORK, NY, USA,IEEE, US, 7 December 1997 (1997-12-07), pages 617 - 620, XP010265582, ISBN: 0-7803-4100-7 *
KUDO J ET AL: "A HIGH STABILITY ELECTRODE TECHNOLOGY FOR STACKED SRBI2TA2O9 CAPACITORS APPLICABLE TO ADVANCED FERROELECTRIC MEMORY", INTERNATIONAL ELECTRON DEVICES MEETING 1997. IEDM TECHNICAL DIGEST. WASHINGTON, DC, DEC. 7 - 10, 1997, NEW YORK, NY: IEEE, US, 7 December 1997 (1997-12-07), pages 609 - 612, XP000855870, ISBN: 0-7803-4101-5 *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 13 30 November 1999 (1999-11-30) *

Also Published As

Publication number Publication date
WO2002041339A2 (de) 2002-05-23
DE10056295A1 (de) 2002-05-23

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