WO2002037549A2 - Procede pour structurer une couche d'oxyde de silicium - Google Patents

Procede pour structurer une couche d'oxyde de silicium Download PDF

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Publication number
WO2002037549A2
WO2002037549A2 PCT/EP2001/012538 EP0112538W WO0237549A2 WO 2002037549 A2 WO2002037549 A2 WO 2002037549A2 EP 0112538 W EP0112538 W EP 0112538W WO 0237549 A2 WO0237549 A2 WO 0237549A2
Authority
WO
WIPO (PCT)
Prior art keywords
etching
mask
plasma
etching gas
silicon oxide
Prior art date
Application number
PCT/EP2001/012538
Other languages
German (de)
English (en)
Other versions
WO2002037549A3 (fr
Inventor
Matthias Goldbach
Bastian HAUSSDÖRFER
Ortrun Grahl
Original Assignee
Infineon Technologies Ag
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Applied Materials, Inc. filed Critical Infineon Technologies Ag
Publication of WO2002037549A2 publication Critical patent/WO2002037549A2/fr
Publication of WO2002037549A3 publication Critical patent/WO2002037549A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process

Definitions

  • the invention relates to a method for structuring a silicon oxide layer.
  • Silicon oxide layers serve silicon oxide layers, among other things, as insulating, passivating layers or even as hard masks. Silicon oxide layers find e.g. Application in trench isolation technology, where they are used to isolate neighboring transistors. In addition, they serve as insulation layers in multi-layer wiring or when building e.g. MOS transistors.
  • the construction of integrated semiconductor circuits thus requires the provision of suitable etching methods by means of which a silicon oxide layer which has been deposited or is generated by thermal oxidation can be structured. In particular, plasma etching processes are used as the etching process.
  • the etching process Due to the ever increasing integration density of the circuits, the etching process has to be able to realize ever smaller critical dimensions and ever higher aspect ratios.
  • structures such as contact holes, vias or hard masks with ever larger ones
  • the etching must firstly be as anisotropic as possible.
  • the etching should be as selective as possible to that of the Etching materials used as a mask, such as silicon or polymer lacquer masks. If the etching has only a low selectivity, the mask is attacked in the etching process, in particular on its profile flanks, to an extent that leads to an undesired processing of the structure specified by the mask. As a result, both the aspect ratio to be achieved and the critical dimension to be achieved are adversely affected.
  • the etching depth to be achieved is reduced by a low selectivity of the etching process, since the mask itself is removed very quickly. The improvement of the selectivity of etching processes for silicon oxide layers is therefore the subject of constant research in semiconductor technology.
  • the deposition and the etching rates are in an interplay and are different from different materials. Through a suitable choice of the process parameters, they can be set so that an effective etching can be achieved selectively for one material, whereas at the same time the deposition predominates on another material. For example, when using CF 4 in the etching gas, it is possible to set the etching parameters so that a fluorine-containing polymer is deposited on silicon and silicon nitride, whereas silicon oxide is etched by the plasma. The etching parameters can therefore be set such that the material of the layer to be structured is etched and at the same time a polymer is deposited on the material of the mask.
  • etching parameters used in these processes always represent a compromise between the protection of the mask by the polymer deposition on the one hand and the etching of the silicon oxide layer in the exposed areas on the other hand optimal etching rate for the material to be structured, still the optimal deposition rate of the polymer on the mask reached.
  • Etching process by excessive polymer deposition in structures with high aspect ratio is avoided by performing the etching process in a two-step process.
  • an etching recipe is selected with which the oxide layer is quickly but non-selectively etched.
  • a second step by changing the etching chemistry, i.e. the fluorine-containing compounds and the power coupled into the plasma reactor created more selective etching conditions.
  • this method also has the disadvantage that the increase in the selectivity of the etching process is a change in the Chemical etching.
  • the plasma is not maintained between the changes in the etching chemistry. This change therefore entails waiting times during which a steady state in the plasma has to be established again.
  • the present invention is therefore based on the object of providing a method for structuring a silicon oxide layer which reduces or completely avoids the disadvantages described above.
  • the object of the present invention is to provide a method with which structures with a high aspect ratio can be etched into a silicon oxide layer with a high selectivity in relation to the mask used.
  • a method for structuring a silicon oxide layer comprises the following steps: A substrate, which comprises a silicon oxide layer and a mask partially covering the silicon oxide layer, is provided in a plasma reactor. A plasma is generated from an etching gas which contains at least one fluorocarbon or fluorocarbon compound selected from the group consisting of compounds of
  • a first potential difference between the substrate and the plasma generated from the above-mentioned etching gas which is selected such that at least the silicon oxide layer undergoes an etching removal (process step c).
  • a second, different from the first potential difference between the substrate and the plasma generated from the above-mentioned etching gas is set, which is chosen such that a layer of a fluorine-containing polymeric material is deposited on the mask, the layer thickness of which during the second period grows. (Process step d).
  • plasma reactors that can be used for the usual chemical-physical dry etching processes can be considered as plasma reactors.
  • Such dry etching processes can e.g. reactive ion etching, anodically coupled plasma etching in the parallel plate reactor, magnetic field-supported reactive ion etching, triodes reactive ion etching, inductively coupled plasma etching or etching with an inductively coupled plasma source.
  • masks are to be understood as layers of materials which are suitable for protecting a silicon oxide layer from etching removal during plasma etching. In particular, this includes materials such as Silicon, silicon nitride or polymeric materials that are used as photolithography masks or lacquer masks. The only exception is silicon oxide itself.
  • fluorocarbon compound is to be understood as meaning both compounds which are composed only of fluorine and carbon or compounds which also contain hydrogen in addition to fluorine and carbon.
  • Such connections can be, for example.
  • C 4 F 8 is used as the fluorocarbon compound, the constitutional isomer of this compound not being important.
  • the gas flow rate of the C 4 F 8 is between 10 and 50 sccm, in particular between 20 and 50 sccm.
  • the higher gas flow rates are preferred since higher etching or deposition rates can be achieved when they are used.
  • the potential difference between the plasma and the substrate is understood to mean the potential difference that forms between the plasma envelope and the adjacent substrate.
  • This potential difference determines the energy with which the ions are accelerated from the plasma onto the substrate.
  • This potential difference can be influenced by various process parameters that can be set on the plasma reactor. As a rule, the potential difference is varied by changing the high-frequency power coupled into the plasma reactor. This power is also referred to as "bias power". Depending on the type of plasma reactor, the coupling can take place inductively and / or capacitively.
  • the first (in method step c) and the second potential difference (in method step d) between the substrate and the plasma generated from the etching gas used is set by coupling a power into the plasma reactor.
  • This power is particularly preferred. This can be done, for example, by adding power to the plasma in addition to inductively coupled power is thereby coupled in that the substrate or the electrode on which the substrate is attached is capacitively connected to a high-frequency source.
  • the sequence of process steps c) and d) is not specified in the process according to the invention.
  • the method can be designed in such a way that the SiO 2 layer is etched in a first etching step and the polymer is deposited on the mask in a subsequent deposition step. Conversely, the polymer can first be deposited on the mask and then the silicon oxide layer can be etched. In the first case, the mask is reinforced by the deposition after the etching, in the second case the mask is reinforced before the etching.
  • the first potential difference is selected in the method according to the invention in such a way that the silicon oxide layer experiences an etching removal. Only the silicon layer alone or also the mask protecting it can be etched. If both the silicon oxide layer and the mask are etched, the first period must be dimensioned so that the mask is not completely removed in any area.
  • the power which is coupled into the plasma reactor and with which the first potential difference is set during the first period is at least 400 W, preferably at least 600 W and particularly preferably at least 800 W.
  • the parameters that can be set on the plasma generator are set in this way be that the etching of the Si0 2 layer already has a high selectivity towards the mask during the first period.
  • the first potential difference is set in such a way that a layer of fluorine-containing polymer forms on the mask during the first period, the layer thickness of which remains essentially constant during the first period. That the potential difference is chosen here such that a balance is established between the etching of the mask and the deposition of the polymeric material on the mask during the first period.
  • the layer which is deposited is generally only a few nm thick.
  • the second potential difference between the substrate and the plasma generated from the etching gas is selected in the method according to the invention in such a way that a layer of a fluorine-containing polymeric material is deposited on the mask, the layer thickness of which during the second
  • the preferred power for setting the second potential difference during the second period is less than 400 W, preferably at most 200 W.
  • the deposition rate of the fluorine-containing, polymeric material on the mask is at least 50 nmmin ⁇ 1 , preferably is at least 240 nmmin "1 , in particular at least 350 nmmin " 1 .
  • the polymer layer becomes the mask against further etching protected.
  • This protective effect significantly improves the selectivity of the etching process between silicon oxide and the mask material during the second period.
  • the mask is renewed by the polymer deposition so that it can withstand a subsequent renewed etching longer. This increases the etch depth that can be achieved.
  • the change of the first potential difference to the second potential difference can e.g. by simple
  • the method according to the invention thus offers the advantage that rapid, selective etching of the silicon oxide layer can be achieved without having to make time-consuming changes to the plasma.
  • the etching chemistry of the plasma generated in the method according to the invention is crucially based on the use of a fluorocarbon compound which is suitable for depositing a fluorine-containing, polymeric material on the mask from the plasma. This component is retained in the etching gas over the entire period of the process.
  • the term “the etching gas generated in b) mentioned” is also to be understood in this sense in the context of the present invention.
  • the other etching gas components can be varied throughout the process. To increase the selectivity of the process, additional gas components can either be used during the entire process or also only be mixed in during individual steps. In particular, additional components which increase the etching rate can be added to the etching gas during method step c). In this case, the use of molecular oxygen as an additional component in the etching gas is particularly preferred.
  • the polymer deposition offers a further advantage during the second period.
  • the mask is reinforced by the deposition that takes place selectively on the mask material, so that the mask can then be exposed again to a relatively unselective etching step over a longer period of time. This is done in a particularly preferred variant of the invention
  • the duration of the first and second periods can differ from that of the first or previous cycle. Furthermore, the respective first and second potential differences can be changed in the repetition steps. This also applies to all other selectable process parameters, insofar as they can be changed without lengthy time delays.
  • the etching and deposition conditions in each step can be optimally adapted to the aspect ratios of the structure to be etched during the respective cycle , This results in a higher selectivity and a better profile control during the etching, whereby time-consuming changes in the process conditions can be dispensed with.
  • the etching gas additionally contains an inert gas, preferably argon. Its gas flow rate is preferably between 100 and 1000 sccm, particularly preferably between 200 and 700 sccm, in particular between 200 and 500 sccm.
  • the etching gas additionally contains molecular oxygen 0 2 . It is particularly preferred here that the gas flow rate of the molecular oxygen is between 5 and 25 sccm, in particular 10 sccm.
  • the etching removal in method step c) can be increased further when using molecular oxygen in the etching gas.
  • the etching gas additionally only contains molecular oxygen in method step c).
  • Fig. 1 A graph showing the dependence of the deposition rate of the fluorine-containing, polymeric material Silicon from the capacitively coupled power (bias power) for various etching gases is shown.
  • the polymer deposition from the plasma onto a silicon mask was determined as a function of the capacitively coupled power.
  • silicon wafers were placed in a plasma generator of the type IPS Dielectric Etcher from Applied Materials and exposed to a plasma.
  • the polymer deposition on the silicon wafers was then determined using scanning electron microscopy for various capacitively coupled powers.
  • the basic recipe was used in the first series of measurements and in the second In addition, molecular oxygen with a gas flow rate of 10 sccm was added to the basic recipe.
  • the measured values of the first series of measurements are represented in the graph shown in FIG. 1 by the full symbols.
  • the full circles correspond to the measured values at the edge of the silicon wafers, the full squares represent the measured values in the center of the silicon wafers.
  • the measured values of the second series of measurements are represented by the half-open symbols, the circles again representing the measured values on the edge and the squares representing the measured values in the center of the silicon wafers.
  • the deposition rate decreases with increasing capacitively coupled power and converts into an etching rate from a certain power.
  • the addition rate of molecular oxygen reduces the deposition rate.
  • the deposition rate shows only slight local deviations.
  • Embodiment 2 From these deposition rates, an optimized time can be determined, which is necessary for the deposition of a defined layer thickness.
  • an Si0 2 layer was structured with a silicon mask.
  • the Si0 2 layer already had contact holes with an approximate depth of 500 nm and an aspect ratio of about 5.
  • etching conditions were chosen such that a deposition took place on the silicon mask.
  • etching conditions were chosen so that the Si0 2 layer was etched.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

La présente invention concerne un procédé pour structurer une couche d'oxyde de silicium. Selon ce procédé, un substrat comprenant une couche d'oxyde de silicium pourvue d'un masque est placé dans un réacteur à plasma. La couche d'oxyde de silicium est exposée à un plasma qui est produit à partir d'un gaz de gravure comprenant au moins un composé fluorocarboné choisi dans le groupe des composés de formule brute CxHyFz, où x = 1 à 5, y = 0 à 4 et z = 2 à 10. Le processus peut être optimisé au moyen d'une commutation directe entre un mode de gravure et un mode de dépôt, commutation réalisée par variation de la différence de potentiel entre le substrat et le plasma.
PCT/EP2001/012538 2000-10-30 2001-10-30 Procede pour structurer une couche d'oxyde de silicium WO2002037549A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2000153780 DE10053780A1 (de) 2000-10-30 2000-10-30 Verfahren zur Strukturierung einer Siliziumoxid-Schicht
DE10053780.4 2000-10-30

Publications (2)

Publication Number Publication Date
WO2002037549A2 true WO2002037549A2 (fr) 2002-05-10
WO2002037549A3 WO2002037549A3 (fr) 2002-11-21

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WO (1) WO2002037549A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10224137A1 (de) * 2002-05-24 2003-12-04 Infineon Technologies Ag Ätzgas und Verfahren zum Trockenätzen
DE10239869A1 (de) * 2002-08-29 2004-03-18 Infineon Technologies Ag Verbesserung der dielektrischen Eigenschaften von Schichten aus High-k-Materialien durch Plasmabehandlung
DE10245671B4 (de) * 2002-09-30 2004-08-26 Infineon Technologies Ag Herstellungsverfahren für eine Halbleiterstruktur durch selektives isotropes Ätzen einer Siliziumdioxidschicht auf einer Siliziumnitridschicht

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EP0552491A1 (fr) * 1992-01-24 1993-07-28 Applied Materials, Inc. Procédé de gravure par plasma
US5882535A (en) * 1997-02-04 1999-03-16 Micron Technology, Inc. Method for forming a hole in a semiconductor device
WO2000024046A1 (fr) * 1998-10-22 2000-04-27 Tokyo Electron Limited Procede d'attaque au plasma
US6057247A (en) * 1997-10-29 2000-05-02 Matsushita Electronics Corporation Method for fabricating semiconductor device and method for controlling environment inside reaction chamber of dry etching apparatus
JP2001068462A (ja) * 1999-07-20 2001-03-16 Samsung Electronics Co Ltd 選択的ポリマー蒸着を用いたプラズマエッチング方法及びこれを用いたコンタクトホール形成方法

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US5176790A (en) * 1991-09-25 1993-01-05 Applied Materials, Inc. Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal
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US5882535A (en) * 1997-02-04 1999-03-16 Micron Technology, Inc. Method for forming a hole in a semiconductor device
US6057247A (en) * 1997-10-29 2000-05-02 Matsushita Electronics Corporation Method for fabricating semiconductor device and method for controlling environment inside reaction chamber of dry etching apparatus
WO2000024046A1 (fr) * 1998-10-22 2000-04-27 Tokyo Electron Limited Procede d'attaque au plasma
JP2001068462A (ja) * 1999-07-20 2001-03-16 Samsung Electronics Co Ltd 選択的ポリマー蒸着を用いたプラズマエッチング方法及びこれを用いたコンタクトホール形成方法

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DE10053780A1 (de) 2002-05-16
WO2002037549A3 (fr) 2002-11-21

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