WO2002037464A1

WO2002037464A1 - Microdisplay with reduced flicker

Info

Publication number: WO2002037464A1
Application number: PCT/US2001/028560
Authority: WO
Inventors: John K. Waterman
Original assignee: Three-Five Systems, Inc.
Priority date: 2000-10-30
Filing date: 2001-09-13
Publication date: 2002-05-10
Also published as: EP1337995A1; KR20030048088A; AU2001292636A1

Abstract

A method for storing video image data of a video source (528) in a buffer (520, 522), retrieving video image data from the buffer and writing data onto a display device (500), which has a plurality of pixels (510) and compromises a frame inversion driven liquid crystal material having a mean luminance and an image luminance modulation between a positive frame mode and a negative frame mode, wherein the video image data is written to the display device at a frame rate N equal to a frame rate K of the video source multiplied by a frame rate multiplier of N/K, where N/K is non-integer and N is at least as great as the Critical Fusion Frequency for the mean luminance.

Description

MICRODISPLAY WITH REDUCED FLICKER

BACKGROUND OF THE INVENTION

The present invention relates to liquid crystal display devices, more particularly, to active matrix liquid cyrstal displays.

Conventional active matrix liquid crystal display devices (AMLCDs) typically comprise a substrate having a matrix of thin-film transistors, each of which is connected to an individual transparent electrode. Each of the thin-film transistors has a gate and a drain. Gate busses are connected to the gates of the Ihin-film transistors. Drain busses are connected to the drains of the tl n-film transistors. A drain driver is connected to the drain busses to supply an analog voltage to the drain of a selected thin-film transistor, which will determine the voltage offset and therefore the gray shade of the pixel associated with the particular thin-film transistor. A gate driver is connected to the gate busses for supplying electric power cyclicly to the gate busses.

The gate driver causes the particular thin-film transistor to latch at the voltage being supplied by the drain driver, h this manner, each transparent electrode representing one picture element (pixel) is separately addressable and can be driven to a desired voltage independently of the remaining pixels in the matrix. In order to prevent degradation of the liquid crystal materials used in such displays, it is necessary to drive the displays with alternating voltage with respect to the cover glass voltage (Ncom). To prevent an average D.C. voltage build up, a pixel is charged with a certain negative voltage with respect to Ncom and then with a positive voltage of equal magnitude. The need to drive the displays with an alternating voltage, however, introduces a number of design challenges. Because of electropositiviry differences, the relative brightness of a pixel driven at a positive voltage will not be the same as a pixel driven at an equal and opposite voltage. Therefore, if the entire frame is driven first at a positive voltage and then at a negative voltage (known as frame inversion) the entire display will exhibit a noticeable flicker as the intensity of the display varies from the positive to the negative inversion state. Several methods have been suggested for reducing flicker in active matrix liquid crystal displays. It has been suggested that a flicker free frame mode inversion could be achieved if, instead of driving the liquid crystal display at equal and opposite voltages in a frame inversion mode, the negative voltages are adjusted to compensate for the asymmetry of the gray scale response of the cell to voltage. This method is known as asymmetrical frame inversion. Unfortunately, asymmetrical frame inversion still produces a D.C. voltage component that is non-zero, and, therefore, over time, the D.C. component of the driving voltage will degrade the liquid crystal material. A second method, which has been employed successfully in large direct view active matrix liquid crystal displays is to interlace positive and negative pixels in a single frame. According to this method, known as interlacing or frame "averaging", during the first frame, each pixel is driven to its appropriate gray shade voltage with a voltage of opposite polarity to the voltage of each adjacent pixel, h the next frame cycle, the voltages are reversed such that the formerly negative pixel is driven at a positive voltage and the formerly positive pixel is driven at a negative voltage. Although each individual frame is flickering due to the asymmetry of the liquid crystal gray scale response to voltage, the average of the frame does not flicker perceptively. hi a conventional AMLCD a sizable portion of each pixel is taken up by the thin-film transistor elements. Since the size of the transistor element is fixed irrespective of the pixel size, the presence of the transistor elements inhibits the ability to miniaturize AMLCDs beyond a certain point. Liquid crystal on silicon (LCOS) displays show great promise for use as high performance nήcrominiature display elements suitable for use in virtual image displays, projectors, and other display applications where extremely fine resolution is necessary. Because the resolution of an LCOS microdisplay is so much greater than that of a conventional AMLCD

(on the order of 1,000 dots per inch "dpi" or more) interlacing to reduce flicker is not practical

because of the fringing fields between adjacent pixels. Utilizing frame inversion to drive an

LCOS microdisplay causes the characters to flicker in an LCOS microdisplay just as it does in a

5 conventional AMLCD display. Accordingly, what is needed is a high resolution LCOS

microdisplay capable of producing a substantially flicker free image without fringing.

SUMMARY OF THE INVENTION

The present invention comprises a method of storing and retrieving video data and

[ 0 writing it to a display device in a frame inversion mode in which the display frame refresh rate is

optimized to produce a substantially flicker free image while maximizing the slew and settle

time for the liquid crystal material. This is accomplished by writing to the display device at a rate that is above the Critical Fusion Frequency for the mean luminance of the display

independent of the frame rate of the video signal being received. In this way, a flicker free

L5 image of maximum contrast can be obtained for a given liquid crystal design. According to an

illustrative embodiment of the invention, video data is received from a video source at a particular frame rate, such as 60 frames per second (a video rate common in the industry for

video games and other computer graphics applications). The video data is written to a video

buffer as it is received. The video data is then read out of the video buffer and written to the

10 display device at a display rate slightly above the Critical Fusion Frequency for display based on

the mean luminance and modulation of the display, irrespective of the mcoming video frame

rate. In an illustrative embodiment, where the luminance modulation of the display is 20% and the mean luminance is somewhat over 10,000 Trolands (Td), the frame refresh rate is optimized

at 100 Hz and therefore, for a 60 Hz video frame rate, five display frames are written for every three video frames. Because the display frame rate is not an integer multiple of the video frame rate, every third video frame is skipped with one of the remaining two video frames written twice and the other written three times to produce the 100 Hz display frame rate. To the observer, the image appears to have one frame displayed for 20 milliseconds (a 50 Hz apparent video frame rate) one frame displayed for 30 milliseconds (a 33.3 Hz apparent frame rate) followed by the action skipping forward 16.7 milliseconds (a 60 Hz apparent video frame rate) to display the next two frames again at the 50 Hz and 33.3 Hz apparent video frame rate. Since the 33.3 Hz and 50 Hz apparent video frame rates of the displayed frames as well as the 60 Hz apparent video frame rate of the skipped frame are well above the conventional movie frame rate of 24 Hz, the change in apparent video frame rate as well as the skipped frame are undetectable to the human observer.

BRIEF DESCRIPTION OF THE DRAWING

The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures in which like references designate like elements and, in which:

FIG. 1 is a partial schematic plan view of a prior art active matrix liquid crystal display;

FIG. 2 is a prior art active matrix liquid crystal display driven in an interlaced mode during a first time frame;

FIG. 3 is the display of FIG. 2 in a second time frame;

FIG. 4 is a graphical representation of the temporal modulation transfer function showing the Critical Fusion Frequency versus luminance modulation for displays having various average luminances; and FIG. 5 is a partial schematic representation of a display incorporating features of the present invention.

DETAILED DESCRIPTION

The drawing figures are intended to illustrate the general manner of construction and

are not necessarily to scale. In the description and in the claims the terms left, right, front and back and the like are used for descriptive purposes. However, it is understood that the

embodiment of the invention described herein is capable of operating in other orientations and

is shown in the terms so used are only for the purpose of describing relative positions and are interchangeable under appropriate circumstances.

FIG. 1 is a partial schematic representation of a conventional active matrix liquid

crystal display (AMLCD). The display 10 comprises a matrix of thin film transistors 12, each

connected to an individual picture element (pixel) electrode 14. Each transistor 12 has a gate

16 and a drain 18 connected respectively to one of a plurality of gate lines 22A-C and drain lines 20A-D. Each of drain lines 20A-D is connected to one of a plurality of digital analog

converters (DACs) 24A-D which convert a digital signal into an analog voltage along the

respective drain lines 20A-D. Conventionally, each electrode 14 is separably addressable to

be latched into a particular voltage by placing the appropriate voltage along the appropriate drain line such as drain line 20A by DAC 24A and latching the voltage by strobing the

appropriate gate line such as gate line 22C. A capacitor (not shown) connected to thin film

transistor 12 maintains the voltage on electrode 14. A transparent electrode 30 covering the

entire matrix of electrodes 14 is positioned a precise distance away from the array of electrodes 14 and a liquid crystal material sandwiched therebetween. The differential voltage necessary to drive the liquid crystal material is produced by maintaining the transparent electrode 30 at a fixed voltage (Ncom) while varying the voltage on the respective electrodes 14.

As is well known in the art, liquid crystal materials are capable of producing a

variation in shading as a function of voltage. The greater the voltage difference across the

5 pixel, the greater the relative darkness or lightness of that pixel. It is also well known that

these liquid crystal materials must be driven at an alternating voltage having a net D.C.

component of zero in order to prevent degradation of the liquid crystal material. One solution

to the need to drive the liquid crystal material at an alternating voltage is known as frame

inversion. In frame inversion mode, during the first frame period, all of the pixels 14 of

.0 display 10 are driven at a positive voltage relative to Ncom. During the second frame period

all of the pixels of display device 10 are driven at a negative voltage relative to Ncom. During

the third frame period positive; and the fourth frame period negative, and so on. However,

with conventional liquid crystal materials, the transmissivity of the liquid crystal material

when driven at a positive voltage is not identical to the transmissivity when driven at an equal

L5 negative voltage. For many materials, the transmissivity difference is 15% or more. The

human eye is not particularly sensitive to flicker where the image intensity does not vary from

frame to frame. This is why in a movie theatre where the frame rate is only 24 frames per

second, but the images are projected from a light source that does not change in intensity from

frame to frame, the audience does not notice the image flickering. Unfortunately, a 15%

.0 luminance variation from frame to frame is highly noticeable and will cause eye fatigue even

at conventional computer video frame rates of 60 frames per second.

One method of reducing perceptible flicker in AMLCDs that has had some

commercial success is known as interlacing. As shown in Fig. 2, in an interlaced display 200, each pixel 210 is driven at the inverse voltage of each adjacent pixel during the first frame sequence of the display. As shown in Fig. 3, during the second frame sequence, the polarity of the pixels is reversed, h an interlaced display, although each pixel is flickering at up to 15% or more in intensity, the pixels are small enough that the flickering of the individual pixels is not discemable to the human eye. Because only half of the pixels at any one time are brighter, while the other half darker and vice versa, the average luminance of the display does not change. Therefore to the human eye, the display does not appear to flicker. The disadvantage of an interlaced display is that since adjacent pixels are driven at opposite voltages, a substantial electric field exists between the adjacent pixels, which is not present in a frame inversion type display. The electric field between the adjacent pixels causes fringing (the darkening of a portion of a light pixel caused by a dark adjacent pixel) which reduces the image fidelity of the display. In large AMLCDs which have resolutions of on the order of 100 dpi and up to 10 microns or more between pixels, the effects of fringing are generally negligible, however, in microdisplays such as LCOS displays, where the resolution is on the order of 1,000 dpi or more, the effects of fringing are quite noticeable. For a 2,000 dpi microdisplay having 12 micron pixels with a one micron gap between pixels, a black pixel will fringe into the white pixel by almost 20%. Accordingly, microdisplays using conventional liquid crystal materials must be driven in a frame inversion mode and therefore will flicker to some extent.

It has been suggested that if the frame refresh rate of a frame inversion driven display is sufficiently fast, although the display will be flickering, at a certain point the flicker will become so fast the image will appear to be nonflickering, or "fused" to the human eye. Fig. 4 is a graphical representation of the temporal modulation transfer function for a display device showing the Critical Fusion Frequency 400 (also known as Flicker Fusion Frequency or Critical Flicker Frequency) as a function of luminance modulation percentage 410 for a selection of displays having average luminance of .375 Td to 10,000 Td (Fig. 4 is adapted

herein by reference). As shown in Fig. 4, as expected, the Critical Fusion Frequency

decreases as the magnitude of the luminance modulation decreases. Also as shown in Fig. 4,

Critical Fusion Frequency increases as the average luminance of the display increases. For

example, the plot 428 of a display having an average luminance of 10,000 Td exhibits a

Critical Fusion Frequency of about 55 Hz at a luminance modulation of 100%> decreasing to about 10 Hz at 0.5% luminance modulation. A display having a flicker frequency greater than

the Critical Fusion Frequency will appear to the user as being fused. Accordingly, in an

illustrative example, a display having an average luminance of 10,000 Td and an intensity

modulation of 20% (shown as Reference 430 in Fig. 4) will appear fused because for a display

having an average luminance of 10,000 Td and a luminance modulation of 20%, the critical fusion frequency shown as Reference 432 on Fig. 4, is about 43 Hz. (Note that a flicker

frequency of 45 Hz as shown in Fig. 4 represents one complete cycle of positive and negative

luminance. Accordingly, the flicker frequency of 45 Hz as shown in Fig. 4 would correspond to a display frame rate of 90 Hz since display frame rate counts each positive and negative frame separately).

One potential solution to increasing the display frame rate would be simply to write

each frame of video data twice thereby doubling the 60 Hz video frame rate to 120 Hz (frame

doubling). Although this would produce a fused image for a 10,000 Td display, a 120 Hz

display frame rate is faster than necessary to produce a fused image and therefore achieves a

fused image at the cost of rendering optimization of display for slew and settle of the liquid crystal impossible. The inability to optimize the display for slew and settle time degrades the

contrast ratio of the display. Frame doubling also places unnecessary design constraints on the speed of the buffers, DACs and other system components. It was determined by the

inventor of the present invention that in order to optimize a liquid crystal display to produce both a flicker free image and to maximize contrast, the frame refresh rate would have to be

implemented independent of the video frame rate.

Fig. 5 is a partial schematic of a driver circuit and microdisplay in which the

microdisplay frame refresh rate is independent of the incoming video frame rate in accordance

with the present invention. Microdisplay 500 comprises an array of pixels 510 each having a transistor (not shown) having a gate (not shown) connected to an appropriate one of gate lines

512A-C and a drain connected to an appropriate one of drain lines 514A-D. Each of drain

lines 514A-D is connected to a digital to analog converter (DACs) 516A-D. Each of DACs

516A-D are connected to video storage buffers 520 and 522. A frame refresh clock 524 determines the rate "N" at which the video image data will be written to display 500 (the display frame rate or display refresh rate). A video clock 526 determines the rate "K" at

which video data is written from video source 528 to input buffers 520 and 522. A controller

530 determines which of video storage buffers 520 and 522 the video data from video source

528 will be written.

In operation, although video data is received into video storage buffers 520 and 522 at

a clock rate "K", the same video data is written to microdisplay 500 at a frame rate equal to ^

multiplied by the video frame rate K, such that the frame refresh rate N is optimized for

maximizing the slew and settle time of microdisplay 500. Since the frame rate multiplier ?

is not necessarily an integer, provisions must be made to accommodate the difference between the frame refresh rate and the video frame rate. In the illustrative embodiment, the frame rate

multiplier ^ is reduced to its least common denominator to produce a frame mode multiplier . The video data is then written to microdisplay 500 "J" times with the "Lth" frame of video

data skipped.

For example, where the video frame rate is 60 Hz and the optimum frame refresh rate is

100 Hz, the frame rate multiplier is ^ . The frame mode multiplier in its least common

form is equal to f , thus "J" is set to 5 and L is set to 3. According to the present invention,

therefore, video data is written to microdisplay 500 J = 5 times, typically with either the first frame of video data written twice and the second frame of video data written three times or the

first frame of video data written three times with the second frame of video data written twice.

The L = 3 third frame of video data is then skipped, and the cycle is repeated with the next two

frames of video data written five times and the following third frame of video data skipped. As noted hereinbefore, to the observer, the image appears to have one frame displayed for 20

milliseconds each (a 50 Hz apparent video frame rate) one frame displayed for 30 milliseconds

(a 33.3 Hz apparent frame rate) followed by the action skipping forward 16.7 milliseconds (a 60

Hz apparent video frame rate) to display the next two frames again at the 50 Hz and 33.3 Hz

apparent video frame rate. Since the 33.3 Hz and 50 Hz apparent video frame rates of the displayed frames as well as the 60 Hz apparent video frame rate of the skipped frame are well

above the conventional movie frame rate of 24 Hz, the change in apparent video frame rate as

well as the skipped frame are undetectable to the human observer.

h a second illustrative example, for a display having an average luminance of 10,000

Td and a luminance modulation of 8%, when video data is received at 60 Hz the optimum

display frame rate is 80 Hz, the frame rate multiplier - is equal to ϋ . The frame mode

multiplier is therefore equal to . Accordingly, video data is written to microdisplay 500 J

= 4 times. The writing of the four frames can be accomplished by writing the first video

frame once and the second video frame three times, the first video frame three times and the second video frame once, or preferably the first video frame twice and the second video frame

twice. The L = 3 third frame of video is skipped and the cycle is repeated.

As can be deteπnined from the foregoing, by implementing a driver circuit that writes

the video data to the microdisplay at - - times the video rate, the microdisplay can be

optimized for maximum slew and settle time independent of the frame rate of the video data

to be displayed, hi this way, a flicker free display having the maximum possible contrast can

be realized.

Although certain preferred embodiments and methods have been disclosed herein, it

will be apparent from the foregoing disclosure to those skilled in the art that variations and

modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. Accordingly, it is intended that the invention shall be

limited only to the extent required by the appended claims and the rules and principles of applicable law.

Claims

The claims are:

1. A method of storing and retrieving visual data and writing said data onto a display

device having a plurality of image pixels, said display device comprising a frame inversion

driven liquid crystal material having a mean luminance and an image luminance modulation

between a positive frame mode and a negative frame mode, the method comprising: receiving video image data from a video source at a frame rate having a value of K

frames per second;

storing said video image data in a buffer;

reading said video image data from said buffer; and writing said video image data to said display device, said image data being written to

said display device at a frame rate N equal to said K frames per second multiplied by a frame

rate multiplier of N/K where N/K is non-integer and N is at least as great as the Critical

Fusion Frequency for said mean luminance.

2. The method of claim 1 , wherein said refresh rate multiplier N/K is less than 2.

3. The method of claim 1 , wherein said luminance modulation between said positive

frame mode and said negative frame mode is between 15 and 20 percent and N is greater than

90 frames per second and less than 120 frames per second.

4. The method of claim 3, wherein N is equal to 100 frames per second.

5. The method of claim 1 , wherein; said video image data from the video source is digital data representing a gray scale for each pixel of said display device;

12

819531 and said video image data is converted into analog voltage levels before writing to display device.

6. The method of claim 1 , wherein a reduced frame mode multiplier J/L is equal to N/K

reduced to its least common denominator, the method further comprising:

writing video data to said display device J times; and

after writing to said display device J times, skipping the Lth frame of video data.

7. The method of claim 6, wherein:

J/L is equal to 4/3;

a first frame of video data is written to said display device twice;

a second frame of video data is written to said display device twice; and a third frame of video data is skipped.

8. The method of claim 6, wherein: J/L is equal to 5/3;

a first frame of video data is written to said display device twice;

a second frame of video data is written to said display device thrice; and

a third frame of video data is skipped.

9. The method of claim 6, wherein:

J/L is equal to 5/3;

a first frame of video data is written to said display device thrice; a second frame of video data is written to said display device twice; and a third frame of video data is skipped.