WO2002023340A1  Optimized ram representation of convolutional interleaver/deinterleaver data structure  Google Patents
Optimized ram representation of convolutional interleaver/deinterleaver data structure Download PDFInfo
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 WO2002023340A1 WO2002023340A1 PCT/US2001/041922 US0141922W WO0223340A1 WO 2002023340 A1 WO2002023340 A1 WO 2002023340A1 US 0141922 W US0141922 W US 0141922W WO 0223340 A1 WO0223340 A1 WO 0223340A1
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 interleaver
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 pointer
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 modulo
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 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
 H03M13/2732—Convolutional interleaver; Interleavers using shiftregisters or delay lines like, e.g. Ramsey type interleaver
Abstract
Description
Description
OPTIMIZED RAM REPRESENTATION OF CONVOLUTIONA INTER EAVER/DEINTER EAVER DATA STRUCTURE
TECHNICAL FIELD
This invention relates to the art of electronic data transmission, and more specifically, to a method and apparatus for convolutional interleaving and deinter leaving of data for correcting bursts of errors in transmitted data.
BACKGROUND ART
Error correction and error detection codes have been used extensively in data communication and data storage applications. In a data communication application, data is encoded prior to transmission, and decoded at the receiver. In a data storage application, data is encoded when stored in a storage device, e.g. in a disk drive, and decoded when retrieved from the storage device. The principles discussed herein are equally applicable to a data communication system and to a data storageretrieval system, although the remainder of this description deals with a data communication application. In a typical application of error detection and correction codes, data symbols are stored in blocks, wherein each block of data symbols includes a selected number of special symbols, called check symbols. A symbol may consist of a single bit or multiple bits . The check symbols in each block represent redundant information concerning the data stored in the block. When decoding the blocks of data, the check symbols are used to detect both the presence and the locations of errors and, in some instances, to correct these errors. The theory and applications of error correction codes are wellknown to those skilled in the art. For reference, please see "Error Control Coding: Fundamentals and Applications", by Shu Lin and Daniel J. Costello, Jr., PrenticeHall, 1983. In a typical application of error correction codes, the input data is divided into fixedlength blocks ("code words") . For a linear block (n, k) code, each code word consists of n symbols, of which a fixed number k are data symbols, and the remaining (nk) symbols are check symbols. The linear block code can be defined in terms of generator and paritycheck matrices. As mentioned above, the check symbols represent redundant information about the code word and can be used to provide error correction and detection capabilities. Each data or check symbol of such a code word can be represented by a coefficient of a polynomial of order (n1) . For the linear error correcting and detecting (n, k) code, the check symbols are the coefficients of the remainder poly nomial generated by dividing the order (n1) polynomial by an order (nk) "generator" polynomial over a Galois field. For an order (n1) polynomial divided by an order (nk) polynomial, the remainder polynomial is of order (nk1) . The construction and basic properties of Galois field can be found in "Error Control Coding: Fundamentals and Applications", by Shu Lin and Daniel J. Costello, Jr., PrenticeHall, 1983.
The decoding of linear block codes is based on a set of "syndromes" computed from a remainder polyno mial. The set of "syndromes" is obtained by dividing the code word by the generator polynomial. Ideally, if no error is encountered during the decoding process, all computed syndromes are zero. A nonzero syndrome indicates that one or more errors exist in the code word. Depending on the nature of the generator polynomial, the encountered error may or may not be correctable. If the generator polynomial can be factorized, a syndrome computed from the remainder polynomial obtained by dividing the received code word by one of the factors of the gen erator polynomial is called a "partial syndrome".
One can view the code words as occupying the vertices of a cube in an ndimensional space. Choosing a good set of code words for a code consists of choosing a set of vertices which have good distance properties in the ndimensional space. The probability of error between two blocks of binary digits is reduced by increasing the Hamming distance between the code words, which is defined as the number of symbol positions at which two code words differ. In such an error correction code, two code words differ by a distance of one, if they differ at one symbol position, regardless of the number of bit positions these code words differ within the correspond ing symbols at that symbol position.
The capability of an error correction or detection code is sometimes characterized by the size of the maximum error burst the code can correct or detect . For example, a convenient capability measure is the "single error burst correction" capability, which characterizes the code by the maximum length of consecutive error bits the code can correct, as measured from the first error bit to the last error bit, if a single burst of error occurs within a code word. Another example of a capabil ity measure would be the "double error burst detection" capability, which characterizes the error correction or error detection code by the maximum length of each error burst the error correction code can detect, given that two or less bursts of error occur within a code word. Because errors often occur in bursts in some types of channels (for instance, in the Rayleigh fading channel), a technique, called "interleaving", is often used to spread the consecutive error bits or symbols into different "interleaves", which can each be corrected individually. Interleaving is achieved by creating a code word of length nw from w code words of length n. In one method for forming the new code word, the first w symbols of the new code word are provided by the first symbols of the w code words taken in a predetermined order. In the same predetermined order, the next symbol in each of the w code words is selected to be the next symbol in the new code word. This process is repeated until the last symbol of each of the w code words is selected in the predetermined order into the new code word. Another method to create a wway interleaved code is to replace a generator polynomial G(X) of an (n, k) code by the generator polynomial G(X^{W}). This technique is applicable, for example to the ReedSolomon codes. Using this new generator polynomial G(X^{W}), the resulting (nw, kw) code has the error correcting and detecting capability of the original (n, k) code in each of the w interleaves so formed. There are two basic types of prior art interleavers : a block interleaver and a convolutional interleaver. The block interleaver has a rectangular configuration and is represented by a matrix having N number of columns and M number of rows, that is the block interleaver includes two interleaving parameters: (N, M) . The input data in written into the block interleaver by column , and is read out by row. On the receiving end, after the data is transmitted over a channel generating bursts of errors, the block deinterleaver writes the received data by row, and reads the data out by column, thus randomly spreading the bursts of errors in time.
A convolutional prior art interleaver has two interleaving parameters: a number of branches L, and a delay D: (L, D) . The first branch of the convolutional interleaver includes a minimum delay zero, wherein the last Lth branch includes the maximum delay: (Ll)D. A convolutional deinterleaver includes the matching parameters: the L number of branches, and the same D delay. However, the last Lth branch of the convolutional de interleaver includes a minimum delay zero, wherein the first branch includes the maximum delay: (Ll)D. For a digital video broadcast channel (DVB channel) , the parameters of the convolutional interleaver are such: there are L = 12 branches, and the delay D =17. The prior art implementation of a convolutional interleaver for a digital video broadcast channel (DVB channel) is a RAM with an addition of a READ/WRITE signal. The prior art implementation of a convolutional interleaver (deinterleaver) for the digital video broadcast channel (DVB channel) is a relatively expensive and ineffective one because it utilizes only about 50% of RAM thus leaving a lot of unused space on an Application
Specific Integrated Circuit (ASIC) chip. In addition, the prior art implementation of a convolutional interleaver (deinterleaver) for the digital video broadcast channel (DVB) channel utilizes too much circuitry to generate the RAM addresses (for example, it takes about 6 gates to implement a single register) .
What is needed is to optimize the architecture of RAM that is used for implementation of the convolutional interleaver (deinterleaver) that (1) does not leave unused space on the ASIC, and (2) significantly reduces the amount of circuitry required to generate the RAM addresses.
SUMMARY OF THE INVENTION To address the shortcomings of the available art, the present invention provides an optimized convolutional interleaver (deinterleaver) for DVB channel that includes an efficiently organized RAM memory that does not leave unused space in the Application Spe cific Integration Circuit (ASIC) , and that reduces the amount of circuitry required for RAM addresses generation.
One aspect of the present invention is directed to a system for data transmission comprising: (a) an interleaver configured to interleave an original data stream by at least one interleaving parameter so that the original data stream is divided in a plurality of data blocks, each of the data blocks comprising a plurality of data units; and (b) a deinterleaver configured to re cover the original data stream by use of at least one interleaving parameter.
In one embodiment, the interleaver further includes an interleaver memory unit configured for writ ing and reading the plurality of data units into a plurality of the interleaver memory locations identified by a single interleaver pointer and an interleaver pointer generator. The interleaver pointer generator is config ured to generate the interleaver pointer during the interleaving procedure, wherein the interleaver pointer generator is cyclically modulo modifying the interleaver pointer up (or down) to (or from) an interleaver modulo value . In one embodiment, the deinterleaver further comprises a deinterleaver memory unit configured for writing and reading the plurality of data units into a plurality of the deinterleaver memory locations identified by a single deinterleaver pointer and a de interleaver pointer generator. The deinterleaver pointer generator is configured to generate the deinterleaver pointer during the deinterleaving procedure, wherein the deinterleaver pointer generator is cyclically modulo modifying the deinterleaver pointer up (or down) to (or from) a deinterleaver modulo value. The interleaver pointer generator and the deinterleaver pointer generator are synchronized.
In one embodiment, the interleaver memory unit further comprises a plurality of interleaver branches, wherein the interleaver branch further comprises a plurality of interleaver blocks, and wherein the interleaver block further includes a plurality of interleaver addresses . The deinterleaver memory unit further comprises a plurality of deinterleaver branches, wherein the deinterleaver branch further comprises a plurality of deinterleaver blocks, and wherein the deinterleaver block further includes a plurality of deinterleaver addresses. The interleaver memory unit and the de interleaver memory unit can be implemented using: a RAM memory unit, a hard drive memory unit, or an external memory unit. In one embodiment, the interleaver memory unit further includes an interleaver algorithmic encryption means configured to encrypt the transmitted data by selecting at which points the interleaver pointer takes value, and the deinterleaver memory unit further includes a deinterleaver algorithmic decryption means configured to decrypt the received data by selecting select at which points the deinterleaver pointer takes value . In one embodiment, the present invention includes system for data transmission comprising: (a) a convolutional interleaver configured to interleave an original data stream so that the original data stream is divided in a plurality of data blocks, and (b) a convolutional deinterleaver configured to recover the original data stream. In the preferred embodiment, the convolutional interleaver includes two interleaving parameters : a number of interleaver branches and an interleaver delay. In one embodiment, the number of interleaver branches N is equal to 12, and the interleaver delay D is equal to 17 time units.
Another aspect of the present invention is directed to a method for data transmission comprising the steps of: (a) using an interleaver to communicate with a channel; (b) interleaving an original data stream by at least one interleaving parameter so that the original data stream is divided in a plurality of data blocks, wherein each data block comprises a plurality of data units; (c) using a deinterleaver to communicate with the channel; (d) using the deinterleaver to recover the original data stream by using at least one interleaving parameter; and (e) synchronizing the interleaver pointer generator and the deinterleaver pointer generator.
In one embodiment, the step (a) of interleaving the original data stream by at least one interleaving parameter further includes the step (al) of configuring an interleaver memory unit for writing and reading the plurality of data units into a plurality of the
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In one embodiment of the present invention, the step (b) of encrypting the original data stream by interleaving the original data stream by at least one interleaving parameter further includes the steps of: (bl) configuring an interleaver memory unit for writing and reading the plurality of data units into a plurality of the interleaver memory locations identified by a single interleaver pointer and an interleaver pointer generator; (b2) generating the interleaver pointer during the inter leaving procedure by using the interleaver pointer generator; (b3) cyclically modulo modifying the interleaver pointer up (or down) to (or from) an interleaver modulo value by using the interleaver pointer; and (b4) selecting an algorithm that determines at which points the interleaver pointer takes value.
BRIEF DESCRIPTION OF THE DRAWINGS
The aforementioned advantages of the present invention as well as additional advantages thereof will be more clearly understood hereinafter as a result of a detailed description of a preferred embodiment of the invention when taken in conjunction with the following drawings .
FIG. 1 shows a prior art general bit interleaver device that groups input into kl blocks of k2 bits.
FIG. 2 depicts a prior art interleaving process, wherein an original data stream and an interleaved data stream are shown in reference to index axes. FIG. 3 illustrates a prior art specific interleaver that comprises a number of (Jl) delay lines, a write switch, and a read switch.
FIG. 4 shows a simplified block diagram of a prior art data transmission system comprising interleaver, communication channel, and deinterleaver.
FIG. 5 illustrates a simplified prior art block diagram of interleaver /deinterleaver of FIG. 4. FIG. 6 depicts a conceptual diagram of the prior art data transmission system comprising a convolutional digital video broadcast channel (DVB channel) interleaver, a convolutional DVB deinterleaver, and a bursty communication channel .
FIG. 7A illustrates a RAM representation of interleaver data structure of the present invention.
FIG. 7B depicts how two parameters are used to address a particular location in the RAM data structure of the present invention: (a) the current step value as the index of the 17byte segment presently used by the row, and (b) the block counter value that counts from 0 to 16 and represents how many bytes into a given segment the pointer is. FIG. 8 is a flow chart of the method of the present invention for data transmission using an interleaver to spread out the bursts of errors caused by a bursty error channel.
FIG. 9 depicts a flow chart of the method of the present invention for using a deinterleaver to recover the original data stream transmitted over a bursty error channel .
BEST MODE FOR CARRYING OUT THE INVENTION As was stated above, in a number of data transmission systems (for instance, a data transmission system that utilizes a Rayleigh fading channel) , the errors occur in bursts rather than at random. In a bursterror situation the occurrence of a bit in error means that the likelihood of the next bit being also in error is increased. A rare burst of errors can cause output errors even though the overall probability of bit error is low. This stands in contrast to random errors, which are independent of one another and are modeled by the Binary Symmetric Channel (BSC) . The prior art bit interleaver device 10 that causes the burst errors to be randomized over a sequence is shown in FIG. 1 (according to "Data Communications Principles" by Richard D. Gitlin, Jeremiah F. Hayes, and Stephen B. Weinstein, published by Plenum Press, in New York, in 1992) .
Suppose, for example, that data is segmented in kl successive blocks each including k2 bits. This is a block interleaver having interleaving parameters (Nl,
N2 ) , wherein Nl = kl , and N2 = k2. The drawback to the interleaving method is delay. Indeed, up to kl *k2 bits should be buffered at the transmitter side of the communication channel before transmission. The maximum permis sible delay depends on the type of information to be transmitted. The integrity constraints of computer data transmission are at least three orders of magnitude higher than those of digital speech transmission. However, the data channels can accept longer interleaving delays which allows effective randomization of the bursty error statistics of a channel generating bursts of errors, thus increasing the ability of the forward error correction (FEC) decoder to decrease the bit error rate (BER) . There is a minimum interleaving delay to trans form the BER statistics of a channel generating bursts of errors (for instance, the Rayleigh fading channel) into a good approximation of those BER encountered in a Gaussian channel .
The general principle of convolutional interleaving/deinterleaving method using pointer incrementing is described in U. S. Patent No. 6,014,761, incorporated in the present patent application in its entirety.
According to 761 patent, FIG. 2 depicts a prior art interleaving process, by the way of example 100, wherein an original data stream 110 and an interleaved data stream 120 are shown in reference to index axes 105 and 105'. The original data stream 110, also {ORIGINAL_DATA_STREAM} , comprises a first plurality of code blocks 140146, with a block index increasing from b=0 to b=B=6. The "length" of the block is defined as a number of data units in each block. Each code block 140146 {ORIGINAL_BLOCK b} has a length J =3 of data units 112. Each data unit in each block is assigned a pair of index coordinates (b, j), wherein unit index j goes cyclically from j = 0 to j =J  1=2.
An original data unit 112, which can be written in the following notation: {ORIGINAL_DATA_UNIT [ (b, j)
=(0, 0)]} = [(X (b, j)= X(0,0)] includes, preferably, one byte of information. For convenience, index axis 105 counts data units 112 (also, X (i) ) inside {ORIGINAL_DATA_STREAM} 110 by index pair (b, j), and by single index i. Index i starts from i=0. Index i which is assumed to be indefinite is only limited here by the size of {ORIGINAL_DATA_STREAM} 110 measured in bytes. As depicted in FIG. 2, index i runs from 0 to Ml=20 Counting with single index i and double index (b, j) is equiv alent. For example: X (0)=X (0,0), X (1)=X (0,1), X (2)=X (0,2), X (3)=X (1,0), and so on. In general, indices i, b, and j are related by
b=integer (i/J) ; and (1)
j=mod_{j}(i/J); (2)
wherein the slash "/" stands for division, "integer" for the nonbroken result and "mod" for modulo operation to the base J.
Index i can be calculated from (b,j) according to:
i=b*J+ j (3)
Interleaved data stream
{INTERLEAVED_DATA_STREAM} 120 comprises a second plurality of code blocks 150156, as shown in FIG. 2 with a primed block index b'=0 to B'=6. Each code block 150156 { INTERLEAVED_BLOCK b' } has a length of J'=J, wherein the length J' is the number of interleaved data units 113 inside each {INTERLEAVED_BLOCK b'}. Similarly, index axis 105' counts data units 113 in data stream 120 with single index i' and double index (b',j'). Equations (1), (2) and (3) are applicable in the same way. Data units Y (i') = Y (b, j') 113 of interleaved data stream 120 have single index i' numbers in a new order obtained by interleaving. Inside interleaved data stream 120, unspecified data units 123 identified with e.g., Z1Z6, preferably, do not come from original data stream 110. Data units X (i)=X (b, j) of original data stream 610 are interleaved to a depth (Dl) =6, and become data units Y (i')=Y (b, j') of interleaved data stream 120. Here, deinterleaver parameter D is the number of blocks in the { INTERLEAVED_DATA_STREAM} 120. Therefore, indices i and i' of X (i)=Y (i') are related by a difference d (j) :
i'=i+ d (j) ; (4)
and
d(j)=j*(Dl); (5)
wherein (*) stands for multiplication, d (j) is commonly referred to as "Delay". For example, d (j) is a time shift required in a prior art interleaving/ deinterleaving application.
Double indices of X (b, j ) =Y (b, j') are also related by
b'=b+ d(j) ; (6)
:^{'}=:; (7)
wherein d ( j ) =j * (D l ) ( 8 )
EXAMPLE 1
The following data units go from original data stream 110 to interleaved data stream 120 without delay:
X (0)=X (0,0)=0,
X (3)=X (1,0)=3
X (6)=X (2,0)=6; X (9)=X (3,0)=9,
X (12)=X (4,0)=12;
X (15) =X (5,0) =15; and
X (18) = X(6,0) =18.
Here b is incrementing, j=0, and delay (d(0)=0, as indicated e.g., by line 170.
EXAMPLE 2.
The following data units go from original data stream 110 to interleaved data stream 120 with delay d (1)=1 * 6=6:
X (1)=X (0,1)=1;
X (4)=X (1,1)=4, X (7)=X (3,1)=7,
X (10)=X (4,1)=10; and
X (13)=X (5,1)=13;
as indicated by, e.g., line 171 for data unit X (1)=X (0,1)=1 at i=l going to Y (7)=Y (2,1)=1 at i'=d(l)+ 7.
EXAMPLE 3.
The following data units go from original data stream 110 to interleaved data stream 120 with delay d (2)=2 * 6=12: X (2)=X (0,2) =2
X (5)=X (1,2) =5
X (8)=X (2_{/}2)=8
X (11) =X (3,2)=11
X (14)=X (4,2)=14
X (17)=X (5,2)=17 and
X (20)=X (6,2)=20
as indicated by, e.g., line 172 for data unit X (2)=X (0,2)=2 at i=2 goes to i'=14 (Y (14)=Y (4,2)=2).
In general, data units X (i)=X (b, j) in {ORIGINAL_DATA_STREAM} 110 are distributed to data units Y (i')=Y (b', j') in {INTERLEAVED_DATA_STRE M} by parameter (Dl) as follows:
X (i+ 0) to Y (i') ; e.g. , X(0)=0 to Y (0)=0; (9)
X (i+ 1) to Y (i'+(Dl) ) ; e.g. , X (1)=1 to Y (7)=1; (10)
X (i+j) to Y (i' +(D1) *j) ;
X (i+ (J1)) to Y (i'+ (D1)*J); e.g. , X (2)=2 to Y (14)=2 . (11)
FIG. 3 illustrates a prior art interleaver 200 that comprises a number of (J1) (here: (J1) =2) delay lines: 231, 232 and zerodelay line 230, a write switch 215, and a read switch 225. Interleaver 200 receives original data stream 110 (of FIG. 2) with data units 112 on input line 210. Arrow 216 in write switch 215 (which has J=3 positions) symbolizes how in every time point Ti write switch 215 couples input line 210 to zerodelay line 230 (position "0" or "j=0"), to delay line 231 (position "1" or "j=l"), to delay line 232 (position "2" or position "J1") and again to zerodelay line 130 (position "0"), and so forth. Accordingly, arrow 226 shows how read switch 226 couples lines 230232 to output line 220 (positions "0", "1", and "2"). Thus, switches 215 and 225 couple an input line 110 and an output line 120 via one of delay lines 230232.
In one prior art embodiment, the delay lines 231 and 232 are implemented using shift registers of the type firstinfirstout (FIFO) . Delay line 231 has a number of Dl=2 storage cells 241, 243 (in short: cells) to store data units, wherein the delay line 232 has a number of D2=4 storage cells 242, 244, 245, and 246. The numbers Dl and D2 depend on the depth parameter (D1) . In general, a delay line at position "j" has Dj=j * (Dl)/J storage cells. Dj is also referred to as "FIFOsize".
Thus, a prior art interleaving method includes the following steps of: (1) moving (216, 226) switches 215 and 226 in order to select a delay line 230, 231, or 232; (2) shifting out data units from selected line (230, 231, or 232) to output line 220; (3) shifting data units inside selected line (230, 231, or 232) ; (4) shifting in data units from input line 210 to selected line (230, 231, or 232); (5) preferably repeating steps (1 4).
It is understood to a skillful artisan, that delay lines 231 and 232 with storage cells 241, 243, 242, 244, 245, 246 can be implemented (mapped) by memory cells of e.g., a random access memory (RAM), wherein multiple pointers are calculated by a computing unit.
According to *761 patent, an interleaving/ deinterleaving apparatus can be implemented by using a plurality of firstinfirstout memory registers (FIFOs) (or "delay lines") mapped into memory (e.g., RAM). Each of the FIFOs is formed by memory cells virtually moving through the memory. The interleaver (or deinterleaver) of 761 patent uses only one pointer variable p for any number of delay lines mapped into the memory. The pointer comprises an offset parameter depending only on (D1) and J. This gives the interleaver (deinterleaver) flexibility. The calculation time for p is minimized by having the interleaver (deinterleaver) to read data from memory locations and uses the same location for consecutively writing data.
In the prior art, the variable pointer p is used as an index for storage cells and includes an ele ment of a set {P}={0, 1, 2, 3, . . . (Pl) } comprising P positive integers (pI{P}). For A, B being positive integers and CI{P}, a modulo addition mod (A+ B) =C is defined as follows :
C=(A+B) for A + B <(P1); (12)
and
C=(A+B)  P for A+B >(P1). (13)
A prior art modulo subtraction is defined as follows:
C=(AB) for AB >0 (14)
and
C=(AB)+ P for AB < 0. (15)
EXAMPLE 4. In a set {P} ={0, 1, 2, 3} of P=4 elements, and
A=2 and B=3 , C is calculated as follows: C=mod (A+B)= mod (2+3) =1; C=mod (AB) =mod (23)= 1 +4=3.
For convenience, the number P of elements in set {P}, also called "base", can be indicated as sub script, such as in e.g., mod_{p} (A+B) .
FIG. 4 illustrates a simplified block diagram of a prior art data transmission system 300 comprising interleaver 301', channel 304, and deinterleaver 200 (of FIG. 3). Interleaver 301' receives original data stream 110 (of FIG. 2) and provides interleaved data stream 120 to channel 304. Channel 304 transmits stream 120 to deinterleaver 200 which deinterleaves stream 120 to original data stream 110'. A preferred data stream flow is indicated in FIG. 4 by arrows 310 going to the right, however, the transmission system 300 can operate also in the opposite direction shown by dashed arrows 320 going to the left. FIG. 5 illustrates a simplified block diagram of interleaver 301' /deinterleaver 200 of FIG. 4. Though the following description is focused on the function of interleaver 301', it is believed that a skillful artisan is able, based on the description herein, to implement deinterleaver 200 accordingly.
Interleaver 301' comprises memory 345, pointer generator 308, and memory controller 311. Interleaver 301' receives input stream 101 at input line 310 and provides output stream 102 at output line 320. Lines 310 and 320 are, preferably, implemented by data bus 309. Data bus 309 can carry data, for example, parallel or serially. Data bus 309 with input line 310 and output line 320 is coupled to memory controller 311. Memory controller 311 is coupled to memory 345. Pointer generator 308 supplies pointer 313
(hereinafter pointer p) to memory controller 311. Memory 345 comprises a plurality of K or more storage cells 340k (e.g., k=0 to Kl) , wherein "cells", "memory locations", or "memory cells" are used interchangeably. Cells 340k and 340 (k+ 1) or 340 (kl) are, preferably, not coupled to each other for the purpose of shifting data. It is assumed that one cell 340k can store one data unit X (b, j) (112 of FIG. 2) or Y (b', j'), for instance, one byte. It is understood, that a person skillful in the art, based on the description herein, can organize memory 345 in a different way. Cell (340p) includes a cell (340k) which is addressed by pointer p. Pointer p is an element of the set {P}={0, 1, 2, 3, . . . (Pl) } wherein (P1)=(K1). In other words, pointer p identifies cell (340p) and activates cell (340p) for the data exchange.
Referring still to FIG. 5, in one prior art embodiment, interleaver 301' puts one data unit X (b,j) from input stream 101 to input line 310. Memory control ler 311 stores X (b,j) from input line 310 in cell 340p. Data previously stored in cell 340p is thereby overwritten. After that, memory controller 311 copies the data stored in cell 340p as data unit Y (b', j') to output line 320. During reading, data in cell 340p can remain unchanged or can be deleted. Next, interleaver 301' puts one data byte from output line 320 to output stream 102. Memory controller 311 can also send data unit X (b,j) into memory 345 for storage. In one prior art embodiment, pointer generator
308 initially sets pointer p to a value 0 (zero) and changes pointer's p value, by summation or subtraction, by a predefined value. The pointer's p value can be incremented by a value of 1, 2, and so on, up to a modulo value, or decremented by a value of 1, 2, and so on, down to a modulo value.
Interleaver 301' can use its memory 345 as a delay line. Pointer generator 308 knows values Dj , also called "FIFOsize" . The values Dj are calculated once and stored in pointer generator 308 or calculated by pointer generator 308 at the time they are required. For example, when convolutional interleaving as shown in FIG. 2 is performed, values Dj are:
Dj=j* (D1) /J, for j=l to J1; (16)
but other values can also be used. Values D ' with a primed index j' are calculated in the same way. For example, to perform interleaving procedure 100 of FIG. 2, with parameters (D1) =6 and J=3 , Dj includes two values:
Dl=2 and D2=4. Dj correspond to the sizes of delay lines 231 and 232 (of FIG. 3) . Interleaver 301' writes/reads data units X and Y to/from cells which are at Dj distance located in memory 345 (of FIG. 5) . The number K of cells 340k of memory 345 is equal or larger than the sum of Dj for j=l to (J1) . Preferably, memory 345 temporarily stores data units X (bj ) with 0<j<J 1 and data units Y (b40, j') with 0<j<J'l.
It is convenient for calculating pointer p, that pointer generator 308 knows partial sums, further referred to as offset (j):
offset (j)=Dl+ D2+... D(j1)+ Dj . (17)
The offset (j) can be equal to the number K of cells 340k. The offset (j) can be stored in pointer generator 308. When offset (j) is added to p (or subtracted from p) (pϊ{P}) then modulo addition or subtraction is applicable .
The present invention can be best understood by focusing on conceptual diagram 400, as depicted on FIG. 6, that shows a prior art data transmission system comprising a convolutional digital video broadcast channel (DVB channel) interleaver 402, and a convolutional DVB deinterleaver 422 that are configured to mitigate the effect of a bursty communication channel 420.
The prior art DVB interleaver and DVB de interleaver have been typically implemented using a plurality of firstinfirstout memory registers (FIFOs) 418 (or "delay lines") mapped into memory (e.g., a RAM memory unit, a hard drive memory unit, or an external memory unit) . For example, see memory 345 of FIG. 5 including a number of memory cells (for example, please, see memory cells 3400 through 340 (kl) of FIG. 5). Each of the FIFOs is formed by memory cells virtually moving through the memory.
The prior art DVB interleaver 402 (of FIG. 6) interleaves an original data stream 406 by using two interleaving parameters: L=12, and M=17, wherein L is the number of M byte long delay lines (410, 412, and so on) so that the original data stream 406 is divided into a plurality of data blocks (for example, please, see a plurality of data blocks 140, 141, ... 146 of FIG. 2), wherein each data block comprises a plurality of data units (for example, please, see a plurality of data units
0, 1, and 2 within block 140 of FIG. 2) . Each delay line has a WRITE address pointer and READ address pointer generated by a pointer generator (for example, please, see 308 of FIG. 5) . Pointer generator can generate a variable pointer p to be used as an index for memory cells. In general, the interleaver pointer generator is cyclically modulo modifying the interleaver pointer p up or down to or from an interleaver P modulo value, that is variable pointer p includes an element of a set {P}={0,
1, 2, 3, . . . (Pl) } comprising P positive integers
(pϊ{P>) •
Similarly, the prior art DVB deinterleaver 422 (of FIG. 6) deinterleaves a received data stream 426 by using two deinterleaving parameters: L'=L =12, and
M'=M=17, wherein L' is the number of M' byte long delay lines (424, 428, 430, and so on), so that the received data stream 426 is divided into a plurality of data blocks ( for example, please, see a plurality of data blocks 150, 151, ... 156 of FIG. 2), wherein each data block comprises a plurality of data units (for example, please, see a plurality of data units 0, Zl, ands Z2 within block 150 of FIG. 2) . Each delay line has a WRITE address pointer and READ address pointer generated by a deinterleaver pointer generator (for example, please, see deinterleaver pointer generator 308 of FIG. 5) . Again, in general, the deinterleaver pointer generator is cyclically modulo modifying the deinterleaver pointer p' up or down to or from an deinterleaver P' modulo value, that is variable pointer p' includes an element of a set {P'} = {0, 1, 2, 3, . . . (P'l) } comprising P' positive integers (p'l{P'}). Preferably, the interleaver pointer generator and the deinterleaver pointer generator are synchronized by using the sync word route (404420425 of FIG.6).
More specifically, the conventional (prior art) method of interleaving procedure using the convolutional interleaver 402 of FIG. 6 uses a variable pointer p as an index for memory cell.
The pointer #1 (used for the interleaver memory cell 410 including 17 bytes, or for the deinterleaver memory cell 432 including 17 bytes) increments from 0 up to a module value 16, or decrements from modulo value 16 down to 0, to cover all 17 bytes in the memory cell, then recycles. That is variable pointer (p = row 1 for interleaver, or p => row 10 for deinterleaver) includes an element of a set {17}={0, 1, 2, 3, . . . 16} comprising 17 positive integers.
Similarly, the pointer #2 (used for the interleaver memory cell 412 including 17 bytes, or for the deinterleaver memory cell 432 including 17x2 =34 bytes) increments from 17 up to a module value 50, or decrements from modulo value 50 down to 17, to cover all 34 bytes in the memory cell, then recycles. That is variable pointer (p = row 2 for interleaver, or p => row 9 for deinterleaver) includes an element of a set {34}={17, 18, 19, . . . 50} comprising 34 positive integers.
The variable pointer (p => row 3 for interleaver, or p => row 8 for deinterleaver) includes an element of a set {51} ={51100} comprising 51 positive integers; the variable pointer (p = row 4 for interleaver, or p =» row 7 for deinterleaver) includes an element of a set {68} ={101167} comprising 68 positive integers; and so on. The last variable pointer (p => row 11 for interleaver, or p = row 0 for deinterleaver) includes an element of a set {11*17 = 187}={9401127} comprising 68 positive integers One 10bit register is insufficient to store the pointer data for each row because it includes only 1024 bytes, and we need to store 1127 bytes. The RAM memory comes only in 2^{N} bytes, wherein N is an integer, so that the minimum RAM memory that can be used to store all necessary bytes for each row requires N = 11. Thus, a prior art interleaver having 11 rows uses 2048 bytes total. Even if READ and WRITE pointers are combined, each row requires current pointer, maximum address (where it wraps around) , and base address (where it wraps to) . In addition to an 11bit pointer register, for each row we need also an upper limit 11bit address register, and a lower limit 11 bit address register, for a total of 3 11bits registers per row. Thus, a circuit including 11 rows requires 11 * 33 = 330 bit registers. One bit register requires 6 gates, so that an 11 rows circuit requires (330) *6 gates= 1980 gates for registers only, plus a number of multiplexers and modulo adders, resulting in a rather large and complex circuit. This leaves about half of RAM unused in the prior art implementation of interleaver 402 (or deinterleaver 422) of FIG. 6, thus significantly increasing the cost of the prior art implementation of interleaver 402 (or deinterleaver 422) of FIG. 6.
Thus, a prior art interleaver requires a fairly large amount of RAM, wherein a substantial amount of RAM memory is left over and is available for other uses. It is an object of the present invention to make use of these available bytes of RAM to simplify the interleaver and/or deinterleaver circuit design and to avoid the need for numerous unused storage registers, multiplexers, and computation circuits.
The present invention makes the most efficient use of the RAM memory itself instead of using the prior art 11 bit registers. In one embodiment of the present invention, at first the data is read out, and than the new data is written in. In alternative embodiment of the present invention, at first the new data is written in, and than the previous data is read out.
FIG. 7A depicts a RAM representation of a DVB interleaver data structure 460 of the present invention that processes an input data stream by using two interleaving parameters: L =12, and M=17, wherein L is the number of M byte long delay lines. Each delay line is represented by a row (462 through 484) that has a base value and a current step value, both stored in RAM. The base value for a row is the starting base address for that row, divided by 17. As shown in FIG. 7B, the current step value is the index of the 17byte segment presently used by the row (the step value is 0 for 17byte segment 498) , wherein the block counter 504 counts from 0 to 16 and represents how many bytes into a given segment 498 the pointer is. The base value and current step value for the present row are read out of RAM. In the preferred embodiment of the present invention, the pointer address is computed as follows:
Pointer address=
[ (base_value + current_step_value) * 17] + block_counter_value . (18)
At the pointer address as computed according to Eq. (18) , the output byte is read, and the input byte is written. If block counter wraps around to 0, current step value is incremented, modulo (row number 1) and written to RAM.
In the alternative embodiment of the present invention, the block counter wraps around to 16, current step value is decremented down to modulo (16row number) and written to RAM.
It is understood by those skillful in the art, that as the pointer address is computed according to Eq. (18) , the output byte is read, and the input byte is written. If block counter wraps around to 0, current step value is incremented, modulo (row number 1) and written to RAM. If block counter wraps around to 16, current step value is decremented, modulo (16 row number) and written to RAM. Preferably, the RAM bytes that contain the base values should be initialized to 0, 1, 3, 6, ... and the RAM bytes that contain the current step values should be initialized to 0. In the preferred embodiment of the present invention, the RAM representation of deinterleaver data structure is substantially the same as the given above the RAM representation of interleaver data structure (460 of FIG. 7A, and 560 of FIG. 7B) .
The present invention usage of the RAM memory is optimum as compared with the prior art (as shown in FIG. 6) because all bytes of RAM memory are used for RAM representation of interleaver data structure of the pres ent invention, wherein only about 50% of RAM memory are used for register representation in the prior art interleaver (402 of FIG. 6) .
One aspect of the present invention is directed to a method for data transmission using an interleaver to spread out the bursts of errors caused by a bursty error channel, as depicted in the flow chart 600 of FIG. 8.
An original data stream is intreleaved (step 602 of FIG. 8) by at least one interleaving parameter so that the original data stream (for instance, the data stream 105 of FIG. 2) is divided in a plurality of data blocks (for instance, blocks 140, 141, ...1456 of FIG. 2), wherein each data block comprises a plurality of data units. As shown in FIG. 2, data block 140 comprises data units {0, 1, 2}. In one embodiment of the present invention, the original data stream is interleaved by configuring an interleaver memory unit (step 604 of FIG. 8) for writing and reading the plurality of data units into a plurality of the interleaver memory locations identified by a sin gle interleaver pointer and an interleaver pointer generator. The interleaver pointer is generated (step 608) by using the interleaver pointer generator (for instance, the pointer generator 308 as shown in FIG. 5) .
In one embodiment of the present invention, the user selects an algorithm (step 610 of FIG. 8) that determines at which points the interleaver pointer takes value. More specifically, one can use a password to determine at which points the pointer should take value. As a result, the password takes only certain predetermined values according to password up or down to the pointer modulo value. The password can be transmitted to the recipient of information on the deinterleaver side of the transmission channel, so that the recipient of data can use the same algorithm to recover the transmitted data in the right order.
EXAMPLE 5. The variable pointer p takes values according to password H = { _{Xι} p_{2/} p_{3/} p_{4/} p_{5>} .. p_{k}} , that is variable pointer p includes an element of a subset {P_{k}} = {p_{1(} p_{2>} p_{3;} P_{4}, P_{5}, • • } comprising k positive integers.
Finally (step 612 of FIG. 8) , the interleaver pointer is cyclically modulo modified up (or down) to (or from) an interleaver modulo value P. In one embodiment, the interleaver pointer is increased up to the interleaver modulo value according to the algorithm:
{^{p}k} = {Pi. P2, P_{3}, P4, P_{5}, • ^{■} Pk>' wherein {p_ < p_{2} < p_{3} <p_{4} <p_{5} <P ) ■ ^{In an} alternative embodiment, the interleaver pointer is decreased down to the interleaver modulo value according to the algorithm: {P_{k}} = {p_{X/} p_{2} p_{3f} p_{4r} p_{5ι}.. p_{k}} , and wherein {p_{x} > p_{2} > p_{3} >p_{4}
>P_{5} >P_{k}> FIG. 9 is a flow chart 620 that depicts the method of the present invention for using a de interleaver to recover the original data stream transmitted over a bursty error channel .
An original data stream (for instance, the data stream 105 of FIG. 2) is recovered (step 626 of FIG. 9) by using the deinterleaver (as data stream 105' of FIG. 2) .
In one embodiment of the present invention, the received data stream is deinterleaved by configuring a deinterleaver memory unit (step 628 of FIG. 9) for writing and reading the plurality of data units into a plurality of the deinterleaver memory locations identified by a single deinterleaver pointer and deinterleaver pointer generator. The deinterleaver pointer is generated (step 632) by using the deinterleaver pointer generator after the interleaver pointer generator and the deinterleaver pointer generator are synchronized (step 630) .
In one embodiment of the present invention, the encrypted original data stream is decrypted by using the same algorithm that was used for encryption (634). The selected algorithm is transmitted to the recipient as a part of the transmitted data.
EXAMPLE 6.
The variable deinterleaver pointer p takes values according to transmitted selected password N_{k}, that is variable deinterleaver pointer p includes an element of a subset {P_{k}} = {p_{1;} p_{2,} p_{3,} p p_{5} .  p_{k}} comprising k positive integers according to password K_{k}, wherein
N_{k} ^{= (}Pi, P_{2}, P_{3}, P., Ps, • • Pk> •
Finally (step 636 of FIG. 9), the de interleaver pointer is cyclically modulo modified up (or down) to (or from) a deinterleaver modulo value P. In one embodiment, the deinterleaver pointer is increased up to the deinterleaver modulo value according to the algorithm: {P_{k}} ={p_{1} P_{2}, P_{3}, P_{4}, Ps, • • P_{k} ' wherein {p_{L} < p_{2} < p_{3} <p <p_{5} ^_{k}^ • ^^{n an} alternative embodiment, the deinterleaver pointer is decreased down to the interleaver modulo value according to the algorithm: {P_{k}}={p_{1(} ρ_{2(} p_{3>} p_{4ι} p_{5ι}.. p_{k}}, and wherein {p_{x} > p_{2} > p_{3} >p_{4}
In one embodiment, the interleaver pointer and deinterleaver pointers go in the same direction. In an alternative embodiment, the interleaver pointer and de interleaver pointers go in different direction. For instance, the interleaver pointer is increasing, and the de interleaver pointer is decreasing, or vice versa.The description of the preferred embodiment of this invention is given for purposes of explaining the principles thereof, and is not to be considered as limit ing or restricting the invention since many modifications may be made by the exercise of skill in the art without departing from the scope of the invention.
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