WO2002021691A1

WO2002021691A1 - Method and device for reducing the locking time in power inverters

Info

Publication number: WO2002021691A1
Application number: PCT/DE2001/003422
Authority: WO
Inventors: Michael Peppel; Stefan HÄUSER
Original assignee: Transmit Gmbh
Priority date: 2000-09-08
Filing date: 2001-09-06
Publication date: 2002-03-14
Also published as: DE10044446A1

Abstract

The invention relates to a method and device for reducing the locking time to be maintained between two switching processes in switching elements in power inverters, which is provided to avoid short-circuits in the bridge arms of power inverters. The basis of the invention is that a maintenance of a locking time of conventional duration is only necessary in those cases where current has actually flowed through one of the switching elements. If no current has flowed through the switching element, because the current has flowed through the diode wired in an anti-parallel arrangement to the relevant switching element, then the maintenance of a locking time of significantly reduced duration, in relation to the conventional controllers for the current-carrying case, is sufficient.

Description

description

Method and device for reducing the locking times for inverters

More information

The invention relates to an inverter control device and a method for operating this device. The device and the method ensure a shortening of the locking times which have to be observed in order to protect inverter switching elements from short-circuit currents.

State of the art

The invention relates to the technical field of voltage impressing inverters, which e.g. can be used to control an electrical machine. Such an inverter converts a DC voltage, which is usually obtained from the three-phase network by a rectifier and is buffered in capacitors with large capacitance (intermediate circuit, (ZK)), into an AC voltage. Usually, switches (1), e.g. IGBTs (Insulated Gate Bipolar Transistors) used in the configuration of a three-phase bridge. Fig. La shows schematically such a three-phase inverter in a bridge circuit with the DC voltage supply (20), which represents the output of the intermediate circuit (ZK), with the switches (1) and the electric machine (11).

The output phase of each bridge branch is switched to positive or negative potential once in push-pull. This creates an alternating voltage at every phase. An almost sinusoidal current flows through appropriate inductances in the phases. The windings of a motor in the machine (21) are sufficient as inductors. Otherwise, additional chokes are usually installed. Fig. Lb shows the usual design of one of the three bridge branches of the schematic structure from Fig. La. Switching elements (3), such as, for example, IGBTs, MOSFETs or bipolar transistors, are typically used therein as switches. If, for example, the IGBT receives a positive voltage against the emitter (eg + 15V) at its gate, it is conductive. If the gate is brought to negative voltage (eg —IV), the IGBT is non-conductive after a component-dependent period of time and thus the switching state is locked.

In the example in FIG. 1 a, the gate-emitter voltage is generated by the drivers (2) which are connected upstream of the IGBTs. Drivers are also known in the prior art which do not generate the gate-emitter voltage themselves, but rather only convert corresponding control signals into those which can be used for IGBTs. Control signals are connected to the input of the drivers of FIG. 1 a, which are provided by a corresponding regulation (e.g. microprocessor or by pulse width modulation). If the driver receives a logical 1 at the input in the example (with CMOS / TTL technology this usually corresponds to a voltage of 5V), the driver applies the positive voltage to the gate of the corresponding IGBT, which makes it conductive, with a logical one 0 (0V), the IGBT blocks. The drivers are usually designed so that, in contrast to pure logic circuits, they can provide the necessary currents to control the IGBT.

Since IGBT are components that can only carry current in one direction, a diode (4) is placed antiparallel to each IGBT so that current can flow in both directions at both output polarities.

A problem appears when switching off the component. The charge carriers remaining in the IGBT must be removed from the IGBT or dismantled within the component. This leads to longer switching delay times between two switching processes and a so-called collector current tail (tail current) during switching off. This means that there is uncertainty as to whether the IGBT is really switched off or locked.

If one of the IGBTs of a bridge branch is now switched on, although the other IGBT of the same branch is not yet completely de-energized, there is a risk of generating a short circuit via the DC link. To avoid this damage, the control of the IGBTs after the switch-off signal has been sent to the one IGBT of a bridge arm is provided with a period of time called “locking time” (Δt_off) in which the second IGBT of the bridge arm is not yet switched on. This locking time is in the commonly used drivers, fixed or not selectable during operation, set and, depending on the IGBT, is about 3 ... 10 μs.

Some writings for solving this problem in such inverters are known in the literature. DE 198 43 692 proposes, in order to circumvent the short-circuit problem with inverters for feeding into an AC network, to provide a separate circuit unit for generating each half-oscillation of the desired sinusoidal output current.

DE 198 08 104 proposes as a solution to carry out a locking time compensation by means of several special auxiliary devices. Other proposals to solve or reduce the problem also suggest the introduction of sometimes very expensive auxiliary devices. Examples of this are DE 198 49 097 or EP 01 76 800, which propose methods and devices for monitoring the switching status of IGBTs or turn-off thyristors. Disadvantages of the prior art

The transmission characteristic of the converter becomes non-linear due to the compliance with the locking times, which makes it difficult to control the connected machines. By shortening the locking times, among other things the non-linearity can be reduced.

In the commonly available inverters, only those control methods are implemented that, regardless of the possible switching states of the switching elements (3) in the bridge branches, always adhere to the same locking time (Δt_off) that cannot be changed during operation between two switching operations of switching elements in a bridge circuit. As a result, the longest locking time, depending on the switching elements (3), must be observed as a uniform locking time.

For the sake of clarity, the emergence of the non-linearity is shown in the following for the frequently found case of controlling an inverter with IGBTs as switching elements (3) in a bridge circuit according to FIG Delta voltage (e.g. 8 kHz, Fig. 2a)). If the sinusoidal voltage is greater than the triangular voltage, the upper IGBT (3a) is switched to the phase, the sinusoidal voltage is lower, the lower IGBT (3b). Since the frequency of the delta voltage is usually much higher than that of the sinusoidal voltage, the sinusoidal voltage can be approximated as a straight line if only two switching periods are considered (FIG. 2b)). The input signals for the drivers (2a, b from FIG. 1b) resulting from the PWM are shown in FIG. 2c), and in FIG. 2d) the resulting gate-emitter voltage time profiles with the locking times fixed in the drivers ( Δt_off). The effects of the locking time on the potential of the phase depend on the direction of the current flow and are reflected in the voltage time areas (Fig. 2 e, f). With the current direction out of the phase (Fig. 2e), a certain voltage time area is lost (ΔV-), with current flow into the phase (Fig. 2f), a voltage time area is gained (ΔV +). These changes in the output voltage determined by the control result in the non-linearity in the characteristic curve, so that between changes in the current direction, the output voltage of the inverter, which is averaged, is either smaller or larger than the ideal, sinusoidal output voltage.

Furthermore, the missing or additional voltage time areas ensure further harmonics of low frequency, which in a connected machine cause oscillations, i.e. mechanical vibrations of the machine itself (vibrating moments).

Furthermore, the switching frequency must remain in a lower range (here e.g. 8 kHz). If the switching frequency is increased with the same locking time, the relative duty cycle becomes smaller and smaller. However, it would be advantageous to increase the switching frequency, since this would bring the inverter's output current closer to the sinusoidal shape, which in turn reduces the harmonics in the current and thus the pendulum moments. The disadvantages described above naturally also arise with other control methods in which locking times are provided for switching elements, such as when controlled by a microcontroller.

The object of the invention The object of the invention is to provide a method so that switching elements in inverters with switching elements in a bridge circuit, in particular IGBTs, can be switched with the shortest possible locking time. Another object of the invention is to provide a device for carrying out the method that is as simple and therefore inexpensive as possible.

Solution of the task The solution of the task is based on the fact that it is only necessary to adhere to a locking time that has been usual up to now only in those cases in which current has actually flowed through one of the switching elements (3). If the switching element was de-energized because the current flowed through the diode connected antiparallel to the switching element, it is sufficient to observe a locking time of significantly shorter duration than was previously provided for in the current controls for the current-carrying case. A total of four cases can be distinguished, two of which are considered here with IGBTs as switching elements (3) (Fig. 3.1, 3.2). The other two can easily be derived from the cases considered.

Case 1: (Long locking time Δt_off, Fig. 3.1) The observation assumes that current flows out of the phase via the upper switching element (3a). The driver (2a) of the upper switching element (3a) switches the element (3a) off by changing the voltage. The voltage across the upper switching element (3a) in the main current path (U _C κ, 3a) increases, while the corresponding current (I _c , 3a (t)) drops with the characteristic current tail. Since the inductances usually present in the load circuit prevent the current from being cut off, it switches to the lower diode (4b) without the lower switching element (3b) having to be switched on. This also changes the potential at the output terminal from ZK + to ZK-. In this case, switching on the lower switching element (3b) before the current (I _c , 3a (t)) from the switching element (3a) decays would lead to a short circuit. In this case, a long locking time (Δt__off) must be observed, which is determined in more detail by the time Duration between the time the switch-off signal for the switching element is issued until the time at which the current from this element has fallen below a level which is still compatible with this element in the event of a short circuit.

Switching on the element (3b) is necessary because the current could have a zero crossing until the next switching signal specified by the control and then the current flow from the lower diode (4b) to the lower switching element (3b) must be able to change without one separate switching operation must take place.

Case 2: (Short locking time Δt_off, Fig.3.2)

The consideration assumes that current flows via the upper diode (4a), ie into the phase, and that the upper switching element (3a) is switched on.

If the upper switching element (3a) is now blocked by the driver (2a), no change occurs initially. The current neither commutes to another component in the bridge branch, nor does the potential of the phase change. Both only change when the lower switching element (3b) is switched to conductive by the associated driver (2b).

Between the blocking of the upper switching element (3a) and the opening of the lower switching element (3b), a much shorter locking time must be observed in this case than in the first case, where the upper switching element was live before switching the lower element.

The other two cases result from cases 1 and 2 by reversing the direction of the potential change in the starting phase and the direction of the current.

In the case of IGBTs as switching elements, a locking time of max. lμs are completely sufficient so that a considerable reduction in the locking time - compared to the usual, fixed long locking times between see 3 - 10 μs with conventional, not case-specific inverter controls.

ADVANTAGES OF THE INVENTION The invention has the advantage over the prior art that, depending on the switching state of the switching elements in bridge circuit, only the component-dependent, shortest possible locking time between switching off a switching element and switching on the second switching element is waited for in a bridge branch.

With the method according to the invention, in two of the four possible switching states, even a locking time can be applied which is less than the component-related duration of the switching elements, which elapses between the time when the switch-off signal for the switching element is emitted and when a current from this element falls below a level that is still compatible with this element in the event of a short circuit.

Examples

Using the two pieces of information, the switching state of the switching elements in a bridge branch and the direction of current via the branch between the two diodes of the bridge branch, it can be decided according to the invention whether a short or long locking time between two switching operations within a bridge branch is to be observed. The following table shows the four possible cases:

The invention and its advantageous embodiments are described in more detail by the following figures and examples. Show it:

Fig. La the basic structure of a one-stage, three-phase inverter in bridge circuit

Fig. Lb the conventional design of one of the three bridge branches of the schematic structure of Fig. La in the prior art.

2 shows the emergence of non-linearities in conventional inverters with conventional PWM control of IGBTs as switching elements when considering a bridge branch. Fig. 3.1 one of the two possible out of four cases of switching states within a bridge branch, in which a long locking time between switching off the one and switching on the other switching element must be observed.

Fig. 3.2 one of the two possible out of four cases of switching states within a bridge branch in which only a short locking time between switching off the one and switching on the other switching element must be observed.

4 shows an advantageous embodiment of the device according to the invention for a bridge branch as a block diagram.

Fig. 5 shows an exemplary assembly of the advantageous embodiment of the device according to the invention.

Fig. 6 shows a further advantageous embodiment of the device according to the invention as a block diagram for the case in which the drivers (2) are not immediately upstream of short locking timing pulse generating devices.

FIG. 7 shows an example of the configuration according to FIG. 6.

4 and 5 describe, as a block diagram and in a specific assembly example, an advantageous embodiment of the method according to the invention and an exemplary device in which the generation of the short locking time pulses is provided in the short locking time pulse generation devices (9.1) connected upstream of the drivers (2a, b) and the generation of the long locking time pulse is provided in the device (9.2). The signal from a current transformer normally provided in alternating current converters is passed in the current direction signal detection unit (6) to a fast comparator of the LM311 N type. This compares the signal with ground potential. If the current transformer signal is positive (current flows out of the phase), there is a logic one (5 V) at the comparator output. Conversely, the comparator supplies a zero when the current flows into the phase. The comparator output signal is applied in the current direction signal storage device (7) to the file input of a D flip-flop CD4013 (D-FF). The D-FF is switched so that it switches the state (1 or 0) of the signal at data input 0 through to output Q when it receives a positive trigger edge at the CLK input. This circuit ensures that a change in the current direction during the generation of the locking time pulse does not lead to the termination of the generation or the application of this locking time pulse to the inputs of the drivers (2), but that this pulse remains switched through to the driver inputs.

Trigger signals are generated in the control signal detection device (8) in order to store the current direction again each time the device is switched off. For this purpose, the control signals for TOP and BOT IGBTs are routed to a series of NOR gates CD4001 in the control signal detection device (8). These form a so-called "beeper". When a falling edge arrives at the input of a "beeper", a short pulse appears at the output for a few 100 ns. If the signals of the two beers are linked with an OR gate CD4071 as part of the control signal detection device (8), a pulse of less than 100 ns is always produced at the output of the device (8) when one of the two IGBTs has been switched off , In order to store the current direction again each time an IGBT is switched off, the output of (8) is connected to the current direction signal storage device (7). Furthermore, the output signal of the control signal detection device (8) is also connected to the trigger input of a monostable multivibrator CD4047 within the long locking time generation device (9.2). This so-called monovibrator produces positive signals for everyone

Edge at + T has an approximately 10 μs long pulse at its output Q. This pulse corresponds to the long locking time pulse. Finally, a logical evaluation unit (10) decides whether the long locking time pulse from the device (9.2) is passed on to the inputs of the drivers (2). The stored signal of the current direction is linked with the control signal of the TOP-IGBT within the first evaluation subunit (10.1) by an exclusive OR CD4030 (X-OR). The X-OR assumes high potential at the output when one of the inputs is at high potential and the other at low potential. In this case, the long locking time pulse must be switched through to the drivers. The output of the X-OR is 1 if and only if a long locking time pulse is required.

The output signal of the X-OR is now linked within the second logic subunit (10.2) by a NAND gate CD4081 with the output signal of the monovibrator, ie the long-lock time pulse generator (9.2). The NAND gate outputs a 0 at the output if and only if both inputs are at 1. Then the long locking time pulse is also switched through. This is then linked to the control signals for both IGBTs by an AND gate CD4081 each within the third logical subunit (10.3). As long as the NAND gate outputs a 1, the control signals are directly connected to the driver inputs. With a 0 at the output of the NAND gate, both control signals for the drivers are blocked. Both IGBTs are non-conductive. Only after the long locking time pulse has elapsed can one of the two IGBTs be switched on. Another embodiment example is shown in FIGS. 6 and 7. Compared to the example in FIGS. 4 and 5, it is assumed here that the drivers (2) are not directly connected with short locking time pulse generation devices (9.1).

Compared to FIGS. 4 and 5, a central short locking time pulse generating device (9.1) is provided in the form of a second monovibrator and the third sub-unit (10.3) of the logical evaluation unit (10) has been supplemented by a logical "and" block.

In this exemplary embodiment, both locking time pulse generation devices (9.1, 9.2) are started by the control signal detection device (8) in the form of the beepers and in the logic evaluation device (10) it is then decided which of the two locking time pulses is applied to the inputs of the drivers (2) be switched through.

Further design examples result from the use of software, in which e.g. a microprocessor calculates the switch-on signals for the switching elements (3) and, by supplying the current direction signal, the microprocessor delays the switch-on signals according to the required locking time. This would further reduce the circuitry.

Furthermore, the device according to the invention and the method could also be integrated in an application-specific component (eg ASIC) in the form of a new ASICS as well as by changing the control of ASICs already used to control inverters. LIST OF REFERENCE NUMBERS

1 switch

2 drivers 3 switching element

4 diode

5 Tap for determining the current direction

6 current direction signal detection device

7 Stro directional signal storage device 8 control signal detection device

9.1 Short lock time pulse generator

9.2 Long lock timing pulse generator

10 Logical evaluation unit 10.1 First subunit 10.2 Second subunit 10.3 Third subunit

11 control signal lines for the drivers of the switching elements (3)

20 DC voltage of the intermediate circuit 21 Electrical machine

AS shutdown signal

DC link intermediate circuit

(ΔV-) Negative voltage time area

(ΔV +) Positive voltage time area Δt off locking time (impulse)

Claims

protection claims

1. A method for controlling switching elements (3) in single-stage inverters, each with a switching element in one of two bridge halves per bridge branch and with one diode (4) connected antiparallel to a switching element, each switching element being controlled by its own driver (2) is characterized in that the direction of the current is detected via the branch between the two diodes of a bridge branch and is stored as a current direction signal,

- That the control signals of the upper and / or lower driver are detected and, - That depending on the current direction signal and

Control signals of the upper or / and lower driver either a short or long locking time pulse is applied to the upper or / and lower switching element (3), the short locking time pulse being shorter in duration than the component-specific duration which is observed for short-circuit current protection of the switching elements (3) must become .

2. The method according to claim 1, characterized in that with current direction out of phase, with locked lower

Switching element (3b) and conductive upper switching element (3a) after the blocking signal has been sent to the upper switching element, a long locking time pulse is waited until one of the two or both switching elements is switched on again and that the current flows into phase, with the lower switching element locked ( 3b) and the conductive upper switching element (3a) after the blocking signal has been given to the upper switching element (3a), a short locking time pulse is waited until one of the two or both switching elements is switched on again, the two remaining switching elements tuations for waiting for another long and short locking time pulse result from the fact that in the situations mentioned the other direction of current is assumed.

3. The method according to claim 1 or 2, characterized in that in the drivers (2) or a generated in the circuit short lock time pulse shorter duration than the component-specific duration to be protected for short-circuit current protection by generating a second locking time pulse to the duration of to the

Short-circuit current protection to be observed locking time pulse is extended.

4. The method according to any one of claims 1 to 3, characterized in that - the control signals of the drivers are detected and in the event of the occurrence of a negative edge in one of the control signals a shutdown signal (AS) is generated,

- that the current direction of current is saved again with each switch-off signal,

Locking time pulse of adjustable duration, preferably a longer duration than the duration set in the drivers, but at most the duration of the locking time of the switching elements to be observed for the component for short-circuit protection, is generated,

- That the current direction signal with the control signal from the lines (11) of the upper switching element is logically "exclusive or" linked to form a long locking time signal (LTZ signal), - that the LTZ signal with the long

Locking time pulse is logically "not and" linked to form a driver disable signal while the LTZ signal is set, and

- That the driver disable signal is logically "and" linked to the control signals for each of the two drivers in a bridge branch.

5. The method according to claim 1, characterized in that a microprocessor is used to control the drivers so that the detection of the control signals for the drivers within the processor and that

Processor the current direction signal of a current direction detection device (6) is supplied.

6. Device for carrying out the method according to claim 1, each comprising a driver (2), with an upstream short locking time pulse generating device (9.1) for generating locking pulses with a duration that is below the component-specific required locking time of the connected switching element for each of the two switching elements (3), further comprising a control, in particular based on pulse width modulation or space vector modulation for the drivers (2) and a current transformer, each with a tap (5) between the two diodes (4) of a bridge arm, characterized by

- A current direction signal detection device (6) for detecting the current direction via the branch between the diodes of a bridge arm and for forming a corresponding current direction signal; - A current direction signal storage device (7) for storing the current direction signal from (6);

- A control signal detection device (8) for detecting the control signals of the lines (11) for the two drivers (2) and for generating a switch-off signal (AS) from the control signals if one of the control signals has a negative edge;

- a long lock time pulse

Generation device (9.2) for generating long locking time pulses of adjustable duration for the drivers (2), the duration preferably being equal to or greater than the minimum component-specific locking requirements is the switching elements used; - A logical evaluation unit (10), which comprises a first logical sub-unit (10.1), which logically links the stored current direction signal from (7) with the control signal of the upper or lower switching element (3) of the bridge arm in such a way that a long locking time signal only is generated in the two cases where a) the current flows out of the phase and the current flows successively first over the upper switching element (3) and then over the lower diode or b) the current flows into the phase and the current sequentially flows first over the lower switching element (3) and then over the upper diode; comprises a second logical subunit (10.2), which logically combines the output signal of the first subunit (10.1) with the long locking time pulses of the corresponding device (8) and comprises a third logical subunit (10.3) which contains the output signal of the second logical subunit ( 10.2) linked to the two control signals of the drivers (2) of the control signal lines (11) in such a way that in the above-mentioned cases a) and b) both control signals of the conventional control are blocked for the drivers (2) and that are generated by the logical subunit ( 10.3) that the

Switching elements (2) corresponding lock signal is emitted.

7. The device according to claim 6, characterized in that the current direction detection device (6) comprises a comparator which compares the current signal from the current transformer at the tap (5) with the ground potential and is connected to the current direction signal storage device (7).

8. Device according to one of claims 6 to 7, character- ized in that the current direction signal storage device (7) comprises a D flip-flop, which when a trigger edge is applied to an input, the state of the data input switches to the output and is connected to the control signal detection device (8), the long locking time pulse generation device (9) and the logical evaluation unit (10).

9. Device according to one of claims 6 to 8, characterized in that the control signal detection device (8) comprise two rows of at least 4 NOR gates (so-called beeper), which are connected in parallel with an OR gate, the one Series is connected to the signal line (11) of the upper driver and the other to that of the lower driver and the OR gate of the output of (8) is connected to the current direction signal storage means (7) and to the long lock timing pulse generator - device (9).

10. Device according to one of claims 6 to 9, characterized in that the long locking time pulse generating device (9) comprises a monostable multivibrator, preferably a monovibrator with an adjustable pulse duration, which with the current direction signal memory device (7), the control signal Detection device (8) and the logical evaluation unit (10) is connected.

11. The device according to one of claims 6 to 10, characterized in that the logical evaluation unit (10)

- A first sub-unit (10.1) with an "exclusive or" component, which is connected to the current direction signal storage device (7) and the control line (11) of the upper driver (2a);

- A second sub-unit (10.2) with a "not and" - component, which is connected to the output of (10.1) and the output of the long-locking time pulse generating device (9);

- a third subunit (10.3) with one each "And" component for each of the drivers (2a, b), the two AND components at one input being controlled in parallel by the output of the subunit (10.2) and the one AND component at the other input by the control signal from the upper driver and the second component at the other input is controlled by the control signal of the lower driver and the outputs of the AND components are connected to the upper or lower switching element (3) in accordance with the control of the control signals.

12. The device for performing the method according to claim 1, each comprising a driver (2), comprising a control, in particular based on pulse width modulation or space vector modulation for the drivers (2) and a current transformer, each with a tap (5) between the two diodes ( 4) a bridge branch, characterized in that only a single device (9.1 / 9.2) is provided for generating the short / long locking time pulse.

13. Device for performing the method according to claim 1, characterized in that a microprocessor or ASIC is provided for performing the method.

Attached drawings

Number of attached drawings:

A total of 7 figures on 8 sheets.