WO2002015285A1 - Metal sulfide semiconductor transistor devices - Google Patents
Metal sulfide semiconductor transistor devices Download PDFInfo
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- WO2002015285A1 WO2002015285A1 PCT/US2001/025259 US0125259W WO0215285A1 WO 2002015285 A1 WO2002015285 A1 WO 2002015285A1 US 0125259 W US0125259 W US 0125259W WO 0215285 A1 WO0215285 A1 WO 0215285A1
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- WIPO (PCT)
- Prior art keywords
- compound semiconductor
- sulfide
- layer
- field effect
- effect transistor
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 229910052976 metal sulfide Inorganic materials 0.000 title claims description 3
- 150000001875 compounds Chemical class 0.000 claims abstract description 94
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 57
- 230000005669 field effect Effects 0.000 claims abstract description 49
- 239000012212 insulator Substances 0.000 claims abstract description 49
- 239000005864 Sulphur Substances 0.000 claims abstract description 41
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 36
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000003870 refractory metal Substances 0.000 claims abstract description 25
- -1 gallium sulfide compounds Chemical class 0.000 claims abstract description 23
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910005228 Ga2S3 Inorganic materials 0.000 claims abstract description 9
- 239000000203 mixture Substances 0.000 claims abstract description 7
- 229910052761 rare earth metal Inorganic materials 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 18
- 239000007943 implant Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 230000000295 complement effect Effects 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 230000007547 defect Effects 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 70
- 238000005516 engineering process Methods 0.000 description 12
- 238000000151 deposition Methods 0.000 description 11
- 230000008021 deposition Effects 0.000 description 11
- 230000010354 integration Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 7
- BVSHTEBQPBBCFT-UHFFFAOYSA-N gallium(iii) sulfide Chemical compound [S-2].[S-2].[S-2].[Ga+3].[Ga+3] BVSHTEBQPBBCFT-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000002207 thermal evaporation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 150000002910 rare earth metals Chemical class 0.000 description 4
- 229910052688 Gadolinium Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010549 co-Evaporation Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66924—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with an active layer made of a group 13/15 material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
Definitions
- the present invention pertains to low power and high speed integrated circuits in the compound semiconductor field utilizing field effect transistors and more specifically complementary field effect transistors used in concert including enhancement mode self- aligned metal-sulfide-compound semiconductor transistors and depletion mode self-aligned metal-sulfide-compound semiconductor transistors and methods of materials growth and fabrication of said structures and the ultra large scale integration of said transistors.
- the gallium arsenide and indium phosphide integrated circuit industry has been limited without a technology that simultaneously allows the integration of complementary field effect transistor devices and transistors with low gate leakage currents.
- CMOS complementary metal oxide semiconductor
- FETs Field effect transistor
- III-V semiconductor industry employ metal gates and Schottky gate contacts that are have quiescent-state leakage currents exceeding many microamps.
- the use of metal gates in compound semiconductor technology further results in individual transistors and integrated circuits that have excessively high power dissipation, reduced transconductance, reduced logic swing and the inability to operate on a single power supply, and generally limited performance characteristics.
- CMOS complementary GaAs and InP circuit technology
- GaAs and InP circuit technology exhibits faster and more optimized speed/power performance and efficiency at a low supply voltage of IV and below.
- the market acceptance of these GaAs and InP integrated circuit technologies remains low because of the lack of ability to demonstrate high integration densities with low amounts of operating power.
- silicon CMOS dominates the field of digital integrated circuitry and neither GaAs nor InP technologies can successfully penetrate this market.
- FIG. 1 is simplified cross sectional view of a self-aligned enhancement mode compound semiconductor MSSFET in accordance with a preferred embodiment of the present invention
- FIG. 2 is a simplified flow chart illustrating a method of manufacturing a self-aligned enhancement mode compound semiconductor MSSFET in accordance with a preferred embodiment of the present invention.
- the exemplification set out herein illustrates a preferred embodiment of the invention in one form thereof, and such exemplification is not intended to be construed as limiting in any manner.
- the present invention provides, among other things, a self-aligned enhancement mode metal-sulfide-compound semiconductor FET.
- the FET includes a gallium sulphur insulating structure that is composed of at least two distinct layers.
- the first layer is most preferably more that 10 angstroms thick but less that 25 angstroms in thickness and composed substantially of gallium sulphur compounds including but not limited to stoichiometric Ga 2 S 3 , GaS, and Ga 2 S, and possibly a lesser fraction of other gallium sulphur compounds.
- the upper insulating layer in the gallium sulfide insulating structure is composed of an insulator that does not intermix with the underlying gallium sulphide insulating structure.
- This upper layer must possess excellent insulating qualities, and is most typically composed of gallium sulphur and a third rare earth element that together form a ternary insulating material. Therefore the entire gallium sulfide rare earth gate insulator structure is composed of at least two layers and may contain a third intermediate graded layers that consists of a mixture of the upper insulating material and the gallium sulphur compounds that compose the initial layer. Together the initial gallium sulphur layer, any intermediate graded layer and the top insulating region form both a gallium sulfide insulating structure and the gate insulator region of a metal-sulfide-compound semiconductor field effect transistor.
- the initial substantially gallium sulphur layer forms an atomically abrupt interface with the top layer of the compound semiconductor wafer structure, and does not introduce midgap surface states into the compound semiconductor material.
- a refractory metal gate electrode is preferably . positioned on the upper surface of the gate insulator structure layer.
- the refractory metal is stable on the gate insulator structure layer at elevated temperature.
- Self-aligned source and drain areas, and source and drain contacts are positioned on the source and drain areas.
- the metal-sulfide-compound semiconductor transistor includes multi-layer gate insulator structure including an initial gallium sulphur layer, intermediate transition layer, and upper insulating layer of 30-250 angstroms in thickness positioned on upper surface of a compound semiconductor heterostructure that form the gate insulator structure.
- the preferred embodiment also comprises a compound semiconductor heterostructure including a GaAs, Al x Ga 1-x As and In y Ga 1-y As layers with or wothout n-type and/or p-type charge supplying layers which are grown on a compound semiconductor substrate, a refractory metal gate of W, WN, or WSi, self aligned donor (n-channel FET) or acceptor (p-channel FET) implants, and source and drain ohmic contacts.
- a compound semiconductor heterostructure including a GaAs, Al x Ga 1-x As and In y Ga 1-y As layers with or wothout n-type and/or p-type charge supplying layers which are grown on a compound semiconductor substrate, a refractory metal gate of W, WN, or WSi, self aligned donor (n-channel FET) or acceptor (p-channel FET) implants, and source and drain ohmic contacts.
- the compound semiconductor heterostructure comprises an In y Ga ⁇ _ y As, Al ⁇ In ⁇ -x As, and InP compound semiconductor heterostructure and n-type and/or p-type charge supplying layers which are grown on an InP substrate, and a refractory metal gate of W, WN, or WSi, self aligned donor (n-channel FET) or acceptor (p-channel FET) implants, and source and drain ohmic contacts.
- FIG. 1 is simplified cross sectional view of a self-aligned enhancement mode compound semiconductor MSSFET in accordance with a preferred embodiment of the present invention.
- Device 10 includes a compound semiconductor material, such as any III-V material employed in any semiconductor device, represented herein by a III-V semiconductor substrate 11 and a compound semiconductor epitaxial layer structure 12.
- a compound semiconductor wafer structure which in FIG. 1 is designated 13.
- Methods of fabricating semiconductor wafer structure 13 include, but are not limited to, molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD). It will of course be understood that in some specific applications, there may be no epitaxial layers present and upper surface of top layer 15 may simply be the upper surface of substrate 11.
- Device 10 further comprises a gate insulator structures (30) that includes at least two or more layers.
- the first layer of the gate insulator structure (31) is composed entirely of gallium sulfide compounds and is directly adjacent to and deposited upon the compound semiconductor structure.
- the second layer of the gate insulator structure (32) is composed of a compound of gallium, sulphur, and one or more rare earth elements from the periodic table.
- the initial gallium sulphur layer (31) forms an atomically abrupt interface 14 with the upper surface of top layer 15, the top layer of the compound semiconductor structure.
- a refractory metal gate electrode 17 which is stable in the presence of top insulating material at elevated temperature is positioned on upper surface 18 of the gate insulator structure.
- Dielectric spacers 26 are positioned to cover the sidewalls of metal gate electrode 17.
- Source and drain contacts 19 and 20 are deposited on self-aligned source and drain areas 21 and 22, respectively.
- the compound semiconductor epitaxial layer structure consists of a ⁇ 11 angstrom GaAs top layer (15), a ⁇ 101 angstrom Al x Ga ⁇ -x As spacer layer (23), a ⁇ 251 angstrom In y Ga 1-y As channel layer (24), and a GaAs buffer layer (25) grown on a GaAs substrate (11).
- Top GaAs layer (15) is used to form an atomically abrupt layer with the gate insulator structure with an abrupt interface with low defect density.
- a III-V compound semiconductor wafer structure 13 with an atomically ordered and chemically clean upper surface of top layer 15 is prepared in an ultra-high vacuum semiconductor growth chamber and transferred via a ultra high vacuum transfer chamber to a second ultra high vacuum sulfide and insulator deposition chamber.
- the initial gallium sulphur layer (31) is deposited on upper compound semiconductor surface layer 15 using thermal evaporation from a high purity Ga 2 S 3 source or from crystalline gadolinium gallium sulphide, Ga 3 Gd 5 S ⁇ .
- This initial gallium sulphur layer is deposited while holding the substrate temperature of the compound semiconductor structure at ⁇ 500°C, and most preferably at a substrate temperature ⁇ 395°C.
- deposition of the second insulator layer is initiated. The deposition of the second insulator layer starts by directing the flux from a low power sulphur plasma source into the ultra high vacuum system such that the sulphur plasma effluent and species are largely directed toward and impinging upon said compound semiconductor structure with initial gallium sulphide layer.
- the flux from the sulphur plasma source should be directed at the surface for between 2-5 seconds, subsequently followed by the co-evaporation of gallium sulphur compounds from Ga 2 S 3 and a second thermal evaporation source that contains a rare- earth element.
- the flux beams from the sulphur source, Ga 2 S 3 and rare-earth evaporation source thermal evaporation sources are carefully balanced to provide a ternary insulator layer on top of the initial gallium sulphide layer on said compound semiconductor structure.
- the substrate temperature is simultaneously adjusted to provide an optimized substrate temperature for the deposition of this layer.
- the substrate temperature required to deposit the gallium+sulphur+rare earth layer is ⁇ 530°C.
- this second insulator layer proceeds until the total insulator thickness of 200-250 angstroms is achieved.
- Shutters and valves are utilized to stop the deposition of the ternary gallium+sulphur+rare earth layer upon the deposition of the required thickness of the insulator layer.
- the substrate temperature is cooled in- vacuum to ⁇ 200°C, and the deposition of a refractory metal which is stable and does not interdiffuse with on the top layer of the gate insulator structure at elevated temperature such as WSi or WN is deposited on upper surface 18 of sulfide layer 32 and subsequently patterned using standard lithography.
- the refractory metal layer is etched until sulfide layer 31 is exposed using a refractory metal etching technique such as a fluorine based dry etching process.
- the refractory metal etching procedure does not etch the sulfide layer 31, thus, sulfide layer 31 functions as an etch stop layer such that upper surface of top layer 15 remains protected by sulfide layer 31.
- All processing steps are performed using low damage plasma processing.
- Self-aligned source and drain areas 21 and 22, respectively are realized by ion implantation of Si (n-channel device) and Be/F or C/F (p-channel device) using the refractory metal gate electrode 17 and the dielectric spacers 26 as implantation masks.
- Such ion implantation schemes are compatible with standard processing of complementary compound semiconductor heterostructure FET technologies and are well known to those skilled in the art.
- the implants are activated at 700-900°C using rapid thermal annealing in an ultra high vacuum environment such that degradation of the interface 16 established between top layer 15 and sulfide layer 31 is completely excluded.
- ohmic source and drain contacts 19 and 20 are deposited on the self-aligned source and drain areas 21 and 22, respectively.
- the devices may then be interconnected using the standard methods to those skilled in the art of integrated microelectronics and integrated circuit manufacture.
- FIG. 2 is a simplified flow chart illustrating a method of manufacturing a self-aligned enhancement mode compound semiconductor MSSFET in accordance with a preferred embodiment of the present invention.
- a compound semiconductor wafer structure is produced using standard epitaxial growth methods in the art.
- a layer consisting of gallium sulphide compounds including but not limited to Ga 2 S 3 , Ga 2 S s GaS is deposited on upper surface of said compound semiconductor wafer structure.
- an insulating layer of gallium sulphide and one or more rare earth elements is deposited on the upper surface of the initial gallium sulphide compound layer.
- the gallium sulfide gate insulator structure is formed in steps 104 and 105.
- a stable refractory gate metal is positioned on upper surface of said gate insulator structure.
- source and drain ion implants are provided self-aligned to the gate electrode.
- source and drain ohmic contacts are positioned on ion implanted source and drain areas.
- step 100 provides a compound semiconductor substrate such as GaAs or InP.
- Step 102 includes the preparation and epitaxial growth of an atomically ordered and chemically clean upper surface of the compound semiconductor wafer structure.
- Step 103 preferably comprises thermal evaporation from a purified and crystalline gadolinium gallium sulphide or Ga 2 S 3 source on an atomically ordered and chemically clean upper surface of the compound semiconductor wafer structure.
- Step 104 comprises the formation of a gallium+sulphide+rare earth elemental insulating layer formed through the simultaneous vacuum evaporation of gallium sulphur species and at least one rare earth element such as Gadolinium with the simultaneous sulphidization using the effluent of an sulphur gas plasma source directed in simultaneous combination with other thermal evaporation sources toward substrate 100.
- the initial gallium sulphur compound layer of the gate insulator structure preferably functions as an etch stop layer such that the upper surface of the compound semiconductor wafer structure remains protected by the gate sulfide during and after gate metal etching.
- the refractory gate metal desirably does not react with or diffuse into the gate sulfide layer during high temperature annealing of the self-aligned source and drain ion implants.
- the quality of the interface formed by the gate sulfide layer and the upper surface of the compound semiconductor structure is desirably preserved during high temperature annealing of the self-aligned source and drain ion implants.
- the self-aligned source and drain implants are desirably annealed at approximately 700°C in an ultra high vacuum environment.
- the self-aligned source and drain implants are desirably realized by positioning dielectric spacers on the sidewalls of the refractory gate metal.
- the new and improved self-aligned enhancement mode metal- sulfide-compound semiconductor heterostructure field effect transistors enable stable and reliable device operation, provide optimum compound semiconductor device performance for low power/high performance complementary circuits and architectures, keep interconnection delay in ULSI under control, and provide optimum efficiency and output power for RF and microwave applications as well as for digital integrated circuits that require very high integration densities.
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002520314A JP2004507888A (en) | 2000-08-11 | 2001-08-10 | Metal sulfide semiconductor transistor element |
KR10-2003-7001950A KR20030027018A (en) | 2000-08-11 | 2001-08-10 | Metal sulfide semiconductor transistor devices |
EP01963936A EP1312123A4 (en) | 2000-08-11 | 2001-08-10 | Metal sulfide semiconductor transistor devices |
AU2001284850A AU2001284850A1 (en) | 2000-08-11 | 2001-08-10 | Metal sulfide semiconductor transistor devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/638,130 US6445015B1 (en) | 2000-05-04 | 2000-08-11 | Metal sulfide semiconductor transistor devices |
US09/638,130 | 2000-08-11 |
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WO2002015285A1 true WO2002015285A1 (en) | 2002-02-21 |
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PCT/US2001/025259 WO2002015285A1 (en) | 2000-08-11 | 2001-08-10 | Metal sulfide semiconductor transistor devices |
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US (1) | US6445015B1 (en) |
EP (1) | EP1312123A4 (en) |
JP (1) | JP2004507888A (en) |
KR (1) | KR20030027018A (en) |
AU (1) | AU2001284850A1 (en) |
WO (1) | WO2002015285A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7187045B2 (en) | 2002-07-16 | 2007-03-06 | Osemi, Inc. | Junction field effect metal oxide compound semiconductor integrated transistor devices |
US7190037B2 (en) | 2000-05-04 | 2007-03-13 | Osemi, Inc. | Integrated transistor devices |
US9245742B2 (en) | 2013-12-18 | 2016-01-26 | Asm Ip Holding B.V. | Sulfur-containing thin films |
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Cited By (12)
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US7190037B2 (en) | 2000-05-04 | 2007-03-13 | Osemi, Inc. | Integrated transistor devices |
US7187045B2 (en) | 2002-07-16 | 2007-03-06 | Osemi, Inc. | Junction field effect metal oxide compound semiconductor integrated transistor devices |
US9245742B2 (en) | 2013-12-18 | 2016-01-26 | Asm Ip Holding B.V. | Sulfur-containing thin films |
US9478419B2 (en) | 2013-12-18 | 2016-10-25 | Asm Ip Holding B.V. | Sulfur-containing thin films |
US9721786B2 (en) | 2013-12-18 | 2017-08-01 | Asm Ip Holding B.V. | Sulfur-containing thin films |
US10199213B2 (en) | 2013-12-18 | 2019-02-05 | Asm Ip Holding B.V. | Sulfur-containing thin films |
US10553424B2 (en) | 2013-12-18 | 2020-02-04 | Asm Ip Holding B.V. | Sulfur-containing thin films |
US10854444B2 (en) | 2013-12-18 | 2020-12-01 | Asm Ip Holding B.V. | Sulfur-containing thin films |
US9711350B2 (en) | 2015-06-03 | 2017-07-18 | Asm Ip Holding B.V. | Methods for semiconductor passivation by nitridation |
US10490475B2 (en) | 2015-06-03 | 2019-11-26 | Asm Ip Holding B.V. | Methods for semiconductor passivation by nitridation after oxide removal |
US9711396B2 (en) | 2015-06-16 | 2017-07-18 | Asm Ip Holding B.V. | Method for forming metal chalcogenide thin films on a semiconductor device |
US9741815B2 (en) | 2015-06-16 | 2017-08-22 | Asm Ip Holding B.V. | Metal selenide and metal telluride thin films for semiconductor device applications |
Also Published As
Publication number | Publication date |
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US6445015B1 (en) | 2002-09-03 |
EP1312123A1 (en) | 2003-05-21 |
JP2004507888A (en) | 2004-03-11 |
KR20030027018A (en) | 2003-04-03 |
AU2001284850A1 (en) | 2002-02-25 |
EP1312123A4 (en) | 2006-08-02 |
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