WO2001091390A3 - Pipelined and sliced shared-memory switch - Google Patents

Pipelined and sliced shared-memory switch Download PDF

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Publication number
WO2001091390A3
WO2001091390A3 PCT/US2001/016222 US0116222W WO0191390A3 WO 2001091390 A3 WO2001091390 A3 WO 2001091390A3 US 0116222 W US0116222 W US 0116222W WO 0191390 A3 WO0191390 A3 WO 0191390A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
sliced
words
pipelined
output port
memory units
Prior art date
Application number
PCT/US2001/016222
Other languages
French (fr)
Other versions
WO2001091390A2 (en )
Inventor
Jintae Oh
Taehee Lee
Chan Park
Hojae Lee
Dongbum Jung
Original Assignee
Engedi Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/104ATM switching fabrics
    • H04L49/105ATM switching elements
    • H04L49/108ATM switching elements using shared central buffer
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding through a switch fabric
    • H04L49/253Connections establishment or release between ports
    • H04L49/255Control mechanisms for ATM switching fabrics
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3081ATM peripheral units, e.g. policing, insertion or extraction
    • H04L49/309Header conversion, routing tables or routing tags
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5678Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679Arbitration or scheduling

Abstract

A pipelined switch fabric device has a plurality of memory units between a plurality of input ports and at least one output port. Each memory unit has multiplexer for sequentially receiving sliced words from at least one of the input ports, a buffer for temporarily storing the sliced words, and a de-multiplexer for transmitting the sliced words to at least one output port. The switch fabric device has a switch controller for selecting each of the memory units to receive each of the sliced words and for selecting at least one output port for each of the memory units to send each of the sliced words.
PCT/US2001/016222 2000-05-19 2001-05-17 Pipelined and sliced shared-memory switch WO2001091390A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US57491700 true 2000-05-19 2000-05-19
US09/574,917 2000-05-19

Publications (2)

Publication Number Publication Date
WO2001091390A2 true WO2001091390A2 (en) 2001-11-29
WO2001091390A3 true true WO2001091390A3 (en) 2002-04-18

Family

ID=24298171

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/016222 WO2001091390A3 (en) 2000-05-19 2001-05-17 Pipelined and sliced shared-memory switch

Country Status (2)

Country Link
KR (1) KR20010106079A (en)
WO (1) WO2001091390A3 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0516805D0 (en) * 2003-03-03 2005-09-21 Xyratex Tech Ltd Apparatus and method for switching data packets

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
US5905725A (en) * 1996-12-16 1999-05-18 Juniper Networks High speed switching device
US5910928A (en) * 1993-08-19 1999-06-08 Mmc Networks, Inc. Memory interface unit, shared memory switch system and associated method
US6031842A (en) * 1996-09-11 2000-02-29 Mcdata Corporation Low latency shared memory switch architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910928A (en) * 1993-08-19 1999-06-08 Mmc Networks, Inc. Memory interface unit, shared memory switch system and associated method
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
US6031842A (en) * 1996-09-11 2000-02-29 Mcdata Corporation Low latency shared memory switch architecture
US5905725A (en) * 1996-12-16 1999-05-18 Juniper Networks High speed switching device

Also Published As

Publication number Publication date Type
KR20010106079A (en) 2001-11-29 application
WO2001091390A2 (en) 2001-11-29 application

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