WO2001091390A3 - Pipelined and sliced shared-memory switch - Google Patents

Pipelined and sliced shared-memory switch Download PDF

Info

Publication number
WO2001091390A3
WO2001091390A3 PCT/US2001/016222 US0116222W WO0191390A3 WO 2001091390 A3 WO2001091390 A3 WO 2001091390A3 US 0116222 W US0116222 W US 0116222W WO 0191390 A3 WO0191390 A3 WO 0191390A3
Authority
WO
WIPO (PCT)
Prior art keywords
sliced
words
pipelined
output port
memory switch
Prior art date
Application number
PCT/US2001/016222
Other languages
French (fr)
Other versions
WO2001091390A2 (en
Inventor
Jintae Oh
Taehee Lee
Chan Park
Hojae Lee
Dongbum Jung
Original Assignee
Engedi Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Engedi Networks Inc filed Critical Engedi Networks Inc
Priority to AU2001263297A priority Critical patent/AU2001263297A1/en
Publication of WO2001091390A2 publication Critical patent/WO2001091390A2/en
Publication of WO2001091390A3 publication Critical patent/WO2001091390A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/108—ATM switching elements using shared central buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/255—Control mechanisms for ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H04L49/309—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling

Abstract

A pipelined switch fabric device has a plurality of memory units between a plurality of input ports and at least one output port. Each memory unit has multiplexer for sequentially receiving sliced words from at least one of the input ports, a buffer for temporarily storing the sliced words, and a de-multiplexer for transmitting the sliced words to at least one output port. The switch fabric device has a switch controller for selecting each of the memory units to receive each of the sliced words and for selecting at least one output port for each of the memory units to send each of the sliced words.
PCT/US2001/016222 2000-05-19 2001-05-17 Pipelined and sliced shared-memory switch WO2001091390A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001263297A AU2001263297A1 (en) 2000-05-19 2001-05-17 Pipelined and sliced shared-memory switch

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57491700A 2000-05-19 2000-05-19
US09/574,917 2000-05-19

Publications (2)

Publication Number Publication Date
WO2001091390A2 WO2001091390A2 (en) 2001-11-29
WO2001091390A3 true WO2001091390A3 (en) 2002-04-18

Family

ID=24298171

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/016222 WO2001091390A2 (en) 2000-05-19 2001-05-17 Pipelined and sliced shared-memory switch

Country Status (3)

Country Link
KR (1) KR20010106079A (en)
AU (1) AU2001263297A1 (en)
WO (1) WO2001091390A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004079961A2 (en) * 2003-03-03 2004-09-16 Xyratex Technology Limited Apparatus and method for switching data packets

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
US5905725A (en) * 1996-12-16 1999-05-18 Juniper Networks High speed switching device
US5910928A (en) * 1993-08-19 1999-06-08 Mmc Networks, Inc. Memory interface unit, shared memory switch system and associated method
US6031842A (en) * 1996-09-11 2000-02-29 Mcdata Corporation Low latency shared memory switch architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910928A (en) * 1993-08-19 1999-06-08 Mmc Networks, Inc. Memory interface unit, shared memory switch system and associated method
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
US6031842A (en) * 1996-09-11 2000-02-29 Mcdata Corporation Low latency shared memory switch architecture
US5905725A (en) * 1996-12-16 1999-05-18 Juniper Networks High speed switching device

Also Published As

Publication number Publication date
WO2001091390A2 (en) 2001-11-29
AU2001263297A1 (en) 2001-12-03
KR20010106079A (en) 2001-11-29

Similar Documents

Publication Publication Date Title
EP1449275A4 (en) Efficient multiple input multiple output system for multi; path fading channels
GB2414625B (en) Network interconnect crosspoint switching architecture and method
WO2005071554A3 (en) Method and apparatus for shared i/o in a load/store fabric
WO2005071553A3 (en) Method and apparatus for shared i/o in a load/store fabric
WO2004095286A3 (en) Method and apparatus for shared multi-bank memory in a packet switching system
WO2001094994A3 (en) A reconfigurable optical switch
WO2008029318A3 (en) Cluster coupler in a time triggered network
WO2003023602A1 (en) Data processing system and control method thereof
WO2010016889A3 (en) Flexible and expandable memory architectures
WO2001076141A3 (en) Switching fabric
CA2224606A1 (en) A distributed buffering system for atm switches
ZA200105385B (en) Impact-resistant sandwich structural element.
IT1316766B1 (en) CAN COMPACT VIDEO MONITORING DEVICE Y, Z, X COMPOSED AXES.
EP1284587A3 (en) Low-power reconfigurable hearing instrument
AU2001234309A1 (en) Input unit arrangement
NO20040838L (en) Signal transmission in a projection system, and such a projection system.
EP1146530A4 (en) Multidirectional input device
EP1126354A4 (en) Multidirectional input device
WO2003025737A1 (en) Operation apparatus and operation system
WO2003048953A3 (en) Method for determination of a separation from processor units to at least one reference position in a processor arrangement and processor arrangement
WO2005026970A3 (en) Multi-port device configuration
WO2001091390A3 (en) Pipelined and sliced shared-memory switch
WO2001084776A3 (en) Memory management with data discard
MXPA04002745A (en) Device and method for transmitting a plurality of signals by means of multi-stage protocol processing.
EP1357709A3 (en) A physical layer device having a serdes pass through mode

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 69(1) EPC DATED 04-03-2003

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP