WO2001084344A1 - Enhanced memory algorithmic processor architecture for multiprocessor computer systems - Google Patents
Enhanced memory algorithmic processor architecture for multiprocessor computer systems Download PDFInfo
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- WO2001084344A1 WO2001084344A1 PCT/US2001/008323 US0108323W WO0184344A1 WO 2001084344 A1 WO2001084344 A1 WO 2001084344A1 US 0108323 W US0108323 W US 0108323W WO 0184344 A1 WO0184344 A1 WO 0184344A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Definitions
- the present invention relates, in general, to the field of computer architectures incorporating multiple processing elements. More particularly, the present invention relates to a multiprocessor computer architecture incorporating a number of memory algorithmic processors ("MAP") in the memory subsystem or closely coupled to the processing elements to significantly enhance overall system processing speed.
- MAP memory algorithmic processors
- commodity microprocessors increase in capability there is an ever increasing push to use them in high performance multiprocessor systems capable of performing trillions of calculations per second at significantly lower cost than those made from custom counterparts.
- many of these processors lack specific features common to systems in this category that employ much more expensive custom processors.
- One such feature is the ability to perform vector processing.
- a data register or buffer is filled with operands forming what is called a vector. All of these operands are then passed one after the other through a functional unit capable of performing operations such as multiplication. This functional unit will output one result every clock cycle.
- This type of processing does require that the same operation be performed on all operands in the input vector and it is, therefore, widely used in that it exhibits much higher processing rates than the traditional scalar method of computation used in most microprocessors.
- the enhanced memory algorithmic processor architecture for multiprocessor computer systems of the present invention is an assembly that not only contains, for example, field programmable gate arrays functioning as the memory algorithmic processors, but also an operand storage, intelligent address generation, on board function libraries, result storage and multiple I/O ports. Like the original MAP architecture disclosed in the aforementioned patent applications, this architecture differs from other so called “reconfigurable" computers in many ways.
- its function is intended to be altered every few seconds distinguishing itself from other systems with very long reconfiguration times primarily intended for a single function.
- it contains dedicated hardware to provide for large data set operand storage (on the order of 16 Mbytes or more) allowing the MAP element to function autonomously from its host system once operands are loaded.
- it contains dedicated data ports to allow, but not require, multiple MAP elements to be chained together to perform very large operations. As currently contemplated, it is intended that typically 32 to 512 or more MAP sections can be connected in a single system.
- the MAP element is intended to augment, not replace, the high performance microprocessors in the system.
- it may be connected through the memory subsystem of the computer system resulting in it being very tightly coupled to the system as well as being globally accessible from any processor in the system.
- This technique was developed by SRC Computers, Inc. and distinguishes the MAP architecture from all other so called "attached array processor" systems that may exist today. While such "attached array processor" systems may bear some superficial similarities to MAP based systems, they are entirely separate units connected to the host computer through relatively slow interconnects resulting in lost system performance.
- MAP Memory Algorithmic Processor
- FPGA reconfigurable field programmable gate array
- FIFO first-in, first-out
- a MAP assembly comprising an intelligent address generator capable of supporting a data gather function from its associated input buffer or common memory.
- the MAP assembly may also comprise circuitry to allow the reconfigurable elements to reprogram their on-board configuration read only memory (“ROM”) devices to cause alterations in the functionality of the reconfigurable circuitry.
- ROM read only memory
- a MAP assembly comprising dedicated input and output ports for the purpose of allowing an infinite number of MAP elements to be chained together to accomplish a single function.
- the MAP assembly may also incorporate provisions to create a single MAP chain or multiple independent MAP chains automatically based on the contents of the reconfigurable circuitry.
- a MAP assembly comprising output FIFOs for the purpose of holding output data and allowing the MAP element to not stall in the event the processor reading these results is delayed due to outside factors such as workload or crossbar switch conflicts.
- the MAP assembly may further comprise relatively large dedicated input storage buffers to allow for optimization of operand transfer as well as allow multiple accesses to an operand without requiring external processor intervention.
- a MAP assembly comprising a dedicated port for connection to an input buffer so that the MAP element can simultaneously receive operands via the chained input (chain) port and the input buffer.
- reference data in the input buffer such as reciprocal look up tables
- a MAP assembly which may comprise connections to the memory subsystem of a high performance computer for the purpose of providing global access to it from all processors in a multiprocessor high performance computer system.
- the MAP assembly incorporates the capability to update multiple on board function ROMs under program control while in the system and may also include connections to the memory subsystem of a high performance computer utilizing DMA to accept commands from a microprocessor.
- Fig. 1 is a simplified, high level, functional block diagram of a multiprocessor computer architecture employing memory algorithmic processors ("MAP") in accordance with the disclosure of the aforementioned patent applications in an alternative embodiment wherein direct memory access (“DMA”) techniques may be utilized to send commands to the MAP elements in addition to data;
- MAP memory algorithmic processors
- DMA direct memory access
- Fig. 2 is a simplified logical block diagram of a possible computer application program decomposition sequence for use in conjunction with a multiprocessor computer architecture utilizing a number of MAP elements located, for example, in the computer system memory space, in accordance with a particular embodiment of the present invention
- Fig. 3 is a more detailed functional block diagram of an exemplary individual one of the MAP elements of the preceding figures and illustrating the bank control logic, memory array and MAP assembly thereof;
- Fig. 4 is a more detailed functional block diagram of the control block of the MAP assembly of the preceding illustration illustrating its interconnection to the user FPGA thereof in a particular embodiment
- Fig. 5 is a functional block diagram of an alternative embodiment of the present invention wherein individual MAP elements are closely associated with individual processor boards and each of the MAP elements comprises independent chain ports for coupling the MAP elements directly to each other;
- Fig. 6 is a functional block diagram of an individual MAP element wherein each comprises on board memory and a control block providing common memory DMA capabilities;
- Fig. 7 is an additional functional block diagram of an individual MAP element illustrating the on board memory function as an input buffer and output FIFO portions thereof;
- Fig. 8 is a more detailed functional block diagram of an individual MAP element as illustrated in Figs. 6 and 7;
- Fig. 9 is a user array interconnect diagram illustrating, for example, four user FPGAs interconnected through horizontal, vertical and diagonal buses to allow for expansion in designs that exceed the capacity of a single FPGA;
- Fig. 10 is a functional block diagram of another alternative embodiment of the present invention wherein individual MAP elements are closely associated with individual memory arrays and each of the MAP elements comprises independent chain ports for coupling the MAP elements directly to each other; and
- Figs. 1 1 A and 1 1 B are timing diagrams respectively input and output timing in relationship to the system clock ("Sysclk”) signal. DESCRIPTION OF A PREFERRED EMBODIMENT
- the multiprocessor computer 10 incorporates N processors 12 0 through 12 N which are bi-directionally coupled to a memory interconnect fabric 14.
- the memory interconnect fabric 14 is then also coupled to M memory banks comprising memory bank subsystems 16 0 (Bank 0) through 16M (Bank M).
- N number of memory algorithmic processors (“MAP") 1 12 0 through 1 12 N are also coupled to the memory interconnect fabric 14 as will be more fully described hereinafter.
- FIG. 2 a representative application program decomposition for a multiprocessor computer architecture 100 incorporating a plurality of memory algorithm processors in accordance with the present invention is shown.
- the computer architecture 100 is operative in response to user instructions and data which, in a coarse grained portion of the decomposition, are selectively directed to one of (for purposes of example only) four parallel regions 102 ⁇ through 102 4 inclusive.
- the instructions and data output from each of the parallel regions 102 1 through 102 4 are respectively input to parallel regions segregated into data areas 104- ⁇ through 104 and instruction areas 106 ⁇ through 106 4 .
- Data maintained in the data areas 104 ⁇ through 104 4 and instructions maintained in the instruction areas 106-j through 106 4 are then supplied to, for example, corresponding pairs of processors 108 ⁇ 108 2 (P1 and P2); 108 3 , 108 4 (P3 and P4); 108 5 , 108 6 (P5 and P6); and 108 7 , 108 8 (P7 and P8) as shown.
- processors 108 ⁇ 108 2 P1 and P2
- 108 3 , 108 4 P3 and P4
- 108 5 , 108 6 P5 and P6
- 108 7 , 108 8 P7 and P8
- a fine grained decomposition, or parallelism, is effectuated by a further algorithmic decomposition wherein the output of each of the processors 108 ⁇ through 108 8 , is broken up, for example, into a number of fundamental algorithms 1 10 1A , 1 10 ⁇ B . 1 10 2A , 1 10 2B through 1 1 0 8 B as shown.
- Each of the algorithms is then supplied to a corresponding one of the MAP elements 1 12 1 , 1 12 1 B , 1 12 2A , 1 12 2B , through 1 12 8B which may be located in the memory space of the computer architecture 100 for execution therein as will be more fully described hereinafter.
- Each memory bank 120 includes a bank control logic block 122 bi- directionally coupled to the computer system trunk lines, for example, a 72 line bus 124.
- the bank control logic block 122 is cou pled to a bi-directional data bus 126 (for example 256 lines) and supplies addresses on an address bus 128 (for example 17 lines) for accessing data at specified locations within a memory array 130.
- the data bus 126 and address bus 128 are also coupled to a MAP element 1 12.
- the MAP element 1 12 comprises a control block 132 coupled to the address bus 128.
- the control block 132 is also bi- directionally coupled to a user field programmable gate array ("FPGA") 134 by means of a number of signal lines 136.
- the user FPGA 134 is coupled directly to the data bus 126.
- the FPGA 134 may be provided as a Lucent Technologies OR3T80 device.
- the computer architecture 100 comprises a multiprocessor system employing uniform memory access across common shared memory with one or more MAP elements 1 12 which may be located in the memory subsystem, or memory space.
- each MAP element 1 12 contains at least one relatively large FPGA 134 that is used as a reconfigurable functional unit.
- a control block 132 and a preprogrammed or dynamically programmable configuration ROM contains the information needed by the reconfigurable MAP element 1 12 to enable it to perform a specific algorithm. It is also possible for the user to directly download a new configuration into the FPGA 134 under program control, although in some instances this may consume a number of memory accesses and might result in an overall decrease in system performance if the algorithm was short-lived.
- FPGAs have particular advantages in the application shown for several reasons.
- commercially available FPGAs now contain sufficient internal logic cells to perform meaningful computational functions.
- they can operate at speeds comparable to microprocessors, which eliminates the need for speed matching buffers.
- the internal programmable routing resources of FPGAs are now extensive enough that meaningful algorithms can now be programmed without the need to reassign the locations of the input/output ("I/O") pins.
- I/O input/output
- MAP element 1 12 can access the memory array 130 itself, referred to as Direct Memory Access ("DMA"'), allowing it to execute tasks independently and asynchronously of the processor. In comparison, were it placed near the processor, it would have to compete with the processors for system routing resources in order to access memory, which deleteriously impacts processor performance.
- DMA Direct Memory Access
- MAP element 1 12 has DMA capability, (allowing it to write to memory), and because it receives its operands via writes to memory, it is possible to allow a MAP element 1 12 to feed results to another MAP element 1 12. This is a very powerful feature that allows for very extensive pipelining and parallelizing of large tasks, which permits them to complete faster.
- the system of the present invention eliminates this problem.
- Multiprocessor computers often use software called parallelizers.
- the purpose of this software is to analyze the user's application code and determine how best to split it up among the processors.
- the present invention provides significant advantages over a conventional parallelizer and enables it to recognize portions of the user code that represent algorithms that exist in MAP elements 1 12 for that system and to then treat the MAP element 1 12 as another computing element.
- the parallelizer then automatically generates the necessary code to utilize the MAP element 1 12. This allows the user to write the algorithm directly in his code, allowing it to be more portable and reducing the knowledge of the system hardware that he has to have to utilize the MAP element 1 12.
- the control block 132 is coupled to receive a number of command bits (for example, 17) from the address bus 128 at a command decoder 150.
- the command decoder 150 then supplies a number of register control bits to a group of status registers iS2 on an eight bit bus 154.
- the command decoder 150 also supplies a single bit last operand flag on line 156 to a pipeline counter 158.
- the pipeline counter 158 supplies an eight bit output to an equality comparitor 160 on bus 162.
- the equality comparitor 160 also receives an eight bit signal from the FPGA 134 on bus 136 indicative of the pipeline depth.
- the equality comparitor 160 determines that the pipeline is empty, it provides a single bit pipeline empty flag on line 164 for input to the status registers 152.
- the status registers 152 are also coupled to receive an eight bit status signal from the FPGA 134 on bus 136and it produces a sixty four bit status word output on bus 166 in response to the signals on bus 136, 154 and line 164.
- the command decoder 150 also supplies a five bit control signal on line 168 to a configuration multiplexer (“MUX") 170 as shown.
- the configuration MUX 170 receives a single bit output of a 256 bit parallel- serial converter 172 on line 176. The inputs of the 256 bit parallel-to- serial converter 172 are coupled to a 256 bit user configuration pattern bus 174.
- the configuration MUX 170 also receives sixteen single bit inputs from the configuration ROMs (illustrated as ROM 182) on bus 178 and provides a single bit configuration file signal on line 180 to the user FPGA 134 as selected by the control signals from the command decoder 150 on the bus 168.
- the operating system will issue a last operand command to the MAP element 1 12 through the use of command bits embedded in the address field on bus 128.
- This command is recognized by the command decoder 150 of the control block 132 and it initiates a hardware pipeline counter 158.
- the algorithm was initially loaded into the FPGA 134, several output bits connected to the control block 132 were configured to display a binary representation of the number of clock cycles required to get through its pipeline (i.e. pipeline "depth") on bus 136 input to the equality comparitor 160.
- the pipeline counter 158 in the control block 132 counts clock cycles until its count equals the pipeline depth for that particular, algorithm.
- the equality comparitor 160 in the control block 132 de-asserts a busy bit on line 164 in an internal group of status registers 152.
- the processor 108 After issuing the last operand signal, the processor 108 will repeatedly read the status registers 152 and accept any output data on bus 166.
- the busy flag is de-asserted, the task can be stopped and the MAP element 1 12 utilized for a different task. It should be noted that it is also possible to leave the MAP element 1 12 configured, transfer the program to a different processor 108 and restart the task where it left off.
- the MAP element 1 12 may be equipped with internal registers in the control block 132 that allow it to monitor efficiency related factors such as the number of input operands versus output data, the number of idle cycles over time and the number of system monitor interrupts received over time.
- efficiency related factors such as the number of input operands versus output data, the number of idle cycles over time and the number of system monitor interrupts received over time.
- FIG. 5 a functional block diagram of a portion of an alternative embodiment of a computer system 20 in accordance with the of the present invention is shown.
- individual MAP elements 1 12 A , 1 12 B etc. are each closely associated with individual processor boards 22 A , 22 B respectively.
- each of the MAP elements 1 12 comprises independent chain ports 24 for coupling the MAP elements 1 12 directly to each other.
- Each of the memory subsystem banks 16 includes a control block 122 and one or more memory arrays 130.
- each MAP element 1 12 comprises an on board memory 40 and a control block 46 providing common memory DMA capabilities.
- the write trunk 26 and read trunk 28 are coupled to the control block 46 from the common memory switch which provides addresses to the memory 40 and receives addresses from the user array 42 on address lines 48.
- Data supplied on the write trunk 26 is provided by the control block 46 to the memory 40 on data lines 44 and data read out of the memory 40 is provided on these same lines both to the user array 42 as well as the control block 46 for subsequent presentation on the read trunk 28.
- the chain port 24 is coupled to the user array 42 for communication of read and write data directly with other MAP elements 1 12.
- FIG. 7 an additional functional block diagram of an individual MAP element 1 12 is shown particularly illustrating the memory 40 of the preceding figure functioning as an input buffer 40 and output FIFO 74 portions thereof.
- FIG. 6 an alternative view of the MAP element 1 12 of Fig. 6 is shown in which memory input data on line 50 (or the write trunk 26) is supplied to an input buffer (memory 40) as well as to a reconfigurable user array 42 coupled to the chain port 24.
- the output of the reconfigurable array 42 is supplied to an output FIFO 74 to provide memory output data on line 94 (or the read trunk 28) as well as to the chain port 24.
- the input buffer 40, reconfigurable array 42 and output FIFO 74 operate under the control of the control block 46.
- each MAP element 1 12 may consist of a printed circuit board containing input operand storage (i.e. the memory/input buffer 40), user array 42, intelligent address generator control block 46, output result storage FIFO 74 and I/O ports to allow connections to other MAP elements 1 12 through the chain port 24 as well as the host system memory array.
- input Operand Storage The input storage consists of memory chips that are initially loaded by memory writes from one of the microprocessors 12 in the host system or by MAP DMA.
- the buffer 40 may be, in a particular embodiment, 72 bits wide and 2M entries deep. This allows for storage of 64 bit operands and 8 error correction code (“ECC”) bits for data correction if needed.
- Operands or reference data can be read from this buffer 40 by the user array 42. Data is not corrupted after use allowing for operand reuse by the MAP elements 1 12. By reading operands only after the buffer 40 is loaded, operands do not need to arrive at the MAP elements 1 12 in time order. MAP elements 1 12 only require that store order be maintained thus allowing for out-of-order arrival of operands prior to storage in the input buffer 40. This means cache line transfers, which typically can not be performed in a timed order but have four times the bandwidth of un-cached transfers, can be used to load the input buffers 40.
- the input buffer 40 contents are accessed by providing address and read enable signals to it from the control block 46. These addresses may be generated in one of two ways. First the address bits can be provided by the programmable user array 42 to the address generator control block 46 where it is combined with other control signals and issued to the input buffer 40. This allows for very random access into the buffer 40 such as would be needed to access reference data. Another address mode requires the user to issue a start command which contains a start address, stop address, and stride. The address generator control block 46 will then start accessing the input buffer 40 at the start address and continue accessing it by adding the stride value to the last address sent until the stop address is reached. This is potentially a very useful technique when performing vector processing where like elements are extracted out of an array. Since the stride can be any number less than the delta between the start and stop addresses, it is very easy for the MAP element 1 12 to perform a data gather function which is highly valuable in the high performance computing market.
- the array 42 performs the actual computational functions of the MAP element 1 12. It may comprise one or more high performance FPGAs interconnected to the other elements of the MAP element 1 12. A particular implementation of the present invention disclosed in more detail hereinafter, may use four such devices yielding in excess of 500,000 usable gates. These components are configured by user commands that load the contents of selected configuration ROMs into the FPGAs. After configuration, the user array 42 can perform whatever function it was programmed to do. In order to maximize its performance for vector processing, the array 42 should be able to access two streams of operands simultaneously. This is accomplished by connecting one 72 bit wide input port to the input operand storage and a second 72 bit wide port to the chain input connector port 24.
- This connector allows the MAP element 1 12 to use data provided to it by a previous MAP element 1 12.
- the chain port 24 allows functions to be implemented that would far exceed the capability of a single MAP element 1 12 assembly. In addition, since in the particular implementation shown, only operands are transferred over the chain port 24, the bandwidth may exceed the main memory bandwidth resulting in superior performance to that of the fixed instruction microprocessor-based processors 12.
- the FPGAs may also contain on board phase locked loops ("PLLs") that allow the user to specify at what multiple or sub-multiple of the system clock frequency the circuit will run. This is important because certain complex functions may require clocks that are slower than the system clock frequency. It may also be that the user desires to synthesize a function resulting in lower performance but faster time to market. By using PLLs, both of these constraints can be accommodated. Another benefit in the potential utilization of a PLL is that future generation FPGAs that can operate faster than the current system clock speeds can be retrofitted into slower systems and use the PLL frequency multiplication feature to allow the MAP element 1 12 to run faster than the rest of the system. This is turn results in a higher performance MAP element 1 12. Output Result Storage
- output FIFO 74 When the user array 42 produces a result, it may be sent over a 72 bit wide path to an output result storage element (for example, output FIFO 74) which can then pass the data to either a 72 bit wide read port or a 72 bit wide chain port 24 to the next MAP element 1 12.
- This storage device can made from a number of different memory types. The use of a FIFO 74 storage device will temporarily hold results that cannot be immediately read by a host microprocessor or passed over the output chain port 24 to the next stage. This feature allows for MAP elements 1 12 in a chain to run at different frequencies. In this case the output FIFO 74 functions like a speed matching buffer. In non-chained operation, the microprocessor that is reading the results may be delayed.
- the FIFO 74 prevents the MAP element 1 12 from "stalling" while waiting for results to be read.
- a FIFO 74 that is 72 bits wide and 512K entries deep may be utilized.
- the output storage may also be a true memory device such as those found in common memory.
- write addresses must be provided by the user array 42 or address generator and read addresses provided by the entity reading the results from the memory. While this may be somewhat more electrically complicated, it has the advantage that results may be accessed in any order.
- EEPROMs electrically erasable programmable ROMs
- EEPROMs electrically erasable programmable ROMs
- the user array 42 function can be changed very rapidly.
- the user program can download a new function into one of the on board ROMs thus updating its contents and allowing the MAP element 1 12 to perform new functions.
- this may be accomplished by reserving one of the library functions to perform the function of an EEPROM programmer.
- the user array 42 may be configured with this special function and data read from the MAP element 1 12 input storage (e.g. input buffer 40) and then loaded into the ROMs to complete the update process.
- MAP element 1 12 includes an enhanced synchronous dynamic random access memory (ESDRAMTM, a trademark of Enhanced Memory
- ESDRAM memory is a very high speed memory device incorporating a dynamic random access memory (“DRAM”) array augmented with an on-chip static random access memory (“SRAM”) row register to speed device read operations.
- DRAM dynamic random access memory
- SRAM static random access memory
- Memory input data on lines 50 is supplied through transmission gates 52 to the data lines 44 for provision to the memory 40 and user array 42.
- address input is received on lines 54 for provision through transmission gates 56 to the address lines 48 coupled to the memory 40 and control block 46.
- the control block 46 operatively controls the transmission gates 52, 56 and receives an FS1 1 signal on line 60 and provides a LOCKOUT signal on line 62.
- the user array 42 may be coupled, as shown, to the chain port 24 and it provides a user address signal on lines 64 and a next address signal on lines 66 to the control block 46.
- the control block 46 provides an indication of whether or not an input is valid to the user array 42 on lines 68.
- Output of the user array 42 is provided on lines 70 together with a write clock ("WRTCLK”) signal on line 72 to the FIFO 74 or other output storage device.
- the FIFO 74 receives a read clock (“RDCLK”) signal on line 78 from the control block 46.
- Output from the FIFO 74 or control block 46 may be selectively supplied on lines 80 through transmission gates 76 to the chain port 24 and/or through transmission gates 82 to provide memory data on lines 94.
- the control block 46 also receives a chain read signal on lines 90 and returns a chain valid output on lines 92.
- the control block 46 operatively controls the transmission gates 76 and 82 in addition to transmission gates 86 which serve to provide error correction code ("ECC") output signals on lines 88.
- ECC error correction code
- the MAP elements 1 12 may comprise one or more circuit boards, utilizing, for example, one Lucent OrcaTM OR3T80 FPGA to function as the control block 46 and, four OR3TI25 FPGAs forming the user array 42. The user can implement algorithms in these FPGAs that alter data that is written to it and provide this altered data when the MAP element 1 12 is then read.
- each MAP element 1 12 may also comprise eight sets of four configuration ROMs on board.
- ROMs are preprogrammed by the user and configure the four user FPGAs of the user array 42 under program control. These ROMs may be reprogrammed either externally or while on the MAP element 1 12 located in a system.
- the MAP elements 1 12 are accessed through the use of normal memory READ and WRITE commands, in the representative embodiment illustrated and described, the user can provide operands to the MAP elements 1 12 either by directly writing 128-bit packets (i.e. in the form of two 64-bit words) into the user array 42 chips or by writing 256-bit packets (in the form of four 64-bit words) into a dedicated 16-MB ESDRAM memory input data buffer 40.
- a read from a MAP element 1 12 always returns a 2-word packet and part of this returned packet contains status information as will be more fully described hereinafter.
- the incoming addresses are decoded into commands as will also be defined later.
- MAP elements 1 12 also have the ability to be chained via hardware. This allows the output data from one MAP element 1 12 to move directly to the user array 42 chips of the next MAP element 1 12 without processor 12 intervention. Chain length is limited by the quantity of MAP elements 1 12 in the overall system. The total number of MAP elements 1 12 may also be broken down into several smaller independent chains. In a chained mode of operation, a MAP element 1 12 can still read from its input buffer 40 to access reference information such as reciprocal approximation tables. Logic Conventions
- the processors 12 may comprise PentiumTM (Intel Corporation, Santa Clara, CA) processors. These devices utilize an active "low" logic convention which applies to all address bits and data words transmitted to or from the MAP elements 1 12 including the returned status word.
- PentiumTM Intel Corporation, Santa Clara, CA
- a user array interconnect 200 diagram is shown, for example, utilizing four user FPGAs interconnected through horizontal, vertical and diagonal buses to allow for expansion in designs that might exceed the capacity of a single FPGA.
- the interconnect diagram 200 corresponds to the user array 42 of the preceding figures with input data bus 210 corresponding to the data lines 44, the chain input bus 212 corresponding to the chain port 24 and the output bus 214 corresponding to the lines 70 of Fig. 8.
- the four FPGAs 202, 204, 206 and 208 comprising the user array 42 are each coupled to the input data bus 210, chain input bus 212 and output bus 214 as well as to each other by means of top bus 216, right bus 218, bottom bus 220, left bus 222 and diagonal buses 224 and 226.
- the four user FPGAs (202, 204, 206 and 208) are interconnected through a series of horizontal, vertical, and diagonal buses which allow the easiest expansion of the existing symmetric internal chip routing for designs that exceed the capacity of a single FPGA for the user array 42.
- bus sizes were chosen to utilize as many pins as possible while maintaining a bus width of at least 64 bits.
- MAP may be located in the memory array of the system and decodes a portion of the address field, the address generated by the processor 12 must be correctly assembled.
- Table 1 shows the address bit allocation as seen by the processor 12 and the MAP element 1 12 board.
- the processor board bridge elements will reallocate the bit positions that are actually transmitted to the MAP element 1 12 based on system size.
- the Field Select bits are the two most significant address bits leaving the bridge elements and are used to select which of the four possible mezzanine cards in the memory stack is being accessed.
- the Field Select bits for all mezzanine cards are determined by the state of P6 bus bits A[21 :20]. If bit A21 is set, a MAP element 1 12 operation is underway and the Field Select bits are set to 11.
- the MAP element 1 12 is always located just above the semaphore registers with the first MAP element 1 12 in segment 0 bank 0, the second in segment 1 bank 0 and so on until one MAP element 1 12 is each segment's bank 0. They are then placed in segment 0 bank 1 and the same pattern is followed until all are placed. This keeps them in a continuous address block.
- Chip Select bits These normally select which one of the eight rows of memory chips on a mezzanine board are activated.
- Chip Selects 0 and 1 are used.
- Chip Select 0 is used to write to the ESDRAM memory input buffer 40 and Chip Select 1 is used to access the control block 46 and user chips of the user array 42.
- the next 19 most significant bits on the P6 bus are Memory Address bits that normally select the actual location within the memory chip of the cache line in use. Five of these bits are decoded by the MAP element 1 12 into various commands that are discussed in greater detail hereinafter.
- the next 4 most significant bits are the Bank Select bits. These bits are used to select the specific bank within a segment in which the desired memory or MAP element 1 12 is located.
- Trunk Select bits The next 4 most significant bits are the Trunk Select bits. The number of these bits range from 0 to 4 depending upon the number of segments in the system. These bits are used to select the segment that contains the desired memory or MAP. Unused bits are set to 0.
- the next 2 most significant bits are the Word Select bits. These bits determine the order in which each word of a 4-word cache line is being used. With CS[1 :0] set to 01 , these bits are part of the decoded command.
- CMD[3:0] are decoded into the following commands by the MAP control block 46 chip when CS[1 :0] are 01 as shown in the following Table 2. This decode is also dependant upon the transaction being either a READ or WRITE.
- SEL[2:0] are used in conjunction with the RECON and LDROM commands described hereinafter to select which one of the eight ROM's is to be used.
- This command causes the control block 46 chips to generate a global set reset ("GSR") to the user chips of the user array 42 and reprograms the control chips. All internal latches are reset but the configuration of the user chip is not changed. Any data that was waiting to be read will be lost.
- GSR global set reset
- This command causes the control chips to generate GSR signal to all four user FPGAs of the user array 42. All internal latches are reset, but the configuration is not changed. Any operands will be lost, but data waiting to be read in the control block 46 chips will not.
- This command causes the control chips to reconfigure the four user FPGAs of the user array 42 with the ROM selected by SEL[2:0]. Any operands still in process will be lost, but data waiting to be read in the control chip will not.
- This command is issued during a write transaction to inform the MAP element 1 12 control block 46 chip that no more operands will be sent and the pipeline should be flushed.
- the control chips start the pipeline counter and continue to provide read data until the pipeline depth is reached.
- MAP element 1 12 control block 46 chip that it is receiving a valid operand to be forwarded directly to the user circuits.
- This command is issued during a write transaction to inform the MAP element 1 12 control block 46 chip that the processor 12 is done using the MAP element 1 12.
- the control chips reset the busy bit in the status word and wait for a new user. The configuration currently loaded into the user circuits is not altered.
- This command is issued during a write transaction and sends the start address, stop address, auto/user selection and stride to input controller.
- the input controller then takes control of input buffer 40 and starts transferring operands to the user chips of the user array 42 using these parameters until the stop address is hit.
- the data word 0 that accompanies this instruction contains the start address in bits 0 through 20, the stop address in bits 23 through 43, the stride in bits 46 through 51 and the user/auto bit in bit position 54. In all cases the least significant bit (“LSB”) of each bit group contains the LSB of the value.
- This command is issued during a read transaction to cause a status word to be returned to the processor 12. This transaction will not increment the pipeline counter if it follows a LASTOP command. Details of the status word are shown in the following Table 4.
- This command is issued during a read transaction to cause 2 data words to be returned to the processor 12. This transaction will increment the pipeline counter if it follows a LASTOP command. Details of the status word are also shown in Table 4.
- This command is issued during a read transaction to cause a status word and data word to be returned to the processor 12.
- SEL[2:0] Decode The SEL[2:0] bits are used for two purposes. When used in conjunction with the RECON or LDROM commands, they determine which of the eight on-board ROM sets are to be used for that instruction. This is defined in the following Table 3.
- Bit 63 is always the most significant bit (“MSB”) as indicated in the following illustration: r 63 0 j
- Normal operation of the MAP elements 1 12 are as follows. After power up, the MAP element 1 12 control block 46 chip automatically configures and resets itself. No configuration exists in the four user chips of the user array 42. A processor 12 that wants to use a MAP element 1 12 first sends an RDSTAT command to the MAP element 1 12.
- the status word is returned with bit 63 "0" (not busy) and the busy bit is then set to 1 on the MAP element 1 12. Any further RDSTAT or RDDAST commands show MAP element 1 12 to be busy.
- the processor 12 After evaluating the busy bit and observing it to be "low", the processor 12 issues a RECON command along with the appropriate configuration ROM selection bits set. This causes the MAP element 1 12 to configure the user chips of the user array 42. While this is happening, status bit 60 is "low”. The processor 12 issues an RDSTAT and evaluates bit 60 until it returns "high”. At this point, configuration is complete and the user chips of the user array 42 have reset themselves clearing all internal registers. The user then issues an RUC command to ensure that any previous data left in the user array 42 or control block 46 circuits has been cleared.
- this buffer may comprise 2M quad words of ESDRAM memory storage. This memory is located on the MAP element 1 12 and is accessed by performing cache line writes. This allows the loading of four 64-bit words per transaction. Once the data set is loaded, a START command is issued.
- the control block 46 chip will assert the lockout bit signaling the memory controller not to access the input buffer 40. It will also evaluate data word "0" of this transaction in accordance with the previously defined fields. If the Auto/User bit is a "1 ", the addresses will automatically be generated by the control block 46 chip. The first address will be the start address that was transferred. The address is then incremented by the stride value until the stop address is hit. This address is the last address accessed.
- the input control chip must interleave accesses to the input buffer 40 with refresh signals provided by the memory controller in order to maintain the ESDRAM memory while the lockout bit is set.
- the processor 12 can start to read the output data.
- the user must first issue a RDDAST, which will return a status word and a data word. If bit 61 of the status word is a 1 , the data word is valid. The user will continue this process until status word bit 62 is a 1 .
- the user knows that the output FIFO 74 on the MAP element 1 12 contains at least 128 valid data words and the RDDAT command can now be used for the next 64 reads. This command will return two valid data words without any status.
- the user must again issue a RDDAST command and check bits 61 and 62. If neither is set, the FIFO 74 has no further data. If only 61 is set the program should continue to issue RDDAST commands to empty the FIFO 74. If 61 and 62 are set, the program can resume with another set of 64 RDDAT commands and repeat the process until all results are received.
- MAP elements 1 12 have the ability to run in a vectored or VMAPTM mode (VMAP is a trademark of SRC Computers, Inc., assignee of the present invention).
- VMAP is a trademark of SRC Computers, Inc., assignee of the present invention.
- This mode allows the output data from one MAP element 1 12 to be sent directly to the user chips in the user array 42 of the next MAP element 1 12 with no processor 12 intervention.
- this link, or chain port 24 operates at up to 800 MB/sec and connects all MAP elements 1 12 in a system in a chain.
- a chain must consist of a sequential group of at least two MAP elements 1 12 and up to as many as the system contains. Multiple non-overlapping chains may coexist.
- VMAP mode operation is identical to single MAP element 1 12 operation except the data buffer 40 on the first MAP element 1 12 in the chain is loaded with data and all results are read from the last MAP element 1 12.
- Chained MAP elements 1 12 simultaneously read from their input buffer 40 while accepting operands from the chainin port. This allows the buffers 40 used to supply reference during chained operation. To do this the input buffers 40 must first be loaded and then START commands must be sent to all MAP elements in the chain.
- the first MAP element 1 12 in the chain must be the last one to receive a START command. All MAP elements 1 12 other than the first in the chain must receive a START command with the user address mode selected.
- MAP elements 1 12 have the capability to allow the contents of an on-board ROM to be externally reloaded while the system is operating, thus changing the algorithm. It should be noted that the same ROM for all four user chips in the user array 42 will simultaneously be updated.
- the configuration files of the four ROMs of a given set are converted from a serial stream to 16-bit words.
- the first words of each ROM file are then combined to form a 64-bit word.
- User chip 0 of the user array 42 files fill bits 0 through 15, chip 1 is 16 through 31 , chip 2 is 31 through 47, and chip 3 is 48 through 64. This process is repeated until all four of the individual files are consumed. This results in a file that is 64-bits wide and 51 ,935 entries deep.
- the input controller Upon receiving an LDROM command, the input controller will load the user chips of the user array 42 with a special algorithm that turns them into ROM programmers. These chips will then start accessing the data in the input buffer 40 and will evaluate word 0.
- bit 60 of the status word is 0. When complete, bit 60 will return to a 1 .
- FIG. 10 a functional block diagram of another alternative embodiment 230 of the present invention is shown wherein individual MAP elements 1 12 are closely associated with individual memory arrays and each of the MAP elements 1 12 comprises independent chain ports 24 for coupling the MAP elements 1 12 directly to each other.
- the system illustrated comprises a processor assembly comprising one or more processors 12 bi-directionally coupled through a processor switch (which may comprise an FPGA) to a write trunks 26 and read trunks 28.
- a number of MAP elements 1 12 are associated with a particular memory array 246 under control of a memory controller 238 (which may also comprise an FPGA).
- a memory controller 238 which may also comprise an FPGA.
- each of the memory controllers 238 A and 238 B are coupled to the processor assembly 232 through the processor switch 234 by means of the write and read trunks 26, 28.
- Each of the memory controllers may be coupled to a plurality of MAP elements 1 12 and associated memory array 246 and to additional MAP elements 1 12 by means of a chain port 24 as previously described.
- memory controller 238 A is in operative association with a pair of MAP elements, the first comprising buffer 240 A ⁇ , user array 242 A ⁇ and FIFO 244 A ⁇ associated with memory array 246 A ⁇ and the second comprising buffer 240 A2 , user array 242 A2 and FIFO 244 A2 associated with memory array 246 A2 .
- memory controller 238 B is in operative association with a pair of MAP elements, the first comprising buffer 240 B ⁇ , user array 242 B ⁇ and FIFO 244 B ⁇ associated with memory array 246 B ⁇ and the second comprising buffer 240 B2 , user array 242 B2 and FIFO 244 B2 associated with memory array 246 B2 .
- Fig. 1 1 A and 1 1 B separate timing diagrams are illustrated respectively depicting input and output timing in relationship to the system clock (“Sysclk”) signal.
- Interface Timing
- the MAP element 1 12 user array 42 can accept data from the input memory bus, input buffer 40 or the chain port 24. In the embodiment of the present invention previously described and illustrated, all sixty four bits from any of these sources are sent to all four of the user chips (202, 204, 206 and 208; Fig. 9) along with a VALID I N signal on lines 68 (Fig. 8) sent from the control block 46 that enables the input clock in the user chips of the user array 42.
- This signal stays high for ten, twenty or forty nanoseconds depending on whether one, two or four words are being transferred.
- This VALID I N signal on lines 68 connects to the clock enable pins of input latches in the user chips of the user array 42. These latches then feed the user circuit in the MAP element 1 12. The timing for the various write operations is shown in with particularity in Figure 1 1 A. input Timing
- output data is formed into 64-bit words-in the user chips of the user array 42 on pins connected to the DOUT[00:63] nets. These nets, in turn, connect to the output FIFO 74 (Fig. 8) that ultimately provides the read data to the memory controller or the next MAP element 1 12 in the chain.
- the user circuitry After forming the 64-bit result, the user circuitry must ensure that a "FULL" signal is “low”. When the signal is "low”, the transfer is started by providing a "low” from the user array 42 to the control block 46 and the FIFO#WE input on the FIFO 74. At the same time, valid data must appear on the data out
- the output FIFO 74 (Fig. 8) is capable of holding 512k words in the embodiment illustrated. When three words are held in the control block 46, the word counter in the status word will indicate binary "1 1 ".
- the user array 42 must also provide the pipeline depth of the algorithm to the control block 46. In a particular embodiment of the present invention, this will be equal to the number of 100-MHz clock cycles required to accept a data input word, process that data, and start the transfer of the results to the FIFO 74.
- the pipeline depth is equal only to the number of clock cycles required to process the operands. This depth is provided as a static 8-bit number on nets DOUT[64:71 ] from FPGAs 202 and/or 204 (Fig. 9). Each of the eight bits are generally output from only of the FPGAs of the user array 42 but the eight bits may be spread across both chips.
- the ROMs that are used on the MAP elements 1 12 may be conveniently provided as ATMELTM AT17LVO1 O in a 20-pin PLCC package. Each ROM contains the configuration information for one of the four user FPGAs of the user array 42.
- ROM sockets allocated to each of the user chips of the user array 42 to allow selection of up to eight or more unique algorithms.
- the first ROM listed for each of the four user chips may be selected by choosing configuration Oh and the last ROM selected by choosing configuration 8h. If all four user chips of the user array 42 are not needed for an algorithm, the unused chips do not require that their ROM sockets be populated. However, at least one of the user chips must always contain a correctly programmed ROM even if it is not used in the algorithm because signals related to the configuration timing cycle are monitored by the control block.
- the user FPGA that directly connects to both the DIN and DOUT signals, should always be used first when locating the algorithm circuit.
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Abstract
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Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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AU4576101A AU4576101A (en) | 2000-05-03 | 2001-03-16 | Enhanced memory algorithmic processor architecture for multiprocessor computer systems |
EP01918715A EP1297441A4 (en) | 2000-05-03 | 2001-03-16 | Enhanced memory algorithmic processor architecture for multiprocessor computer systems |
JP2001580696A JP2003532224A (en) | 2000-05-03 | 2001-03-16 | Advanced memory algorithmic processor architecture for multiprocessor computer systems |
CA002403675A CA2403675A1 (en) | 2000-05-03 | 2001-03-16 | Enhanced memory algorithmic processor architecture for multiprocessor computer systems |
AU2001245761A AU2001245761B2 (en) | 2000-05-03 | 2001-03-16 | Enhanced memory algorithmic processor architecture for multiprocessor computer systems |
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US09/563,561 US6339819B1 (en) | 1997-12-17 | 2000-05-03 | Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer |
US09/563,561 | 2000-05-03 |
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EP (1) | EP1297441A4 (en) |
JP (1) | JP2003532224A (en) |
AU (2) | AU2001245761B2 (en) |
CA (1) | CA2403675A1 (en) |
WO (1) | WO2001084344A1 (en) |
Families Citing this family (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5915123A (en) * | 1997-10-31 | 1999-06-22 | Silicon Spice | Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements |
US7197575B2 (en) * | 1997-12-17 | 2007-03-27 | Src Computers, Inc. | Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers |
US7003593B2 (en) * | 1997-12-17 | 2006-02-21 | Src Computers, Inc. | Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port |
TW449677B (en) * | 1999-07-19 | 2001-08-11 | Novatek Microelectronics Corp | Device and method for rewritable monitor function |
US6438737B1 (en) * | 2000-02-15 | 2002-08-20 | Intel Corporation | Reconfigurable logic for a computer |
US7139743B2 (en) | 2000-04-07 | 2006-11-21 | Washington University | Associative database scanning and information retrieval using FPGA devices |
US6711558B1 (en) | 2000-04-07 | 2004-03-23 | Washington University | Associative database scanning and information retrieval |
US8095508B2 (en) * | 2000-04-07 | 2012-01-10 | Washington University | Intelligent data storage and processing using FPGA devices |
US6515914B2 (en) * | 2001-03-21 | 2003-02-04 | Micron Technology, Inc. | Memory device and method having data path with multiple prefetch I/O configurations |
US20090161568A1 (en) * | 2007-12-21 | 2009-06-25 | Charles Kastner | TCP data reassembly |
US20090006659A1 (en) * | 2001-10-19 | 2009-01-01 | Collins Jack M | Advanced mezzanine card for digital network data inspection |
US7716330B2 (en) * | 2001-10-19 | 2010-05-11 | Global Velocity, Inc. | System and method for controlling transmission of data packets over an information network |
US6836823B2 (en) * | 2001-11-05 | 2004-12-28 | Src Computers, Inc. | Bandwidth enhancement for uncached devices |
JP4143302B2 (en) * | 2002-01-15 | 2008-09-03 | キヤノン株式会社 | Image processing apparatus, image processing method, control program, and recording medium |
US7406573B2 (en) * | 2002-05-09 | 2008-07-29 | Src Computers, Inc. | Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements |
US20030212853A1 (en) * | 2002-05-09 | 2003-11-13 | Huppenthal Jon M. | Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core |
US7711844B2 (en) * | 2002-08-15 | 2010-05-04 | Washington University Of St. Louis | TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks |
US7225324B2 (en) | 2002-10-31 | 2007-05-29 | Src Computers, Inc. | Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions |
US8354450B2 (en) | 2003-05-15 | 2013-01-15 | Vireo Systems, Inc. | Creatine oral supplementation using creatine hydrochloride salt |
US10572824B2 (en) | 2003-05-23 | 2020-02-25 | Ip Reservoir, Llc | System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines |
AU2004273406A1 (en) | 2003-05-23 | 2005-03-24 | Data Search Systems, Inc. | Intelligent data storage and processing using FPGA devices |
US8194855B2 (en) * | 2003-06-30 | 2012-06-05 | Oracle America, Inc. | Method and apparatus for implementing processor instructions for accelerating public-key cryptography |
US7602785B2 (en) * | 2004-02-09 | 2009-10-13 | Washington University | Method and system for performing longest prefix matching for network address lookup using bloom filters |
US7921323B2 (en) * | 2004-05-11 | 2011-04-05 | L-3 Communications Integrated Systems, L.P. | Reconfigurable communications infrastructure for ASIC networks |
US20050288800A1 (en) * | 2004-06-28 | 2005-12-29 | Smith William D | Accelerating computational algorithms using reconfigurable computing technologies |
EP1784719A4 (en) * | 2004-08-24 | 2011-04-13 | Univ Washington | Methods and systems for content detection in a reconfigurable hardware |
US7299339B2 (en) | 2004-08-30 | 2007-11-20 | The Boeing Company | Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework |
US7765250B2 (en) | 2004-11-15 | 2010-07-27 | Renesas Technology Corp. | Data processor with internal memory structure for processing stream data |
WO2006096324A2 (en) * | 2005-03-03 | 2006-09-14 | Washington University | Method and apparatus for performing biosequence similarity searching |
US7478222B2 (en) * | 2005-03-29 | 2009-01-13 | Karl M. Fant | Programmable pipeline array |
US8966223B2 (en) * | 2005-05-05 | 2015-02-24 | Icera, Inc. | Apparatus and method for configurable processing |
US7702629B2 (en) * | 2005-12-02 | 2010-04-20 | Exegy Incorporated | Method and device for high performance regular expression pattern matching |
US7954114B2 (en) * | 2006-01-26 | 2011-05-31 | Exegy Incorporated | Firmware socket module for FPGA-based pipeline processing |
US7921046B2 (en) | 2006-06-19 | 2011-04-05 | Exegy Incorporated | High speed processing of financial information using FPGA devices |
US8326819B2 (en) | 2006-11-13 | 2012-12-04 | Exegy Incorporated | Method and system for high performance data metatagging and data indexing using coprocessors |
WO2008061162A1 (en) * | 2006-11-14 | 2008-05-22 | Star Bridge Systems, Inc. | Hybrid computing platform having fpga components with embedded processors |
US10229453B2 (en) | 2008-01-11 | 2019-03-12 | Ip Reservoir, Llc | Method and system for low latency basket calculation |
US8374986B2 (en) | 2008-05-15 | 2013-02-12 | Exegy Incorporated | Method and system for accelerated stream processing |
CA3059606C (en) | 2008-12-15 | 2023-01-17 | Ip Reservoir, Llc | Method and apparatus for high-speed processing of financial market depth data |
US8191072B2 (en) * | 2008-12-22 | 2012-05-29 | International Business Machines Corporation | System and method for shifting workloads across platform in a hybrid system |
US8458466B2 (en) | 2008-12-22 | 2013-06-04 | International Business Machines Corporation | System and method for handling cross-platform system call in a hybrid system |
US8621207B2 (en) * | 2008-12-23 | 2013-12-31 | International Business Machines Corporation | System and method for handling cross-platform system call with shared page cache in hybrid system |
US8938609B2 (en) * | 2009-11-13 | 2015-01-20 | Qualcomm Incorporated | Methods and apparatus for priority initialization of a second processor |
US8368423B2 (en) * | 2009-12-23 | 2013-02-05 | L-3 Communications Integrated Systems, L.P. | Heterogeneous computer architecture based on partial reconfiguration |
US8397054B2 (en) * | 2009-12-23 | 2013-03-12 | L-3 Communications Integrated Systems L.P. | Multi-phased computational reconfiguration |
JP6045505B2 (en) | 2010-12-09 | 2016-12-14 | アイピー レザボア, エルエルシー.IP Reservoir, LLC. | Method and apparatus for managing orders in a financial market |
KR101738641B1 (en) | 2010-12-17 | 2017-05-23 | 삼성전자주식회사 | Apparatus and method for compilation of program on multi core system |
US20130157639A1 (en) | 2011-12-16 | 2013-06-20 | SRC Computers, LLC | Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption |
US10650452B2 (en) | 2012-03-27 | 2020-05-12 | Ip Reservoir, Llc | Offload processing of data packets |
US10121196B2 (en) | 2012-03-27 | 2018-11-06 | Ip Reservoir, Llc | Offload processing of data packets containing financial market data |
US9990393B2 (en) | 2012-03-27 | 2018-06-05 | Ip Reservoir, Llc | Intelligent feed switch |
US11436672B2 (en) | 2012-03-27 | 2022-09-06 | Exegy Incorporated | Intelligent switch for processing financial market data |
KR20140023609A (en) * | 2012-08-16 | 2014-02-27 | 삼성전자주식회사 | Nonvolatile memory apparatus and operating method thereof |
CA2887022C (en) | 2012-10-23 | 2021-05-04 | Ip Reservoir, Llc | Method and apparatus for accelerated format translation of data in a delimited data format |
US9633093B2 (en) | 2012-10-23 | 2017-04-25 | Ip Reservoir, Llc | Method and apparatus for accelerated format translation of data in a delimited data format |
US10133802B2 (en) | 2012-10-23 | 2018-11-20 | Ip Reservoir, Llc | Method and apparatus for accelerated record layout detection |
US9177646B2 (en) | 2013-05-06 | 2015-11-03 | International Business Machines Corporation | Implementing computational memory from content-addressable memory |
GB2541577A (en) | 2014-04-23 | 2017-02-22 | Ip Reservoir Llc | Method and apparatus for accelerated data translation |
US9530483B2 (en) | 2014-05-27 | 2016-12-27 | Src Labs, Llc | System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem |
US9153311B1 (en) | 2014-05-27 | 2015-10-06 | SRC Computers, LLC | System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers |
US9993452B2 (en) | 2014-12-05 | 2018-06-12 | Vireo Systems, Inc. | Compositions and methods for treatment of inflammation |
US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
US10942943B2 (en) | 2015-10-29 | 2021-03-09 | Ip Reservoir, Llc | Dynamic field data translation to support high performance stream data processing |
EP3560135A4 (en) | 2016-12-22 | 2020-08-05 | IP Reservoir, LLC | Pipelines for hardware-accelerated machine learning |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5570040A (en) * | 1995-03-22 | 1996-10-29 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US5737766A (en) * | 1996-02-14 | 1998-04-07 | Hewlett Packard Company | Programmable gate array configuration memory which allows sharing with user memory |
US5892962A (en) * | 1996-11-12 | 1999-04-06 | Lucent Technologies Inc. | FPGA-based processor |
US6023755A (en) * | 1992-07-29 | 2000-02-08 | Virtual Computer Corporation | Computer with programmable arrays which are reconfigurable in response to instructions to be executed |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69124946T2 (en) * | 1990-11-30 | 1997-09-18 | Ibm | Bi-directional FIFO buffer for interface formation between two buses |
US6076152A (en) * | 1997-12-17 | 2000-06-13 | Src Computers, Inc. | Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem |
DE69919059T2 (en) * | 1998-02-04 | 2005-01-27 | Texas Instruments Inc., Dallas | Data processing system with a digital signal processor and a coprocessor and data processing method |
-
2000
- 2000-05-03 US US09/563,561 patent/US6339819B1/en not_active Expired - Lifetime
-
2001
- 2001-03-16 WO PCT/US2001/008323 patent/WO2001084344A1/en not_active Application Discontinuation
- 2001-03-16 JP JP2001580696A patent/JP2003532224A/en active Pending
- 2001-03-16 AU AU2001245761A patent/AU2001245761B2/en not_active Ceased
- 2001-03-16 CA CA002403675A patent/CA2403675A1/en not_active Abandoned
- 2001-03-16 AU AU4576101A patent/AU4576101A/en active Pending
- 2001-03-16 EP EP01918715A patent/EP1297441A4/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6023755A (en) * | 1992-07-29 | 2000-02-08 | Virtual Computer Corporation | Computer with programmable arrays which are reconfigurable in response to instructions to be executed |
US5570040A (en) * | 1995-03-22 | 1996-10-29 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US5737766A (en) * | 1996-02-14 | 1998-04-07 | Hewlett Packard Company | Programmable gate array configuration memory which allows sharing with user memory |
US5892962A (en) * | 1996-11-12 | 1999-04-06 | Lucent Technologies Inc. | FPGA-based processor |
Non-Patent Citations (1)
Title |
---|
See also references of EP1297441A4 * |
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US6339819B1 (en) | 2002-01-15 |
CA2403675A1 (en) | 2001-11-08 |
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AU2001245761B2 (en) | 2006-11-23 |
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