WO2001035165A1 - Data path design for multiple electron beam lithography system - Google Patents

Data path design for multiple electron beam lithography system Download PDF

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Publication number
WO2001035165A1
WO2001035165A1 PCT/US2000/041988 US0041988W WO0135165A1 WO 2001035165 A1 WO2001035165 A1 WO 2001035165A1 US 0041988 W US0041988 W US 0041988W WO 0135165 A1 WO0135165 A1 WO 0135165A1
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Prior art keywords
die
cell
data
stripe
row
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PCT/US2000/041988
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French (fr)
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WO2001035165A8 (en
Inventor
N. William Parker
Daniel L. Cavan
Michael C. Matter
S. Daniel Miller
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Ion Diagnostics, Inc.
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Priority to US16409399P priority Critical
Priority to US60/164,093 priority
Application filed by Ion Diagnostics, Inc. filed Critical Ion Diagnostics, Inc.
Priority to US70819300A priority
Priority to US09/708,193 priority
Priority claimed from AU41359/01A external-priority patent/AU4135901A/en
Publication of WO2001035165A1 publication Critical patent/WO2001035165A1/en
Publication of WO2001035165A8 publication Critical patent/WO2001035165A8/en

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174Particle-beam lithography, e.g. electron beam lithography
    • H01J37/3177Multi-beam, e.g. fly's eye, comb probe

Abstract

A data path design for a multiple electron beam lithography system is disclosed herein. This data path design addresses the requirement for supplying a large number of parallel pattern data streams, one to each of the multiple writing beams in the lithography system. The data path can be described as a collection of embedded processors custom designed ASICs, SDRAMs, glue logic, and software. A block diagram of this implementation includes an Ethernet link (910), which is used by a controller (906) to bring in pattern data from an outside source and the Pattern Library Storage (PLS) (902), which communicates to the controller (906) through the high speed data bus (904).

Description

DATA PATH DESIGN FOR MULTIPLE ELECTRON BEAM LITHOGRAPHY SYSTEM

Cross-Reference to Related Applications

This application claims the benefit of U.S. Provisional Application No. 60/164,093 filed November 7, 1999 Background of the Invention Field of the Invention

This invention relates to the field of lithography, and in particular to data path design for multiple beam lithography. The data path is the hardware required to process and deliver pattern data in a lithography system. Description of the Related Art

Maskless lithography systems, including electron, ion and laser beam systems, all require hardware to process and deliver the pattern data. Such data path designs are well known for systems with single beams. Systems with multiple beams require a different type of data path - one that functions to efficiently break-up the pattern data and simultaneously deliver it to each beam. In the case of patterning mtegrated circuits on semiconductor wafers with multiple beams, the spacing of the beams and the relationship of this spacmg to the die dimensions becomes very important. In US Pat. No. 4,390,789, a multiple column electron beam lithography system, with one electron beam per column, is described. In this prior art, the X and Y column spacmgs are mechanically adjustable to match the X and Y die dimensions, respectively. However, mechanical adjustment of columns is not practical for a high throughput manufacturing environment in which wafers with different die sizes may be being processed simultaneously withm the same fabrication facility. Thus, it is desirable to have a multiple beam lithography system m which the columns can be fixed at minimum X and Y spacmgs, thereby maximizing the number of columns usable for patterning dies of any size. The data path in this case must be more complex in order to accommodate possible mismatches between the X and Y column spacmgs and the X and Y die dimensions, respectively.

Summary Of The Invention

This invention includes a data process and distribution system for multiple beam lithography. Full advantage is taken in the data path design of the required pattern data structure, m particular, for semiconductor wafers, the high degree of parallel data use arising from the onentation of dies on the wafer parallel both to the orientation of the array of writing cells and to the wafer stage scan direction. Within the lithography system, decompressed pattern data is distributed and stored locally, either at each writing cell m a first embodiment or for each group of cells oriented along the scan-axis of the wafer stage in a second embodiment. The first embodiment is compπsed of a pattern storage device, a controller, a multiplicity of decompression engines, a multiplicity of beamlet pattern memoπes and a multiplicity of blankers connected m said order. The second embodiment is compπsed of a pattern hbrary storage device, a controller, a raster image processor, a multiplicity of row buffers and a cell array connected m said order. The raster image processor is compπsed of a geometry processor connected to a raster ASICS, m turn connected to a SDRAM. The SDRAM has sufficient memory to store a complete die pattern. Each row buffer has sufficient memory to store one die stripe of data. In a further embodiment, the raster image processor and the row buffer have ECC and CRC hardware, so as to reduce errors.

Brief Description of the Figures

FIG 1 shows a schematic of the cell electron optical components and a block diagram of the cell control electronics. FIG. 2a shows a schematic of a die and depicts how it is wπtten using stπpes and substπpes.

FIG. 2b shows a magnified view of FIG. 2a focusing on two adjacent stripes and their decomposition into substπpes.

FIG. 2c shows a schematic of a single substπpe that is 3.2 μm wide and 20.0704 mm long. FIG. 2d shows a schematic of the cells, each with 32 beams, writing on a wafer. FIG. 2e shows a magnified view of FIG. 2d, indicating the electronic scanning of the 32 beams of a single cell over the writing area, and the scanning of the stage underneath the cell. FIG. 2f shows a schematic of a single stripe and its decomposition into substπpes. FIG. 2g shows a magnified view of FIG. 2f, indicating a single substπpe and its decomposition into writing pixels. FIG. 2h shows a magnified view of FIG. 2g, indicating the pixel exposure sequence across a single substπpe.

FIG. 3 shows a block diagram representing an overview of the data path in a first embodiment of the present invention.

FIG. 4 shows a block diagram of a beamlet pattern memory (BPM) 324 showing the bus and address structure for the first embodiment of this mvention.

FIG. 5a shows a schematic of the arrangement of 121 dies on a 300 mm diameter wafer, with the dotted lines indicating the cell placement. The die area is larger than the cell footpπnt.

FIG. 5b shows a schematic cross-sectional side-view of FIG. 5a along a horizontal axis through the center of the wafer, indicating cell and die size differences. FIG. 6 shows a schematic of how the pattern data for the dies in FIG. 5a (with the die area larger than the cell footprint) is distπbuted to the cells m a cell array.

FIG. 7a shows a schematic of the arrangement of 157 dies on a 300 mm diameter wafer, with the dotted lines indicating the cell placement. The die area is smaller than the cell footpπnt.

FIG. 7b shows a schematic cross-sectional side-view of FIG. 7a along a hoπzontal axis through the center of the wafer, indicating cell and die size differences. FIG. 8 shows a schematic of how the pattern data for the dies in FIG. 7a (with the die area smaller than the cell footprint) are distributed to the cells in a cell array.

FIG. 9 shows a block diagram of a top-level view of the data path in a second embodiment of the present invention. FIG. 10 shows a block diagram of the raster image processor.

FIG. 11 shows a block diagram of a single row buffer board.

FIG. 12 shows a block diagram of a row buffer indicating the row buffer ASIC design.

FIG. 13 shows a block diagram of a top-level view of the data path in a second embodiment of the present invention, indicating error detection and correction strategies. Detailed Description

The data path system for a multiple beam electron lithography system in the present invention enables the patterning of semiconductor wafers directly using a plurality of electron beams, each simultaneously supplied with patterning information from a large pattern library storage device. Before considering the details of the data path system, it is first useful to outline the design considerations impelling the need for a multiple beam electron lithography system.

Resolution and throughput are the two most important parameters in an electron beam lithography system. Two given parameters are the sensitivity of the electron beam resist R (μC/cm2), and the wafer area A (cm2). If the total beam current into the wafer is I (μA), the time to expose a wafer, T, is T = R A / 1

Thus, for high throughput, requiring minimum T, we want to maximize I, assuming A and R are given. If the beam current of an electron optical system exceeds a few μA, beam focusing is affected by electron-electron repulsion, or "space-charge effects". This is a fundamental physical limit, although the exact upper limit on the beam current, I, depends on the details of the system design. The multibeam electron lithography system considered herein overcomes this limit by distributing the writing current, I, into multiple electron optical columns, each with one or more writing beams. The current in each column is I / N where N is the number of columns.

Throughput is determined by the total time to expose the wafer plus wafer exchange, align ment, and stage overhead. It is possible to keep this overhead to 25% or less of the total. Thus, 90 s of exposure and 30 s of overhead results m a total time per wafer of 120 s, giving a system throughput of 30 wafers per hour.

Electron Beam Direct Write (EBDW) lithography requires the beams to be unblanked as they write the patterns. The present invention uses a raster scan, in which all the beams simultaneously scan regular raster patterns and the beams are unblanked where the resist is to be exposed and remain blanked where the resist is not to be exposed. Patterns being written are made up of exposed and unexposed pixels, typically square, and at least several times smaller than the minimum feature size.

If the pixel size is p, there will be M pixels per wafer:

M = A / p2

This can be a very large number. For example, if the pixel size is 25 nm and the wafer is 300 mm in diameter with no edge exclusion (unwπtten area at the wafer edge), then:

M = [π (150 mm)2] / (25 nm)2 = 1.13 x 1014 pixels

Precision electron optics have a limited field size (writing area), which is roughly 100 μm wide for the column 100 which is part of the present invention. The addition of mechanical stage scanning orthogonal to the electronic scan allows a long stripe of pattern data to be wntten. If the mechanical stage repeatedly steps over by the width of the stripe, the whole wafer can be written m a series of long stripes that are abutted.

The time to expose each pixel t is t = T / M and the associated blanking rate f > 1 / 1. To achieve high throughput with a single writing beam, this rate would need to be unpractically high. For example, in the case above, t = (90 s) / (1.13 x 10M) = 7.96 x 10"13 corresponding to a minimum blanking rate f = 1 / (7.96 x 10"13) = 1.26 THz. With N columns, the number of pixels to be exposed by each column, Mc , is reduced by a factor 1 / N:

MC = M / N and the time for each pixel is lengthened by N. A further substantial reduction in blanking rate can be achieved if each column has P separate beamlets (where P»l), each blanked independently. The wafer exposure time is then increased by a factor (N P) from the case for a single writing beam: t = ( T N P ) / M

Now, with the following assumed parameter values: R = 10 μC/cm2

A = 707 cm2 for a 300 mm diameter wafer

T = 90 s (combines with 30 s overhead to give 30 wafers per hour)

I = 78 μA [well above the physical (space-charge) limit for a single beam]

N = 201 corresponding to a 15 x 15 (= 225) array of 20 mm square columns with 24 columns omitted (6 columns omitted from each of the 4 corners of the 15 x 15 array) p = 25 nm P = 32 beams per column We have

M = 1.13 x lO14 pixels

Mc = (1.13 x 1014) / 201 = 5.6 x 10π pixels written by each column per wafer t = (T N P) / M = 5.1 ns corresponding to a blanking rate f = 200 MHz Thus, by using multiple beamlets and multiple columns the multibeam electron lithography system achieves high throughput without violating physical laws (space-charge limits) and without excessively high blanking rates.

Now that the necessity for employing a multiplicity of electron beams in a high-throughput electron beam lithography system has been established, we next consider details of the initial pattern data format as it would be supplied to the hthography system. The multi-beam electron hthography system discussed in this patent is designed to replicate the patterns described by an industry standard description of a single layer of a semiconductor device onto an industry standard wafer. In this way, circuits can be manufactured that provide the functionality the original chip designer intended Chip description information is commonly stored m a GDS-II format file GDS-II is an industry standard data format, used to define integrated circuit (IC) mask layers, within a semiconductor chip design.

At the lowest level, the GDS-II data consists of polygonal shapes. These polygons are hierarchically instanced to create complex patterns. Modern IC design methodology constructs extremely dense devices, using a library of characterized, and replicated macrocells. The hierarchy in the GDS-II data allows these dense, but repetitive designs, to be described by a small and manageable data file. A GDS-II data file, for all layers of a chip design, will be on the order of 10 MBytes to 2 GBytes. The data necessary for a single die will be significantly smaller, but the need to include many of the commonly used macrocells m the definitions of each single die reduces the data compression intrinsic in a typical GDS-II data file significantly.

A "cell" is defined as a single structure incorporating the source structure to generate electrons, the electron-optics and associated acceleration and deflection structures, and the necessary support electronics. The multiple column electron beam lithography system incorporates more than 200

"cells" into an mtegrated column structure, consisting of a two dimensional array of rows and columns.

To pattern 300 mm wafers, the multibeam electron hthography (MEL) system uses a 15 x 15 array of electron beam cells, on a roughly 20 mm x 20 mm grid, with 32 beamlets 150 per cell.

Because the wafers are circular, six cells may be omitted from each of the four corners of the 15 x 15

(= 225) cell array, giving a total of 201 cells in the multi-beam column structure. A single cell creates an electronic scan line, which is 102 4 μm long by a single pixel (25 nm) wide. The stage mechanically scans in a direction orthogonal to the scan line, with each cell wπtmg a 102.4μm x 20 mm stπp of pixels on the wafer, called a cell stripe. Withm each cell of the multibeam electron hthography (MEL) system, 32 independently blanked beams (see figure 1) each write a cell subs tripe on the wafer that is 102.4 μm long by 3.2 μm wide.

A die stripe is a stripe of pixels that is 102.4 μm wide and as long as the die. This can be broken down further, where a die substrψe is a stripe of pixels that is 3.2 μm wide and as long as the die. If the die is wider than the cell spacing, then a cell stripe will consist of a subset of the die stripe. On the other hand, if the die is narrower than the cell spacing, then the cell stripe will consist of whole and fractional sections of the die stripe.

The size of the pattern that the die information represents and the size of the pattern that a cell 520 can write have a unique relationship that is determined by the way in which the lithography system writes patterns. Without stage motion, a cell 520 can write a pattern which is 102.4 um wide (along the X-axis), but only one pixel size (25 nm) long (along the Y-axis, the direction of stage scanning), called a "scan line". By moving the stage in the Y-axis direction while scan lines are being written, the cell 520, in combination with the stage, can write a cell stripe that is 102 4_ m in the X- Axis by 20.07 mm m the Y-axis. Once a cell stripe has been written, the stage then moves one stripe width (102.4 Zm) in the X-axis direction, and the cell 520 and stage again cooperate to write another cell stripe that is adjacent to - and parallel to - the previous one. In this way, each cell 520, m conjunction with the motion of the stage, writes successive stripes of a pattern, each of which is 102.4 _ m wide by 20.07 mm long, until a complete cell writing area of 20.07 mm by 20.07 mm has been patterned. Other cells 520 m the cell array 540 write adjoining 20.07 mm x 20.07 mm areas, where the 15 x 15 cell array 540 covers the entire patterned area on the wafer. Since all cells in the array of cells write simultaneously, the entire wafer has been patterned when a single 20.07 mm x 20.07 mm cell pattern has been written.

For the case in which the size of the cell writing area is exactly the same as the size of the die pattern to be written, each beamlet in each cell would write the same pattern data at the same time. At this point, it is useful to define a column of cells as a line of cells in the Y-axis - parallel to the stage motion during cell stripe writing, and a row of cells as a line of cells in the X-axis - perpendicular to the stage motion during cell stripe writing. This means that, upon completion of any cell stripe, the patterns that the cells have written will have merged into a stripe that extends from one edge of the wafer being patterned to the opposite edge, and that incorporates multiple copies of that single stripe of the die pattern to be written. Since die patterns are placed on the wafer m regular arrays, it can be considered that the system is patterning, in much the same way, rows and columns of copies of the die pattern in question on the wafer being patterned.

In the case where the die pattern is either larger or smaller than the cell writing area, the system cannot rely on any given cell writing the same data as any other cell at any given point in time. Further consideration, however, reveals straightforward relationships between the data each cell is causing to be wπtten. Cell columns combine to write a single stripe of pattern image that is a repetition of the same die stripe many times over. This is true whether the die stripe is longer than, shorter than or the same length as the cell stripe. When considered in relation to the die stπpe data being written, each cell 520 in a cell column is writing a portion of the same die stripe data. In some cases, two neighboring cells 520 will write parts of the same die. In other cases, a single cell will write parts or all of more than one die. An example (m which the numbers have been rounded for simplicity) would be where the cell stripe length is 20 mm and the die stripe length is 15 mm. All cell stripes in this example are written simultaneously. In this case, the first cell 520 m the cell column would write the full die stripe for the first copy of the die pattern along this column and the first 5 mm of the same die stripe of the second die copy along the column. The second cell 520 in the cell column would write the last 10 mm of the same die stπpe in the second die copy of that column on the wafer and the first 10mm of the same die stripe in the third die pattern copy The third cell in the column would write the last 5 mm of the same die stπpe in the third die copy and would write all of the same die stripe for the fourth copy of the die pattern for that die column on the wafer. The cells 520 m a particular cell row each write the same sectιon(s) of a die stripe on the wafer, but these will only be the same sectιon(s) of the same die stπpe if the width (the length along the X- axis) of the cell writing area is the same as the width of the die pattern (again, the length along the X- axis). An example would be where the cell writing area width is 20 mm and the die pattern width is 15 mm. Additionally, it is assumed (again, rounded for simplicity) lOO μm die/cell stripe width. In this case, a die pattern would require 150 die stripes ("0" through "149"), while the cell writing area covers 200 cell stripes ("0" through "199"). All cell stripes in this example are written simultaneously. In this example, cell "0" of the cell row would write die stripe "0" of the die pattern in die row "0". Cell "1" of the cell row would write die stripe "50" of the die pattern m die row "1". Cell "2" would write die stπpe "100" of the die pattern in die row "2". Cell "3" would write die stripe "0" of the die pattern in die row "4".

The following section describes details of how the data path system m the present invention uses the die pattern information stored in the pattern library storage device 302 to control a multiplicity of writing cells 520 in a cell array 540 to properly pattern wafers with high throughput and high spatial resolution. Two patterning examples are discussed m detail: (1) where the dimensions 556 of the dies 502 being written are larger than the dimensions 546 of the cell 520 wπting area, and (2) where the dimensions 756 of the dies 704 are smaller than the dimemsions 546 of the cell 520 writing area.

FIG. 1 shows a schematic cross-sectional side view of a single electron optical column 100 as employed in the present invention. In FIG. 1, the source assembly 102, source control 104, alignment deflector 106, alignment deflector control 108, spray aperture plate 109, beam current monitoring aperture plate 110, beam blankers 112, beam blanker drivers 114, beam rotator 116, beam rotator control 118, shield plate 120, focus and shield electrodes control 122, upper mam deflector 124, lower mam deflector 126, mam deflector control 128, subfield deflector 130, subfield deflector control 132, focus electrode 134, blanking aperture 136, hole in blanking aperture 137, blanking aperture current sense control 138, back-scattered electron detector 140, back-scattered electron detector control 142, wafer 144, electron beams 150, field emitter tips 162, tip substrate 164, gate electrodes 166, and lens electrodes 168 are shown. The electron source assembly 102 is controlled by the source control 104. Electrons are emitted by each of the field emitter tips 162 due to the electric field induced at the tips 162 by a voltage applied between the tip substrate 164 and the individual gate electrodes 166. The source control monitors the currents collected on the beam current monitoring aperture plate 110 and regulates the voltages on the gate electrodes 166 to maintain the beam currents constant. Lens electrodes 168 focus the individual beams down the column to the spray aperture plate 109.

The alignment deflector control 108 provides DC deflection voltages to the alignment deflector

106. These deflection voltages steer the individual beamlets into the hole 137 in the blanking aperture

136. The beamlets 150 are centered on the blanking aperture by sweeping the alignment deflector voltages to scan the beamlets 150 m a raster over the hole 137 m the blanking aperture 136 while measuring the blanking aperture current with the blanking aperture current sense control 138.

The beam blanker dπvers 114 provide the beam blanking signals to the beam blankers 112. To blank the beam (i.e., turn off the beam current at the wafer), a small voltage is applied by the blanker driver 114 to the two plates of the blanker 112, thus deflecting the beam out of the hole 137 in the blanking aperture 136. To unblank the beam (i.e., allow the beam to reach the wafer to write a pattern in the resist), the blanker driver 114 sets the blanker 112 voltages to 0 V, and the beam is thus allowed to pass through the hole 137 in the blanking aperture 136.

The rotator 116 is an electrostatic octupole requiring eight voltage drive signals which are supplied by the beam rotator control 118. Drive voltages to the rotator 116 are set only once during a calibration procedure performed during the initial system setup. The purpose of the rotator 116 is to adjust the azimuthal rotation (rotation around the column axis) of the multiplicity of beams 150 in each column 100 to align with the underlying patterns on the wafer - a process called "overlay".

The voltage on the shield electrode 120 is controlled by the focus and shield electrode control 122. The shield electrode 120 provides an offset bias voltage for individual focusing of each column 100. The mainfield deflector control 128 supplies low frequency (<50 kHz) deflection voltages to the mamfield upper 124 and lower 126 deflectors to compensate for stage positioning errors and the normal movement of the wafer 144 under the beams 150 caused by stage movement during scan-line wπt g.

The subfield deflector control 132 supplies high frequency (>10 MHz) signals to the subfield deflector 130. The subfield deflector 130 provides the fast wπtmg ramp which generates the scanning of beams 150 on the wafer 144. The voltage on the focus electrode 134 controls the fine focusing of each column 100 and is provided by the focus and shield electrode control 122. The blanking aperture current sense control 138 monitors the current at the blanking aperture 136 to assist with beam alignment during set-up of the column 100. The back-scattered electron (BSE) detectors 140 are controlled by the BSE detector control 142. The BSE detectors 140 comprise four silicon PIN diodes. The BSE detector control contains four analog pre-amplifiers, and four fast A/D converters. The key function of the BSE detectors 140 is to obtain accurate wafer alignment on each written wafer 144.

FIG. 2 schematically shows a die 202 with X-Y dimensions corresponding to the largest area which can be written by a single optical column 100, and the decomposition of the die pattern data into die stripes and die substπpes. In FIG. 2a, the die 202 and die stripes 204 are shown. In FIG. 2b, die stripe "1" 206, die stπpe "2" 208, and die substπpes 210 are shown. In FIG. 2c, die substπpe detail 212 is shown.

In FIG. 2a, the die 202 has dimensions of 20.0704 mm x 20.0704 mm square, where:

20.0704 mm = 196 x 102.4 μm corresponding to exactly 196 die stripes 204 of width 102.4 μm. The resulting number of 25 nm x 25 nm pixels in each die stripe 204 is then:

# pixels/(die stripe) = 20.0704 mm x 102.4 μm / (25 nm)2 = 3,288,334,336

In FIG. 2b, close-ups of the ends of die stripe "1" 206 and die stripe "2" 208 are shown, as well as the decomposition of die stripe "1" 206 into 32 die sub-stripes 210. All die stripes 204 are decomposed in the same way as is shown here for die stripe "1" 206.

In FIG. 2c, a close-up detail view of a single die sub-stripe 210 is shown. The number of 25 nm x 25 nm pixels in each 3.2 μm wide die sub-stripe is then:

#pixels/(die sub-stripe) = 20.0704 mm x 3.2 μm / (25 nm)2 = 102,760,448

FIGs 2d-2h show several diagrams depicting the writing strategy employed by the lithography writing head. The schematic diagrams in FIGs 2d and 2e show the wafer 144, the writing area 1402, the 32 beams 1406 from each source, the stripe 1414 written by the 32 beams 1406, and the serpentine motion 1418 of the stage. FIGs 2f-2h show increasing magnification of the stripe 1414 written by 32 beams 1406 and the substπpe 1410 written by a single beam. The stripe 1414 is 102.4 μm in width x 20.0704 mm long, and is composed of 32 substπpes 1410, which are 3.2 μm in width x 20.0704 mm long. The width of each substπpe 1410 is composed of 64 writing pixels, each of which are 50 nm x 50 nm.

For a 300 mm wafer 144, a total of 201 cells simultaneously write on the surface of the wafer

144. Each cell covers an approximately 20 mm x 20 mm square writing area 1402 on the surface of the wafer 144. Thus, the entire surface area of the wafer 144 is covered by the 201 cells. Within each cell there are 32 beams 1406, produced by 32 field emission electron sources 162. The 32 beams 1406 are 3.2 μm apart from each other on the wafer 144, and are simultaneously scanned along the array direction using the subfield deflectors 130. Each pixel is 50 nm x 50 nm, and the subfield deflector

130 scans 64 pixels to create a 3.2 μm-wide substπpe 1410, as shown in FIG 2h. This scan completely fills in the area between adjacent beams. Due to the microfabπcation accuracy of the electron optical sources, the edge abutment between adjacent substπpes 1410 can be made with very high precision.

This substπpe 1410 corresponds to the same substπpe 204 depicted m FIGs 2a and 2c. The 32 beams

1406 are stitched together to form a 102.4 μm-wide stripe 1414 on the wafer. Examples of these 102.4 μm-wide stripes 206 & 208 are shown m FIG 2b. In order to create the length of the stripe 1414 and substπpes 1410, the stage moves slowly (relative to the beam scanning speed) in the direction peφendicular to the scan direction of the subfield deflectors 130 (see FIG. 1). As the stage moves, the 32 beams 1406 are simultaneously scanned back and forth to create a stripe 1414 that is written across the 20 mm x 20 mm writing area. As the stage scans across the entire writing area 1402 of the cell, the resulting stπpe 1414 is 20 mm long and 102.4 μm wide After completing one 20 mm pass across the writing area, the stage moves the wafer 102.4 μm in the direction along the beam array, and travels back across the writing area 1402 m the direction opposite to its first pass, as depicted in FIG. 2e. This process is repeated until the entire 20 mm x 20 mm writing area is written with 196 stripes 1414, as shown in FIG. 2a. The wafer stage motion is called a serpentine motion 1418 (back-and-forth, writing both ways), covering the 20 mm square writing area 1402 with about 196 stripes 1414 over a period of roughly 90 seconds. FIG. 3 shows a first embodiment of the present invention. In FIG. 3, the pattern library storage

(PLS) 302, high-speed data link "1" 304, controller 306, high-speed data link "2" 308, sub-stripe storage array (SSSA) 310, disk drives 312, data links 314, disk drive controllers 316, high-speed data links "3" 318, beamlet controllers 319, decompression engines 320, row-data links 322, beamlet pattern memories (BPMs) 324 and outputs to blankers 326 are shown. An off-line pattern preparation system pre-processes the CAD data (typically in GDS-II format) into compressed die sub-stπpe blocks. Each die sub-stripe block defines the patterning data for a rectangular section of the die measuring 3.2 μm by the die height, where "height" is the die dimension along the direction of stage motion.

Device layer data are stored m the multibeam electron lithography (MEL) system in the compressed die sub-stripe format on a large mass storage device called Pattern Library Storage (PLS) 302 The storage capacity of the PLS 302 is configurable based on the number of device layers to be randomly accessed. The typical compressed data size for a 3 cm x 3 cm device will be about 20 GB, assuming at least a 10: 1 compression of the bit-mapped data. To randomly access several dozen layers, a storage capacity of roughly 500 GBytes is required for the PLS 302. Pattern data is supplied to the controller 306 by the high-speed data link "1" 304. The controller

306 then broadcasts the pattern data (organized into die sub-stπpes) through high-speed data link "2" 308 to the SSSA 310. Assuming Ultra-SCSI data transfer rates (about 20 MB/s), this process could take up to seventeen minutes for the 20 GB of compressed layer pattern data. 'Fiber-channel' 3 " " disks with 100 MB/s data transfer rates would reduce the data transfer time to about 4 minutes. This is for a worst case (largest allowable) 3 cm x 3 cm die as shown in FIG. 2. Since, in normal production, all wafers in the lot are written with the same pattern information, this pattern load time occurs, at most, once per lot. A throughput reduction occurs only when the device or the product layer changes between lots.

In this embodiment of the present invention, the SSSA 310 contains an array of disk drives 312, each storing data for four neighboring die sub-stripes. Data from each disk drive 312 is supplied through data link 314 to the disk controller 316.

In the embodiment of the present invention shown in FIG. 3, each disk controller 316 is shown supplying pattern data to four decompression engines 320 through the high-speed data links "3" 318. The exact number of decompression engines 320 required would be determined during design optimization and is not part of the present invention. Each decompression engine 320 supplies decompressed pattern data to 15 beamlet pattern memories (BPMs) 324 using the row data links 322. The reason that a single decompression engine 320 can supply pattern data to 15 BPMs 324 is that all of these cells share the same stage X-axis coordinate, as illustrated in FIGS. 5a and 7a, where the stage motion during writing is parallel to the Y-axis in this embodiment. It is of note that the axis designation used here is arbitrary. Each BPM 324 supplies die sub-stripe data to a single beam blanker driver 114 withm a single cell the cell array 540.

As shown m FIG. 2, there are 293 die stripes, each 102.4 μm wide, in a 20.0704 mm x 20.0704 mm die, where each die stripe 204 consists of 32 die sub-stripes 210, for a total of 196 x 32 = 6272 die sub-stripes. Since the cell aπay is 15 x 15 and all cells 520 a given cell row write different components of the same die stripe 204 data, only 15 die stripes 204 need to be accessed on any single stripe scan of the stage. Each electron column 100 withm each cell 520 has 32 beamlets (writing 32 neighboring die sub-stripes), so only 480 (15 x 32) die sub-stripes (out of the total 6272 maximum possible) need to be accessed on any single stripe scan of the stage. In the embodiment shown, each disk drive 312 and disk controller 316 supplies die sub-stripe pattern data to four decompression engines 320, so there are 120 disks 312 in the SSSA 310, where

120 disks = (480 die sub-stripes) / (4 die sub-stπpes/disk).

The stage transit time from start of one cell stripe scan to the start of the next cell stripe scan, assuming a 20 mm cell stripe length, is roughly 500 ms. This is the time allowed to unload the die sub-stπpe data from each disk in the SSSA 310. Each compressed die sub-stπpe data block is about 2 MB in size, again assuming that we can achieve a compression ratio of about 10:1. This 2 MB of data is transferred from the disk 312 to the SSSA controller 316 every cell stripe scan of the stage - to make this transfer in 500 ms implies a data transfer rate requirement of about 4 MB/s through data link 314.

During the current cell stripe scan, the complete die sub-stripe data for 4 die sub-stripes of the next die stπpe are read from the SSSA disk controller 316 memory and delivered to four separate decompression engines 320. During the writing of this same stripe, data for the die stripe following the next die stripe is being unloaded from the disk 312 into the SSSA controller 316 memory.

Because of the high data rate required at each beamlet blanker 112, each die sub-stripe requires a separate decompression engine 320, requiring 480 individual decompression engines 320. The decompression engine 320 broadcasts the same complete decompressed die sub-stripe data to 15 separate BPMs 324, one for each of the 15 scan-aligned (Y-axis, or stage scan direction) beamlets. All scan-aligned beamlets use data from the same compressed pattern data block, but each beamlet will typically read the decompressed pixel data in a different sequence, as shown m TABLES 2 and 4 and FIGS 6 and 8.

FIG. 4 is a functional block diagram of a beamlet pattern memory (BPM) 324 showing the bus and address structure. In FIG. 4, the control bus 404, BPM interface and control logic 406, BPM read control bus 408, memory bank 'A' 410, memory bank 'B' 412, BPM write data and write address bus 322, BPM read data bus 416, output shift register 418, outputs to blankers 326, BPM address structure key 430, and components of the BPM address: row 432, column 434, and beamlet 436 are shown.

There is sufficient memory in each BPM to contain both the current and next stripe pixel data. This implies a BPM memory size of about 300 Mbits, 150 Mbits in each of memory bank 'A' 410 and memory bank 'B' 412, which are dual ported. The two memory banks 'A' 410 and 'B' 412 alternate so that one is being loaded from the de-compression engine 320 while the other is being read out onto the read data bus 416. Individual BPM controllers 406 receive start, stop, and repeat instructions from the control bus 404, allowing each to read its particular sub-stripe data sequence The BPM address structure 430 enables the addressing of any beamlet within the entire cell array

540. The complete address is designed to use 16 bits, 4 bits for the row address 432, 4 bits for the column address 434 and 8 bits for the beamlet address 436. Two examples are given in FIG. 4, showing the BPM addresses for cell (4,2) beamlet #00 [hexadecimal address 4200h], and cell (3,11) beamlet #31 [hexadecimal address 3BlFh]. FIGS. 5 and 6 illustrate the patterning of a 300 mm wafer 504 for the case of dies 502 larger than the X-Y spacing 546 of the cells 520. In this example, the size of dies 502 is 21.504 mm x 21.504 mm, corresponding to an integral number (=210) of die stripes 204 (where 210 x 102.4 μm = 21.504 mm). The spacing 546 of cells 520 is also an integral number (=196) of stripes 204 wide (where 196 x 102.4 μm = 20.0704 mm). In FIG. 5a, dies 502, 300 mm wafer 504, edge exclusion area 505, wafer edge 506, X-axis cell numbers 510, Y-axis cell numbers 512, cells 520, X-axis cell boundaries 530, Y-axis cell boundaπes 532, and cell spacing 546 are shown. FIG. 5a shows the arrangement of a total of 121 dies 502 on a

300 mm diameter wafer 504, assuming a 6 mm edge exclusion, i.e., no dies can extend into the area

505 of wafer 504 which is withm 6 mm distance measured radially inwards from the edge 506 of the wafer 504. The X-axis 530 and Y-axis boundaπes 532 of the cells 520 are shown as dashed lines, while the X-axis and Y-axis edges of the dies 502 are shown as solid lines. Because the sizes of the dies 502 differ from the sizes of the cells 520, there is a "beat" pattern between them as can be seen from FIG. 5a. For the example shown m FIG. 5, this means that each cell 520 writes an area smaller than the area of a die 502, thus every die 502 is necessarily written by more than one cell 520.

FIG. 5b shows a schematic cross-sectional side-view of FIG. 5a along a horizontal axis through the center of the wafer 504. In FIG. 5b, the cells 520, cell boundaries 532, 20.0704 mm cell spacing

546, cell array 540, dies 502, die edges 552, die dimension 556, and wafer 504 are shown. The "beat" pattern between the cells 520 and the dies 502, arising from the difference between the 20.0704 mm cell spacing 546 and the 21.504 mm die dimension 556.

Difference = 21.504 mm - 20.0704 mm = 1.4336 mm = 14 stripes width can be seen from FIG. 5b. As the difference calculation indicates, the dimension 556 of dies 502 is exactly 14 stripes larger than the spacing 546 of the cells 520.

In FIG. 5b, all the cells 520 in the leftmost vertical column of FIG. 5a are called cell column

"A". The next cell column to the right is "B", and so on, across the cell array 540 to the rightmost cell column "O". A similar scheme is used for die 502 labelling. All the dies 502 in a vertical column at the left of the wafer 504 are called die column "a". The next die column to the right is "b", and so on, across the wafer 504 to the rightmost die column "m".

The cell column labels "A" through "O", and die column labels "a" through "m" are used in

TABLE 1 to illustrate a specific example of how the data path of the present invention distributes die stripe data to the cells 520 in the multibeam electron lithography system.

TABLE 1

Figure imgf000016_0001

TABLE 2

Figure imgf000017_0001

FIG. 5b can also represent a cross-sectional side view of FIG. 5a along a vertical axis through the center of the wafer 504 if the labels are changed as follows:

A → A', B -» B' ,... , N → N', 0 -> 0' where now all the cells 520 in the bottom horizontal row of FIG. 5a are called cell row "A' ". The next cell row up is "B' ", and so on up the cell array 540 to the topmost cell row "O". Similarly, the die 502 labels are also changed as follows: a -» a', b → b', ... , 1 -» r, m -* m' where now all the dies 502 in the bottom horizontal row of wafer 504 are die row "a' ". The next die row up is "b' ", and so on up the wafer 504 to the topmost die row "m' ". The cell row labels "A' " through "O' ", and die row labels "a' " through "m' " are used in

TABLE 2 to illustrate the die stπpe data pointers used for each cell row. Again, a "beat" pattern is evident. Although m this example, the vertical and horizontal die dimensions are shown the same (21.504 mm), this is not a requirement of the present invention.

TABLE 1 describes the allocation of die stripe data to all the cells 520 in the cell array 540 using the notation shown in FIG. 5b. For simplicity, the left edge 532 of cell column "A" is aligned with the left edge 552 of die column "a" (at the far left of FIG. 5a).

Referring to FIG. 5a, all cells 520 in cell column "A" will require the same die stripe data. Similarly, all cells 520 in cell column "B" will also require the same die stripe data, typically different data than for cell column "A". Similar considerations hold for cell columns "C" through "O". This is the basis for the data broadcasting concept in the present invention, as described m FIG. 3, wherein all BPMs 324 along the Y-axis (vertical) rows receive the same stripe data from the row data links 322.

Similarly, m TABLE 1, the die column "a" refers to all of the three dies 502 m the vertical row at the left of the wafer 504 in FIG. 5a. Die column "b" refers to all of the 7 dies 502 in the next vertical row to the right, and so on, across the wafer 504 to die column "m" which refers to all of the three dies 502 in the rightmost vertical row of the wafer 504.

The two left columns m TABLE 1, read top-to-bottom, correspond to FIG. 5b, viewed left-to-πght. At the top of TABLE 1 the die stripe data ("0" through "195" m the third and fourth columns from the left) coπespond to data for die column "a" and are written by cell column "A". The next line in TABLE 1 shows the remaining die stripes "196"-"209" for die column "a" being written by cell column "B". This shows that because the size 556 of dies 502 is larger than the spacing 546 of cells 520, then necessarily part of die column "a" overlaps into the writing area of cell column "B". The third line shows that the first die stripes for die column "b" ("0" through "181") are wπtten by cell column "B", while the remaining die stripes ("182" through "209") are wπtten by cell column "C". TABLE 1 shows the complete distribution of die stπpe data for all the cell columns "A" through "O" of the cell array 540. Note that cell column "N" writes only 182 die stripes and cell column "O" is not used for writing at all.

From TABLE 1, we can now detemine the sequence of die stripe data being supplied simultaneously to each of the cells 520 in the cell array 540. The first die stripe supplied to cell column "A" is "0" of die column "a", for cell column "B" the first die stripe supplied is "196" of die column "a", for cell column "C" the first die stripe supplied is "182" of die column "b", and so on down the third column, labelled "Die Stripes, First" in TABLE 1, to cell column "N" for which the first die stripe supplied is "28" of die column "m".

For cell column "A", die stripes of die column "a" are written sequentially: "0", "1", "2",.... ,"194", "195", for a total of 196 die stripes out of a total of 210 die stripes for die column "a". At this point, the entire wafer 504 has been written by the cell array 540.

For cell column "B", die stripes of die column "a" are written sequentially: "196", "197",..., "209", corresponding to the remaining 14 stripes for die column "a" which were not written by cell column "A". At this point, cell column "B" begins to write die stripes of die column "b": "0", "1", .... , "181", for a total of 182 die stripes. At this point, cell column "A" has just completed writing die stripe "195" of die column "a" and the entire wafer 504 has been written by the cell array 540. Note that the sum of 14 die stripes for die column "a" and 182 die stripes for die column "b" equals 196, the number of die stripes written by each cell 520 in the cell array 540.

Similar considerations hold for cell columns "C", "D", .... , "M" in cell array 540. The case for cell column "N" is different because it is at the edge of the patterned area on wafer 504. The writing sequence for cell column "N" is die stripes "28", "29",.... , "209" of die column "m", for a total of 182 die stripes. At this point, there is no more patterning data for cell column "N", so it remains inactive (all beams 150 blanked) until cell columns "A" through "M" have completed 14 more die stripes, at which point the wafer 540 has been completely patterned. TABLE 1 shows that for this case, cell column "O" is not used at all because it is completely outside the patterned area of wafer 504.

TABLE 2 describes how the die stripe 204 data is used by each cell 520 along each cell row, i.e., in the perpendicular direction from the cell columns considered in TABLE 1. From FIG 5a, given the definitions of cell columns and cell rows, the following table correlates the X-axis cell numbers 510

(from 0 through 14) and the Y-axis cell numbers 512 (from 0 through 14) with the required cell column data and cell row data:

Figure imgf000019_0001

The cell column data consists of the patterning data for the dies 502 being written on the wafer 540. The cell row data tells each cell 520 the proper sequence for using the cell column data. FIG. 5a shows that all cells 520 along each cell column "A" through "O" write the same die stripe on all of the dies 502 m their respective die columns. For example from TABLE 1 (top line), all the cells

520 in cell column "A" initially are writing the same die stripe data into all the dies 502 in die column

"a". However, FIG. 5a shows that the "beat" pattern between the die size 556 and the cell spacing 546 in the vertical (column) direction requires that each of the individual cells 520 along every cell column "A" through "O" must write the pattern data in a different sequence. The purpose of the cell row data "A' " through "O' " is to define the proper writing sequence for all of the cells 520 along each horizontal row of cells 520 across the cell array 540, where typically, the proper writing sequence will be different for each cell row. TABLE 2 is similar m some ways to TABLE 1 since both tables derive from the "beat" pattern between the writing areas of each cell 520 in cell array 540 and the areas of each die 502 on wafer 504. Since in this example, we have assumed that the X and Y dimensions 556 of dies 502 are the same (which is not part of the present invention), and because the X and Y cell spacmgs 546 are also the same (which is also not part of the present invention), then the corresponding X and Y "beat" patterns are identical. The leftmost two columns in TABLE 2 coπespond to the second interpretation of FIG. 5b, described above, wherein the cell row labelling is "A' " through "O' " and the die row labelling is "a' " through "m' ". The top row of TABLE 2 shows that cell row "A' " writes a section of the die stripe from 0.00 mm to 20.07 mm, corresponding to the entire length of a cell stπpe, i.e., the entire distance which any cell 520 can write. Because the die size 556 is larger than the cell spacing 546, there is unused die stripe data, shown in the πghtmost two columns of TABLE 2, corresponding to the length of the die stripe from 20.07 mm to 21.50 mm which cell row "A' " could not write. The next line in TABLE 2 shows cell row "B' " writing the remaining part of the cell stripe data for die row "a' ": the section from 20.07 mm to 21.50mm - note that this is the part not wπtten by cell row "A' ". After cell row "B' " completes writing die row "a' ", the third line in TABLE 2 shows that cell row "B ' " then writes 0.00 mm to 18.64 mm of die row "b' ". Cell row "C " writes the remainder of die row "b' ": 18.64 mm to 21.50 mm. Subsequent lines in TABLE 2 describe the division ofwπtten die stripe data and unused die stripe data for cell rows "C " through "N' ", wπtmg die stπpe data for die rows "c' " through "m' ". Cell row "N' " writes 2.87 mm to 21.50 mm of die row "m' " and then is blanked until cell rows "A' " through "M' " finish writing wafer 504. Cell row "O' " is not used at all since it is outside the patterned area of wafer 504.

FIG. 6, illustrates how the pattern data for the dies 502 on wafer 504 is distributed to the cells 520 in cell array 540, consistent with the table above showing the coπelation between X-axis cell numbers 510 and the cell column data, as well as the correlation between Y-axis cell numbers and the cell row data. In FIG. 3, each beamlet pattern memory (BPM) 324 was shown to correspond to a single beamlet withm the cell array 540. TABLE 2 shows the sections of each die stripe written by each die row, given m distance (in mm) along each die stripe. To convert these distances to address steps along the die stripe, we divide by the pixel size, in this case assumed to be 25 nm. The following table shows conversions from distance to address steps for cell rows "A' ", "B' ", "M' ", and "N' " taken from TABLE 2:

Figure imgf000021_0001

In the table above, the distances along the die stripes (third column from left in the table), have been converted into pixels by dividing by 25 nm (the assumed pixel size). For example, 20.07 mm converts as follows: (pixels) = (distance in mm) / (25 nm) = (distance in mm) / (25 x 10"6 mm)

802815 pixels = 20.07 mm / 25 nm =20.07 mm / (25 x 10"6 mm)

The fifth column from the left converts the pixel numbers into the hexadecimal addresses used in BPM 324 beamlet addressing. The rightmost column shows the writing sequence for the segments of die stripes, as well as the segments of die stripes which are unused in each particular cell row. FIG. 6 illustrates the application of the hexadecimal addresses within the various cell rows "A' ",

"B ' ", .... , "N' " for the writing of wafer 504. Across the top of FIG. 6, the die stripe numbers from TABLE 1 are shown for the corresponding cell columns "A", "B", .... , "N". In FIG. 6, each memory block 602 represents the collection of 32 BPMs die stripe memories 604, each supplying blanking data to a separate beam blanker 112 within the optical column. During writing of a single die stripe, memories 604 would correspond to memory bank 'A' 410 in a BPM 324. For the next die stripe, the other or memory bank 'B' 412 would be used in a 'ping pong' alternating use method, as described in FIG. 4. FIG. 6 shows the maximum die stripe data storage capability m this embodiment, allowing for a die stripe 30.0032 mm long, giving a maximum number of pixels:

1200128 pixels = 30.0032 / 25 nm

Since the first pixel has hexadecimal address OOOOOOh, the top addresses in memory banks 'A' 410 and 'B' 412 are 124FFFh in hexadecimal (=1200127), as shown at the top of each memory bank 604 in FIG. 6.

Within each memory block 602, the 32 memories 604 are labelled "0" through "31" for each cell column "A", ... , "O", shown m FIG. 6, coπespondmg to the numbering of individual beamlets 150 withm the particular columns 100 in the cells 520 corresponding to the memory banks 602. FIGS. 7 and 8 illustrate the patterning of a 300 mm wafer 704 for the case of dies 702 smaller than the X-Y spacing 546 of the cells 520. In this example, the size of dies 702 is 18 944 mm x 18.944 mm, corresponding to an integral number (=185) of die stripes 204 (where 185 x 102.4 μm = 18.944 mm). The spacing 546 of cells 520 is also an integral number (=196) of stπpes 204 wide (where 196 x 102.4 μm = 20.0704 mm) - note that in the present invention, since the spacing 546 of cells 520 is fixed, it is shown the same in FIGS. 5a and 7a.

In FIG. 7a, dies 702, 300 mm wafer 704, wafer exclusion area 705, wafer edge 706, X-axis cell numbers 510, Y-axis cell numbers 512, cells 520, X-axis cell boundaries 530, Y-axis cell boundaries 532, and cell spacing 546 are shown. FIG. 7a shows the arrangement of a total of 157 dies 702 on a 300 mm diameter wafer 704, assuming a 6 mm edge exclusion, i.e., no dies can extend into the area 705 of wafer 704 which is withm 6 mm distance measured radially inwards from the edge 706 of the wafer 704. The X-axis 530 and Y-axis boundaries 532 of the cells 520 are shown as dashed lines, while the X-axis and Y-axis edges of the dies 702 are shown as solid lines. Because the sizes of the dies 702 differ from the sizes of the cells 520, there is a "beat" pattern between them as can be seen from FIG. 7a. For the example shown in FIG. 7, this means that each cell 520 writes an area larger than the area of a die 702. In general, most or all cells 520 will write more than one die 702. In some cases, however, cells 520 near the edge 706 of the wafer 704 may write only one die 702.

FIG. 7b shows a schematic cross-sectional side-view of FIG. 7a along a horizontal axis through the center of the wafer 704. In FIG. 7b, the cells 520, cell boundaries 532, 20.0704 mm cell spacing 546, cell array 540, dies 702, die edges 752, die dimension 756, and wafer 704 are shown. The "beat" pattern between the cells 520 and the dies 702, arising from the difference between the 20.0704 mm cell spacing 546 and the 18.944 mm die dimension 756:

Difference = 20.0704 mm - 18.944 mm = 1.1264 mm = 11 stripes can be seen from FIG. 7b. As the difference calculation indicates, the spacing 546 of the cells 520 is exactly 11 stπpes larger than the dimension 756 of the dies 502. In FIG. 7b, all the cells 520 in the leftmost vertical column of FIG. 7a are called cell column

"A". The next cell column to the right is "B", and so on, across the cell array 540 to the rightmost cell column "O".

A similar scheme is used for die 702 labelling. All the dies 702 in a vertical column at the left of the wafer 704 are called die column "a". The next die column to the right is "b", and so on, across the wafer 504 to the rightmost die column "o".

The cell column labels "A" through "O", and die column labels "a" through "o" are used in TABLE 3 to illustrate a second specific example of how the data path of the present invention distributes die stripe data to the cells 520 in the multibeam electron lithography system.

TABLE 3

Figure imgf000024_0001

TABLE 4 - -

Figure imgf000025_0001

FIG. 7b can also represent a cross-sectional side view of FIG. 7a along a vertical axis through the center of the wafer 704 if the labels are changed as follows:

A → A', B → B' ,... , N → N', O → O' where now all the cells 520 in the bottom horizontal row of FIG. 7a are called cell row "A' ". The next cell row up is "B' ", and so on up the cell array 540 to the topmost cell row "O". Similarly, the die 702 labels are also changed as follows: a → a', b → b', ... , n → n', o → o'

The cell row labels "A' " through "O' ", and die row labels "a' " through "o' " are used m TABLE 4 to illustrate the die stripe data pointers used for each cell row. Again, a "beat" pattern is evident. Although in this example, the vertical and horizontal die dimensions are shown the same (18.944 mm), this is not a requirement of the present invention.

TABLE 3 describes the allocation of die stripe data to all the cells 520 in the cell array 540 using the notation shown m FIG. 7b. For simplicity, the left edge 532 of cell column "A" is aligned with the left edge 752 of die column "a" (at the far left of FIG. 7a).

Referring to FIG. 7a, all cells 520 in cell column "A" will require the same die stripe data. Similarly, all cells 520 in cell column "B" will also require the same die stripe data, typically different data than for cell column "A". Similar considerations hold for cell columns "C" through "O" as for FIG. 5a. Similarly, in TABLE 3, the die column "a" refers to all of the three dies 702 in the vertical row at the left of the wafer 704 in FIG. 7a. Die column "b" refers to all of the 7 dies 702 in the next vertical row to the right, and so on, across the wafer 704 to die column "o" which refers to all of the three dies 702 in the πghtmost vertical row of the wafer 704.

The two left columns in TABLE 3, read top-to-bottom, correspond to FIG. 7b, viewed left-to-πght. At the top of TABLE 3 the die stripe data ("0" through "184" m the third and fourth columns from the left) correspond to all of the data for die column "a" and are written by cell column "A". The next line in TABLE 3 shows die stripes "0" through "10" of die column "b" being wπtten by cell column "A". This shows that because the size 756 of dies 702 is smaller than the spacing 546 of the cells 520, that cell column "A" writes both all of die column "a" and 11 die stripes of die column "b" for a total of 196 die stripes. The third line and fourth lines in TABLE 3 show cell column "B" first wπt g die stripes "11" through "184 of die column "b", then die stπpes "0" through "21" of die column "c", for a total of 196 die stπpes. TABLE 3 shows the complete distπbution of die stripe data for all the cell columns "A" through "O" of the cell array 540. Note that cell column "O" writes only 31 die stripes. From TABLE 3, we can now detemine the sequence of die stripe data being supplied simultaneously to each of the cells 520 m the cell array 540. The first die stripe supplied to cell column "A" is "0" of die column "a", for cell column "B" the first die stripe supplied is "11" of die column "b", for cell column "C" the first die stripe supplied is "22" of die column "c", and so on down the third column, labelled "Die Stripes, First" in TABLE 3, to cell column "O" for which the first die stripe supplied is "154" of die column "o".

For cell column "A", die stripes of die column "a" are written sequentially: "0", "1",

"2",....,"183", "184", followed by die stripes of die column "b": "0", "1",..., "10", for a total of 196 die stπpes At this point, the entire wafer 504 has been written by the cell array 540. For cell column "B", die stπpes of die column "b" are wπtten sequentially: "11", "12",..., "184", corresponding to the remaining 174 stripes for die column "b" which were not wπtten by cell column "A". Cell column "B" then writes die stripes of die column "c": "0", "1", .... , "21", for a total of 196 die stripes At this point, cell column "A" has also just completed writing 196 die stπpes and the entire wafer 704 has been written by the cell array 540 Similar considerations hold for cell columns "C", "D", .... , "M" m cell array 540. The case for cell column "O" is different because it is at the edge of the patterned area on wafer 704. The wπtmg sequence for cell column "O" is die stripes "154", "155",.... , "184" of die column "o", for a total of 31 die stripes At this point, there is no more patterning data for cell column "O", so it remains inactive (all beams 150 blanked) until cell columns "A" through "N" have completed 165 more die stripes, at which point the wafer 540 has been completely patterned.

TABLE 4 describes how the die stripe 204 data is used by each cell 520 along each cell row, i.e., in the perpendicular direction from the cell columns considered m TABLE 3. The correlation of the X-axis cell numbers 510 (from 0 through 14) and the Y-axis cell numbers 512 (from 0 through 14) with the required cell column data and cell row data is the same as for TABLES 1 and 2. The cell column data consists of the patterning data for the dies 702 being wπtten on the wafer

740. The cell row data tells each cell 520 the proper sequence for using the cell column data. FIG. 5a shows that all cells 520 along each cell column "A" through "O" write the same die stripe on all of the dies 702 in their respective die columns. For example from TABLE 3 (top line), all the cells 520 in cell column "A" initially are writing the same die stripe data into all the dies 702 in die column "a". However, FIG. 7a shows that the "beat" pattern between the die size 756 and the cell spacing 546 in the vertical (column) direction requires that each of the individual cells 520 along every cell column "A" through "O" must write the pattern data in a different sequence. The purpose of the cell row data "A' " through "O' " is to define the proper writing sequence for all of the cells 520 along each horizontal row of cells 520 across the cell array 540, where typically, the proper wπtmg sequence will be different for each cell row.

TABLE 4 is similar in some ways to TABLE 3 since both tables derive from the "beat" pattern between the writing areas of each cell 520 in cell array 540 and the areas of each die 702 on wafer 704. Since in this example, we have assumed that the X and Y dimensions 756 of dies 702 are the same (which is not part of the present invention), and because the X and Y cell spacmgs 546 are also the same (which is also not part of the present invention), then the corresponding X and Y "beat" patterns are identical. The leftmost two columns in TABLE 4 correspond to the second interpretation of FIG. 7b, described above, wherein the cell row labelling is "A' " through "O' " and the die row labelling is "a' " through "o' ". The top row of TABLE 4 shows that cell row "A' " wπtes the entire die stπpe from 0.00 mm to 18.94 mm of die row "a' ". Since the cells 520 can write cell stπpes 20.07 mm long, however, cell row "A' " next starts writing the beginning of die row "b' ", from 0.00 mm to 1.13 mm, at which point a full 20.07 mm cell stripe has been written (18.94 mm + 1.13 mm = 20.07 mm). Note that since all the dies 520 along each cell column "A" through "O" use the same die stripe data, die row "b' " is written with the same die stπpe data as die row "a' ", thus the rightmost two columns in TABLE 4 show the reused die stπpe data. This reused die stπpe data is used first to pattern die row "a' " and then second to pattern the beginning of die row "b' ". Similarly, TABLE 4 shows cell row data allocations for die rows "c' " through "o' " Note that for cell row "O' ", die row "o' " from 15.77 mm to 18.94 mm is written, after which all the cells 520 m cell row "O' " are blanked until cell rows "A' " through "N' " complete writing wafer 704. TABLE 4 shows that for cell row "O' ", there is unused die stπpe pattern data: 0.00 to 15.77 mm of the die stπpe - this situation results from the fact that cell row "O' " is at the edge of the patterned area of wafer 704.

FIG. 8, illustrates how the pattern data for the dies 702 on wafer 704 is distributed to the cells 520 in cell array 540, consistent with the table above showing the correlation between X-axis cell numbers 510 and the cell column data, as well as the correlation between Y-axis cell numbers and the cell row data.

In FIG. 3, each beamlet pattern memory (BPM) 324 was shown to correspond to a single beamlet withm the cell array 540. TABLE 4 shows the sections of each die stripe written by each die row, given in distance (in mm) along each die stripe To convert these distances to address steps along the die stripe, we divide by the pixel size, in this case assumed to be 25 nm. The following table shows conversions from distance to address steps for cell rows "A' ", "B' ", "M' ", and "N' " taken from TABLE 4-

Figure imgf000029_0001

In the table above, the distances along the die stripes (third column from left in the table), have been converted into pixels by dividing by 25 nm (the assumed pixel size). For example, 18.94 mm converts as follows:

(pixels) = (distance in mm) / (25 nm) = (distance in mm) / (25 x 10"6 mm)

745471 pixels = 18.94 mm / 25 nm =18.94 mm / (25 x 10"6 mm)

The fourth column from the left converts the pixel numbers into the hexadecimal addresses used in BPM 324 beamlet addressing. The rightmost column shows the writing sequence for the segments of die stripes, as well as the segments of die stripes which are unused in each particular cell row.

FIG. 8 illustrates the application of the hexadecimal addresses within the various cell rows "A' ", "B' ", .... , "O' " for the writing of wafer 704. Across the top of FIG. 8, the die stripe numbers from TABLE 4 are shown for the corresponding cell columns "A", "B", .... , "O". In FIG. 8, each memory block 602 represents the collection of 32 BPMs die stripe memories 604, each supplying blanking data to a separate beam blanker 112 within the optical column. During writing of a single die stripe, memories 604 would correspond to memory bank 'A' 410 in a BPM 324. For the next die stripe, the other or memory bank 'B' 412 would be used in a 'ping pong' alternating use method, as described in FIG. 4. FIG. 8 shows the maximum die stripe data storage capability in this embodiment, allowing for a die stripe 30.0032 mm long, giving a maximum number of pixels: 1200128 pixels = 30.0032 / 25 nm

Since the first pixel has hexadecimal address OOOOOOh, the top addresses in memory banks 'A' 410 and 'B' 412 are 124FFFh in hexadecimal (=1200127), as shown at the top of each memory bank 604 in FIG. 6. Withm each memory block 602, the 32 memories 604 are labelled "0" through "31" for each cell column "A", ... , "O", shown in FIG. 8, coπespondmg to the numbering of individual beamlets 150 within the particular columns 100 in the cells 520 corresponding to the memory banks 602.

What follows is a second embodiment of the data path design. While the first embodiment was designed to use as many commercially available components as possible, thus saving time and cost, the second embodiment is an effort to improve the flexibility and performance of the design, to improve the packaging by reducing the total required board count and to reduce the number and power requirements of those components in the vacuum to reduce the amount of heat generated.

This second embodiment increases the amount of preprocessing the information goes through before the system begins replicating the die. Unlike embodiment one, in this embodiment, the die layer information is reduced to pixel data pπor to actual writing of the patterns. This greatly increases the amount of intermediate memory storage, but also greatly improves performance. This also eliminates the need for aligning die patterns and die pattern sizes on cell stπpe boundaries. This embodiment takes advantage of the data structure to reduce the amount of total memory required m the vacuum by having all cells in a common column of cells access different locations in the same physical memory for the data, rather than creating a unique copy of the die data for each cell. This embodiment also simplifies the task of generating the intermediate format files and reduces the resultant file size by maintaining the data storage in die stripe width rather than reducing the data to sub-stripe components m the intermediate file format as assumed m embodiment one. In this embodiment of the data path design, the stage scans along the X-axis, with each cell writing a 102.4 μm x 20.0704 mm strip of pixels on the wafer, called a cell stripe. A line of cells 520 along the stage scan axis is called a row of cells. The stage scan axis is the X-axis in this embodiment of the data path design, and the primary beam scan axis is the Y-axis. This designation is purely arbitrary and used as a convenient convention. As previously discussed, a die stπpe is a stπpe of pixels that is 102.4μm wide and as long as the die. If the die is wider than the cell spacing, then a cell stripe will consist of a subset of the die stπpe. On the other hand, if the die is narrower than the cell spacing, then the cell stripe will consist of whole and fractional sections of the die stπpe. Thus, withm a row, each cell writes different sections of the same die stripe. This data commonality, along each row, is exploited m the Data Path architecture of the present invention. In this embodiment of the data path design, the all cells 520 along a single row of cells 520 are driven so that the data they write is read from different portions of the same memory image of the die stripe data currently being wπtten.

The dies that the cells 520 have caused to be written are put down in repeating patterns that are parallel to the cells 520 themselves. The term "row of cells" 520 has been defined to mean a line of cells 520 parallel to the scan direction of the stage. By inspecting the repeating nature of the data, it is seen that if the die size happens to match the cell writing size that every cell 520 in a row will cause the same data to be written While this scenario will not often occur, an expansion of this concept shows that even when the cell writing size does not match the die size, the cells 520 are, at any given point in time, writing data from different locations in the same stπpe. If a single stripe of die data were stored m a memory array that could be accessed simultaneously by multiple sources, all cells in a given row could be driven from a single memory containing one stripe of die data. This is what this embodiment of the invention incorporates. For a more detailed look at the relationship between die pattern size and cell stripe length, refer to figures 5b and 7b and tables two and four. The tables provide a graphical representation of the relationship between cell size and die size, while the tables show which component of each die stripe (withm the die stripe buffer memory 1212) is being written. While each cell 520 within a row of cells 520 is writing different components of the same die stπpe, different rows of cells 520 are writing different stripes Even so, the data can be organized and accessed such that stripe data is more rapidly loaded into the row buffer boards 924.

At a simple level, the data path can be described as a collection of embedded processors, custom designed ASICs, SDRAMs, glue logic, and software. A block diagram of this implementation of the data path is shown in figure 9. Included are Ethernet link 910, which is used by the controller 906 to bring in pattern data from an outside source and the Pattern Library Storage (PLS) 902, which communicates to the controller 906 through the high speed data bus 904. The controller 906 communicates to the raster image processor (RIP) 916 through the image data link 908. The raster image processor (RIP) 916 converts the pattern data into raster data which is then passed, die stripe by die sfripe, through the raster image pipeline 1116 to the row buffer board 924 array 922. The array 922 contains 15 row buffer boards 924 each communicate to the cell 520 array blanking plates 928 via the communication lines 926 that drive blanking plates 112 for all 32 beamlets 150 in each of 15 cells m a row (also see fig. 1). It should be noted that the row buffer board 924 array 922, the communication lines 926 and the call 520 array blanking plates are mounted inside the vacuum enclosure 920, leading to unique implementation issues for the raster image pipeline 1116, which must pass the data through the vacuum barπer.

In this implementation of the Data Path, data is processed in die stπpes in "Just In Time" fashion. This means that while the system is actually writing the structures for a single stripe, the Data Path is loading the row buffer memories with the data necessary to write the next stripe. The hierarchically organized data for a single chip is stored m a format and organization that minimizes file size (typically GDS-II format). It is highly compressed and hierarchical and because it contains all layers - dies - of the chip, makes the file unusable by the multibeam electron lithography (MEL) data path. An off-line pattern preparation system pre-processes the file into a format that can be used directly. This format separates the information necessary for a single layer of the circuit design in question into die stπpes m the order needed by the rows of cells. This preparation also decomposes the original data format polygonal structures into simpler trapezoids. This intermediate format will expand the data, multiplying its size by a factor of approximately four (4). A single layer will take between 4 Mbytes and 800 Mbytes of storage.

A multibeam electron lithography (MEL) system will include a Pattern Library Storage (PLS)

902 subsystem, which will contain intermediate format files for all the layers, or dies, to be used by the lithography system. All dies of a single chip, stored in intermediate format, will require between

40 Mbytes and 8 Gbytes of storage. The total size of the PLS 902 is arbitrary as long as there is sufficient storage to allow all intermediate format copies of the requisite data representations of all necessary dies. A storage medium capable of holding 500 Gbytes of information would be capable of holding dozens of die data files in intermediate format. In a specific implementation of the data path design, the functionality of the PLS 902, the combination of the high speed data bus 904 and the controller 906 can be provided by a high-end commercially available file server. The data transfer rate is extremely high and the eπor rate in the data that such a system would deliver to the raster image processor (RIP) 916 is essentially zero, as high-end file servers are designed to operate for many years without an undetected or uncorrected bit error. These types of computers make extensive use of error correction code (ECC) hardware and software.

The controller 906 can be used as the conversion engine for converting the original data format to the intermediate format and storing it in the PLS 902. Alternately, an off-line engine may serve to convert the original circuit design file to the intermediate format. If this were the case, the intermediate files would be downloaded through the Controller 906 to the PLS 902 through the available Ethernet link 910.

During lithography, the controller 906 is the first stage of the Data Path pipeline. During lot transition, the controller 906 will transfer the required die layer data file from the PLS 902 across the high speed data bus 904 and send it to the RIP 916 across the image data link 908. The system cannot begin processing wafers until the RIP 916 has completed rasterizing the die data.

Figure 10 shows a specific implementation of the raster image processor (RIP) 916. The data is received from the image data link 908 by the geometry processor 1106, which converts the trapezoid pattern data to write commands and block transfer (BIT) commands and passes them to the raster ASICs via the internal command bus 1108. The raster ASICs execute these commands and transfer the resultant pixelated die data to the internal 320 Gbyte pixel RAM array 1112 across the internal memory bus 1114, a bi-directional link between the pixel RAM array 1112 and the raster ASICs 1110. When the system is writing the die data, the data is read, in stripe format, from the pixel RAM array 1112 by the raster ASICs 1110, and is transferred across the internal pixel memory bus 1114 and out the raster image pipeline 1116. The RIP 916 is the second stage in the Data Path pipeline, and is used to convert the intermediate format data into a bitmap pattern for the entire layer. The raster image processor (RIP) 916 receives the geometrically represented data across the image data link 908 from the controller 906. The geometry processor 1106 traverses the incoming intermediate format data and decomposes the representation - still in a shallow hierarchical form in simple trapezoid geometries - into a flat representation set of trapezoid draw commands and block transfer (BIT) commands. The Raster

ASICs 1110 execute these commands, transfering the pixelated data across the internal pixel memory bus 1114 into the pixel RAM aπay 1112, thus generating the bitmap pattern for the full die layer.

When complete, the pattern, stored in the 320 GByte pixel RAM array 1112, can be read out, in stripe order, by the raster ASICs 1110 and sent to each of the 15 row buffer boards 924.

The raster image processor (RIP) 916 is a high speed, raster image processor that requires fast polygon drawing rate (>4 Gpixels/sec), pixel RAM array 1112 with storage for the current layer (> 320 Gbytes), and a high speed data interface to subsequent stages of the Data Path through the raster image pipeline 1116. Bi-directional communications capability is desirable across the raster image pipeline 1116 for verification and timing purposes. The raster image pipeline 1116, like many of the communication busses described in this embodiment of the Data Path patent, can be implemented using a number of different technologies and protocols, such as UltraFastWide SCSI, Gigabit Ethernet and Fibre Channel. The latter is extremely high speed (>4 Gpixels/sec), robust and can be implemented over a variety of media, including fiber optic, twisted pair and co-axial cable as well as over certain local bus designs. While local bus (or back plain), twisted pair cable or co-axial cable are preferred for their ease and simplicity within a single equipment rack, fiber optic cable has many advantages for the design of the raster image pipeline 1116, as this would simplify the problems associated with running multiple high speed communications cables in parallel in a noisy, high voltage environment and would solve the problems associated with passing cables through a vacuum barrier. An implementation of the raster image pipeline 1116 that included an individual high speed Fibre Channel from the RIP 916 to each of the 15 row buffer boards 924 would provide an aggregate data transfer capability of 60 Gpixels/sec. The design of the RIP 916 should incorporate features to provide a high level of reliability and availability, and should minimize design and verification complexity, risk and cost.

The stage transit time from the start of one cell stripe scan to the start of the neighbor cell stripe scan, assuming a 20 mm cell stripe length, is roughly 500 ms. This is the time allowed to load the appropriate die stripe data for the next stripe to be written from the raster image processor (RIP) 916 raster memory 1112 into the memories 1212 of the array of row buffer boards 922 (see fig. 9). Each row buffer board 924 contains enough memory 1212 to contain two die stripes - the die stripe that is currently being written and the die stripe that is currently being downloaded from the Raster Image Processor (RIP) 916 through the raster image pipeline 1116.

Figure 11 shows a specific implementation of row buffer board 924, one of 15 row buffer boards 924 in the row buffer board array 922 (see fig. 9). In this implementation, the internal design is broken up into 16 row buffers 1220, each intended to handle the data for two (2) cell sub-stripes and to drive the blanking control for two (2) beamlets 150 within each of the 15 cells in a cell row. Each row buffer board 924 receives the data from the raster image processor 916 through the raster image pipeline 1116, which is designed to send data to all 15 row buffer boards 924 simultaneously. The data coming in from the raster image pipeline 1116 is fed to the clock and data recovery driver 1206, as is a common clock signal. The data which is being fed to the clock and data recovery is broken up into groups of two pixels and sent across the internal data communication bus 1208 to the row buffer

ASICs 1210. The row buffer ASICs send this data across the internal stripe memory pixel bus 1214 to the alternate stripe buffer in the stripe buffer memory 1212, which consists of a 32Mbyte SDRAM array. The common clock signal is fed to all row buffer ASICs 1210 which, in turn, use this signal to drive the blanking signal for the individual pixel data, and is fed directly to the 15 cells as a blanking gate pulse to aid in pixel write precision.

There are 15 row buffer boards 924 in the system, one for each row of cells in the array. Each row buffer board 924 double buffers two die stripes of pattern data, loaded from the Raster Image Processor (RIP) 916. During writing, the row buffer board 924 reads each cell's appropriate piece of the die stripe. Custom circuitry within each row buffer 1220 in this implementation directly drives the blanker plates for two (2) of the beamlets 150 within each of the 15 cells within the cell row with this pattern data. Each row buffer 1220 thus drives 30 blanker plates. The row buffer board 924 also contains the clock recovery and blanking gate hardware.

In general, the row buffer board 924 functions are to input the pattern data from the raster image processor (RIP) 916 into the alternate stripe buffer of the stripe buffer memory 1212, to output the pattern data, as needed, to each cell in the row. In the implementation shown in figure 11, the structure is further broken down into 16 discrete row buffers 1220, each of which handles the data for two beamlets 150 within a cell for every cell within the cell row controlled by this row buffer board 924. A very important additional function is the recovery of the 250 MHz blanking signal clock and the generation of the 2 ns blanking gate pulse. Each row buffer board 924 contains 16 row buffer ASICs 1210, and 64 each 4 Mbit 3 16 bit wide double data rate (DDR) synchronous dynamic random access memory (SDRAM) 1212, organized into 16 discrete row buffers 1220. This partitioning accomplishes two goals - the row buffer ASIC 1210 pin count is kept in the range of 208 to 240 pins, keeping the packaging within industry standards, and there is no duplicated die stripe pattern data within the SDRAMs 1212. The complete set of 15 row buffer boards 924 will contain 240 row buffer ASICs 1210 and 960

SDRAMs 1212.

All 15 row buffer boards 924 can be located within the vacuum chamber (within which the cells are located), which is desirable because of the cost and complexity of vacuum feedthroughs. If the row buffer boards 924 were outside the vacuum, the system would require 6,600 vacuum feedthroughs. Putting the row buffer boards 924 inside the vacuum reduces this count to 540. The row buffer boards 924 will generate a significant amount of heat, but this heat can be removed by installing liquid cooled plates sandwiched between each of the row buffer boards 924. Figure 12 shows a block diagram of a single row buffer 1220 as shown within a row buffer board

924 in figure 11. Data and control signals come into the input FIFO 1304 of the row buffer ASIC

1210 through row buffer board 924 internal data communication bus 1208. For completeness, the internal data communication bus 1208 is broken into the data pathway 1308, which flows only into the input FIFO 1304, and the control signal pathway 1306, which is bi-directional. Data is read across the internal bi-directional communications link 1312 from the input FIFO 1304, and control signals are sent to control signals are sent to the input FIFO 1304, by the Memory Queue and Driver Interface

1310. Data is then sent across the internal stripe memory pixel bus 1214 to the alternate stripe buffer in the stripe buffer memory 1212, which consists of a 32Mbyte SDRAM array. For completeness, the internal stripe memory pixel bus 1214 is broken into the address and control signal path 1316, which flows only into the stripe buffer memory 1212, and the data path 1314, which is bi-directional. When the row buffer drives the beamlets 150 in the cells of the cell row to write data, the output logic driver 1318 requests the memory queue and interface driver 1310 to read the appropriate data from the primary write stripe buffer of the stripe buffer memory 1212. The data is received across the internal stripe memory pixel bus 1314 by the memory queue and interface driver 1310 and then sent to the output logic driver 1318 over the data path 1320. The output logic driver then clocks all 30 blanking signals to the appropriate cell blanking lines 1322 simultaneously.

The row buffer ASIC 1210 contains all the logic to support the bitmap buffering and blanking drive for two beamlets 150 (see fig. 1) in all 15 cells within a row of cells. It should be noted that a single row buffer board 924 contains 16 row buffers 1220, enough to drive all beamlets 150 that constitute the output of all cells within a single row of 15 cells.

The row buffer ASIC 1210 controls 32 MB of SDRAM 1212, loads pattern data, from the raster image processor 916 into SDRAM 1212, reads and serializes the pattern from the SDRAM 1212, and sends 30 blanker signals along blanking lines 1322. A specific iteration of the design embodiment shown in figures 9 through 12 that includes error correction hardware is shown in FIG. 13. Included are the Pattern Library Storage (PLS) 902, which communicates to the controller 906 through the high speed data bus 904. The controller 906 communicates to the raster image processor (RIP) 916 through the image data link 908. The raster image processor (RIP) 916 converts the pattern data into raster data and generates cyclic redundancy check (CRC) information. The data and appropriate CRC information are then passed, die stripe by die stripe, through the raster image pipeline 1116 to the row buffer board 924 array 922. The array 922 contains 15 row buffer boards 924, each with 320 Gbytes of row memory with error correction code (ECC) logic 1008, which is the error correcting equivalent of stripe buffer memory 1212. As each generate the data to communicate to the cell array blanking plates 928, check CRC logic 1006 checks for communications and network data errors and communicates these back to the RIP 916 via the communication lines 1002. Only if no errors are detected are the blanking signals sent out communications lines 926 that drive all 32 beamlet 150 blanking plates in each of 15 cells in a row. The two primary types of errors are classified as hard and soft. Hard errors are component failures which require the replacement of the failed component. Reliability requires a design which minimizes these failures as well as simplifying the diagnosis of them. Soft eπors are random, non- repeatable errors that are typically caused by electrical noise and radiation, and are transient in nature. Reliability requires a design that can detect and correct these errors on the fly.

To accommodate the high volume of pixel data withm the multibeam electron lithography

(MEL) system, the raster image processor (RIP) 916 will require a 320 Gbytes pixel RAM array 1112 and 100 instances of custom ASICs 1110. These devices typically exhibit 25 failures per billion device hours (commonly called FITs), which would give a mean time between failures (MTBF) for the raster image processor 916 of 23,000 hours.

Should the need be foreseen for longer MTBF, redundancy and automatic monitoring systems can be included in this implementation of the design. In addition, this implementation accommodates easy diagnosis and replacement of subsystems and components.

The row buffer boards 924 in this embodiment include self-checking logic. This includes such error handling hardware as cyclic redundancy check (CRC) 1006 for the blanking data to the tips, as well as fault tolerant hardware (row memory with ECC 1008 and other corrective measures, such as redundant circuitry).

Production SDRAMs now have soft error rates of between 100-15,000 failures per billion device hours (FITs). Assuming the pessimistic number of 15,000 FITs, without ECC, the combined raster image processor 916 and row buffer boards 924 will see one soft error, resulting in a single bad pixel, every 26 hours. At 30 wafers per hour per write head, the system would write one bad pixel every 780 wafers. Addition of Row Memory with Error Correcting Code (ECC) hardware 1008 will bπng the uncorrectable soft error rate to one error every 44 trillion years.

An alternative to ECC memory is to have CRC for the raster image processor (RIP) 916 hardware that will generate CRC Check codes withm the row buffer 1004. This can be used to correct errors in the row buffer board 924 and can detect (but not correct) hard and soft errors in the RIP 916. When an error is discovered by the CRC logic (comprising the Extract CRC block 1004 supplying the CRC to the Check CRC 1006 block, which compares the CRC with a second CRC generated from the data supplied by the row memory 1008), the line data is prevented from reaching the blankers by the output logic 1318 of the row buffers 1220 The stage would then be stopped, turned around and the stπpe re-tπed starting at the next unwritten line. Note that this stripe re-try should happen only once every 26 hours. On a subsequent failure, the data would be re-rasteπzed and the stπpe fried again. If an error is detected again, the machine stops writing and reports a hard failure. Note that a hard failure like this should happen only once every 2.5 years and is resolved by replacing the faulty hardware.

Another potential source of soft errors is the transmission of data from the RIP 916 to the row buffer boards 924. For 25nm pixels, a 300mm wafer has 1014 pixels. Assuming a tolerance of one (1) pixel error per 100 wafers the data link between the RIP 916 and the row buffer boards 924 will need a bit error rate of 10"16. A typical data link suitable for use for the raster image pipeline 1116 between the RIP 916 and the row buffer boards 924 has an uncorrected Bit Error Rate of 10"5. A commercially available forward error correction chipset is typically capable of improving this bit error rate to 10"20, which is more than adequate. This forward error correction strategy is not shown in figure 13.

The foregoing descriptions of various embodiments of the invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise forms disclosed. Many modifications and equivalent arrangements will be apparent. For instance, the data path design could be used for a multiple ion beam system. Furthermore, the data path design could be used for any lithography system with more than one cell in conjunction with more than one charged particle beam per cell.

Claims

WHAT IS CLAIMED IS:
1. A data process and distribution system for multiple beam lithography comprising: a pattern library storage device; a controller connected to the pattern library storage device; a sub-stripe storage array connected to the controller; a multiplicity of decompression engines connected to the sub-stripe storage array; a multiplicity of beamlet pattern memories connected to the decompression engines; and a multiplicity of blankers connected to the beamlet pattern memories.
2. The data process and distribution system of claim 1, wherein there is one blanker connected to each beamlet pattern memory.
3. The data process and distribution system of claim 1, wherein there are a multiplicity of beamlet pattern memories connected to each decompression engine.
4. A data process and distribution system for multiple beam lithography comprising: a pattern library storage device; a controller connected to the pattern library storage device; a raster image processor connected to the controller; a multiplicity of row buffers connected to the raster image processor; and a cell array connected to the row buffers.
5. The data process and distribution system of claim 4, wherein each row buffer is connected to a row of cells.
6. The data process and distribution system of claim 4, wherein the raster image processor comprises: a geometry processor connected to a raster ASICS; and a SDRAM connected to the raster ASICS.
7. The data process and distribution system of claim 6, wherein the SDRAM comprises a memory sufficient to store a complete die pattern.
8. The data process and distribution system of claim 4, wherein each row buffer comprises a memory sufficient to store one die stripe of data.
9. The data process and distribution system of claim 4, wherein the raster image processor further comprises ECC and CRC hardware.
10. The data process and distribution system of claim 4, wherein the row buffer further comprises ECC and CRC hardware.
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