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WO2001024019A1 - Embedded computer system and method with internal bus interface logic - Google Patents

Embedded computer system and method with internal bus interface logic

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Publication number
WO2001024019A1
WO2001024019A1 PCT/US2000/025429 US0025429W WO2001024019A1 WO 2001024019 A1 WO2001024019 A1 WO 2001024019A1 US 0025429 W US0025429 W US 0025429W WO 2001024019 A1 WO2001024019 A1 WO 2001024019A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
memory
system
window
address
register
Prior art date
Application number
PCT/US2000/025429
Other languages
French (fr)
Inventor
Raymond Brinks
Kaido Kevvai
Andrus Aaslaid
Jüri-Henrik PÕLDRE
Gustav Poola
Original Assignee
Zf Linux Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0653Configuration or reconfiguration with centralised address assignment
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20Employing a main memory using a specific memory technology
    • G06F2212/202Non-volatile memory
    • G06F2212/2022Flash memory

Abstract

Embedded computer system (10, Figure 1) with internal logic (14, Figures 1 and 2) for mapping a plurality of external I/O devices (23) to the system memory. In the disclosed embodiments, the system includes an ISA bus (21) to which the devices are connected, and the devices are mapped to the ISA bus space in the system memory. A starting address register (26), a window size register (27), and a status register (28) are provided for each of the external devices.

Description

EMBEDDED COMPUTER SYSTEM AND METHOD WITH INTERNAL BUS INTERFACE LOGIC

This invention pertains generally to embedded computer systems and, more particularly, to an embedded computer system and method having a internal logic for controlling external memory and input/output (I/O) devices.

U.S. Patent 5,742,844 discloses an embedded computer module in a package the size of an integrated circuit, with the functionality of a desktop computer. The module includes an Intel X86 processor, serial and parallel interfaces, drive controllers, a keyboard interface, a DRAM interface and flash memory.

A more recently developed system includes a complete processor and peripheral subsystem on a single chip, with the only external components being a clock, SDRAM and a flash memory containing system start-up code (BIOS) and/or application software.

Such systems generally have logic outside the system controller for controlling external memory and I/O devices, and require external control lines and timing.

It is in general an object of the invention to provide a new and improved embedded computer system and method with internal logic for controlling external memory and I/O devices. Another object of the invention is to provide an embedded computer system and method of the above character overcome the limitations and disadvantages of the prior art.

These and other objects are achieved in accordance with the invention by providing an embedded computer system and method with internal logic for mapping a plurality of external I/O devices to the system memory. In the disclosed embodiments, the system includes an ISA bus to which the devices are connected, and they are mapped to the ISA bus area of the system memory. A starting address register, a window size register, and a status register are provided for each device.

Figure 1 is a block diagram of one embodiment of an embedded computer system with a internal bus interface logic incorporating the invention.

Figure 2 is a simplified block diagram of the bus interface logic in the embodiment of Figure 1 .

Figure 3 is a diagram illustrating the mapping of an external memory device to system memory in one embodiment of a system incorporating the invention.

Figure 4 is a diagram illustrating the layout of the memory settings registers in one embodiment of a system incorporating the invention.

The embedded computer system illustrated in Figure 1 is constructed on a single chip 10 packaged in a 35 mm, 388 pin ball grid array (not shown). The system includes a processor core 1 1 which in one embodiment comprises a standard X86 processor (e.g., Intel 386) with an integrated floating point co-processor and 8K bytes of write-back level 1 cache. The system also includes a north bridge system controller 1 2 with a frontside PCI interface and an SDRAM interface, and a south bridge controller 1 3 having a frontside PCI interface to the north bridge controller and a backside PCI system interface. The south bridge controller also has an enhanced ICE controller which supports two devices on a single channel, a USB controller with two hub ports, a real time clock, a floppy disk controller, serial ports, an access bus, a keyboard and mouse controller, a parallel port, general purpose programmable l/O's and counters, PC/AT system components, and power management. The PC/AT system components include DMA controllers, interrupt controllers, a system timer, and an ISA bus interface.

A logic module 14 is connected internally to the ISA bus and uses external pads on the chip to control external devices. This module includes general purpose and specific chip selects, a watchdog timer, and a flash controller, and is discussed in greater detail below.

A BIOS update ROM (BUR) 1 6 on the chip contains the minimal necessary code to read data into the chip and to update an externally connected flash memory device 1 7. The connection between the chip and the flash memory device can be made either via a serial port or by multiplexing the floppy disk drive interface between the floppy disk drive and the flash memory device. The serial connection utilizes a standard UART1 embedded in the chip, and allows a remote PC with special host software or to access the flash device to do the update. This approach can be used only in applications where the serial port is not hardwired to an external device and where access to the serial port is physically possible. The use of the floppy disk drive interface for the flash memory is disclosed in detail in Serial No. , filed of even date.

The logic module includes bus interface logic for mapping external memory and I/O devices to the system memory. This logic is internal to the system controller, and is included in the chip. In the embodiment illustrated, the system includes an ISA bus 21 to which the memory and I/O devices 22,

23 are connected, and the devices are mapped to the ISA I/O space in the system memory.

As illustrated in Figure 2, a starting address register 26, a window size register 27, and a status register 28 are provided for each of the external devices. The ISA bus starting address is stored in the address register, the ending address or length is stored in the window size register, and the status of the chip select is stored in the status register. In one present embodiment, eight sets of registers are provided, and eight chip selects can be configured for four memory address spaces and four I/O address spaces. When new data is written into either a starting register or a window size register, a check is made to ensure that it does not overlap with existing data. If it does, the new window is not enabled.

The external memory and I/O devices are connected to the ADDRESS, DATA and MEMWR lines of the ISA bus. Each device has a dedicated chip select which is generated by the system logic. The devices can be up to

24 Megabytes deep, occupying all 24 ISA address lines, and are accessed through windows in the memory space. In the DOS mode, the windows can be up to 256 Kbytes deep and can reside only in the upper 1 Mbyte DOS ROM area (COOOO-FFFFF). In the protected mode, the windows can occupy all 24 ISA address lines (OOOOO-FFFFF), and this area is accessed through memory space above the system SDRAM. If the address is not in the system memory and no PCI device claims it, then it is forwarded to the ISA bus. This makes the ISA bus appear multiple times in the upper memory area.

With external flash memory, a separate window is defined for each memory device, with the following parameters: Window size

Starting address

Flash page All parameters are aligned with 8 Kbyte increments in the system memory. After writing new data to either window size or starting address, a check is made to ensure that the windows do not overlap. If they do, the new window is not enabled. The configuration status can be read from the window status register, and the access mode can be changed from a window control register, as discussed further below.

Page registers are translated on-the-fly via the ISA bus address lines. If an active window is accessed, then the page register is multiplexed to the external ISA upper address lines. Since the ISA address lines are stable during the entire memory cycle, the flash memory devices can be connected directly to the ISA bus lines. The flash window mapping is illustrated in Figure 3.

For external memory devices, the register map of the memory decode area is as follows:

First window settings

30h CSO window size 34h CSO page 38h CSO starting address

Second window settings

40h: CS1 window size

44h: CS 1 page

48h: CS1 starting address Third window settings

50h CS2 window size 54h CS2 page 58h CS2 starting address

Fourth window settings

60h: CS3 window size

64h: CS3 page

68h: CS3 starting address

71 h Access mode

70h Status

74h Debug

where CSO - CS3 are the chip selects for the four windows.

The starting address, window size and page define the mapping for each of the four external memory devices. The mapping is disabled when the window size is zero. The starting address, window size and page registers are 32-bit registers, each of which consumes four 8-bit registers in the system register space. In the 32-bit registers, the bytes are ordered with the base + 0 bits in bits 0-7 of the registers, the base + 1 bits in bits 8- 1 5 of the registers, the base + 2 bits in bits 1 6-23 of the registers, and the base + 3 bits in bits 24-31 of the registers. Window size, location and flash page can be set in 8 Kbyte increments, and the ISA bus limits the address space to 24 bits.

The layout of the memory settings registers is illustrated in Figure 4. The lower 1 3 bits must be zero in order to comply with 8 Kbytes increments, and the upper 8 bits are reserved because the ISA bus has only 24 address lines. As an example, 60 Kbytes of FLASH 0 memory starting at 1 60 Kbytes are to be mapped into RAM starting at 500 Kbytes. Since the registers can be changed in 8-Kbyte steps, the window size can be either 56 or 64 Kbytes.

Since 60 Kbytes are needed, a 64-Kbyte window is selected. The flash page remains the same, and the starting address in RAM is incremented to

504 Kbytes. These numbers are programmed into the CSO registers as follows:

Starting address 504 Kbytes 00 7e 00 00

Window size 64 Kbytes 00 01 00 00

Flash page 1 60 Kbytes 00 28 00 00

If the 8-Kbyte restriction were ignored and the ranges were written directly into the registers, then they would be truncated, then the window length would be 56 Kbytes instead of 60 Kbytes, the starting address would be 496 Kbytes instead of 500 Kbytes, and the flash page would remain unchanged at 0 Kbytes. Since the starting address and the flash page have changed, the data would be in the wrong location.

ISA upper addresses are accessed by using the area above 256 Mbytes, and above the system SDRAM the addresses are mapped to the ISA bus by the PCI-ISA bridge using subtractive encoding.

The control register is common for all four memory devices. The first four bits control the data width of the external memory device, and the lower four bits set the write enable mask to write protect the memory. These registers are configured as follows:

The status register is configured as follows:

A window is active when it does not overlap with another window in the system RAM. This run-time test is executed every time the memory mapping registers are accessed.

For the external I/O devices, each GPCS signal is assigned a window in the ISA I/O space. The largest window is 1 6 Kbytes. As in the case of the external memory devices, the windows cannot overlap, and an internal check is done to ensure that they do not before enabling the GPCS lines. Each GPCS signal can be inverted from the control register and separately enabled for reading, writing, or both.

A GPCS mapper creates I/O decoders for external GPCS signals. Each GPCS line has control and base registers, and the GPCS register area of the system memory is as follows:

GPCS 0 settings

80h: Control 82h: Base address

GPCS 1 settings

90h: Control 92h: Base address

GPCS 2 Settings

AOh: Control A2h: Base address

GPCS 3 settings

BOh: Control B2h: Base address

COh: Common status register.

Each of the base registers is 1 6 bits wide, and the windows can be defined anywhere in the 1 6-bit I/O space. The GPCS control register is configured as follows:

The signal inverter selects the active level of the GPCS line. The signal enable enables the decoder. The write enable masks the ISA I/O write signal, making the window read-only. The window size determines the window size in the ISA I/O space.

The GPCS base low byte register is configured as follows:

This byte is located at the GPCS base in the system register map. It determines the low byte of the window start address in the ISA I/O space. The GPCS base high byte register is configured as follows:

This byte is located at GPCS base + 1 in the system register map. It determines the high byte of the window starting address in the ISA I/O space.

The GPCS status register is configured as follows:

This register shows the status of the decoders, and the bits of the register mirror the status bits in each I/O window control register. After a power- on reset, the four GPCS signals are inactive. A runtime check is made after an access into the GPCS register area to verify that the windows do not overlap. A window become active when the windows do not overlap and the enable bit is set in the control register.

The invention has a number of important features and advantages. It puts the bus interface logic inside the chip with the rest of the system and eliminates the need for external control lines and timing. No external glue logic is required, and the user is provided with eight chip selects that can be configured to four memory address spaces and four I/O address spaces.

It is apparent from the foregoing that a new and improved embedded computer system and method with internal bus interface logic have been provided . While only certain presently preferred embodiments have been described in detail, as will be apparent to those familiar with the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.

Claims

1 . An embedded computer system formed on a single chip and including as an integral part thereof: internal system memory, a bus, and means for mapping to the system memory a plurality of memory devices and I/O devices which are connected externally to the bus.
2. The embedded computer system of Claim 1 wherein the bus is an ISA bus, and the memory devices and the I/O devices are mapped to the ISA bus area of the system memory.
3. The embedded computer system of Claim 1 wherein the means for mapping the memory devices and the I/O devices to the system memory includes a starting address register, a window size register, and a status register for each of the devices.
4. A method of controlling external memory and I/O devices with an embedded computer system having internal system memory and an externally accessible bus, the steps of: connecting the memory and I/O devices to the bus, and mapping the memory devices and the I/O devices to the internal system memory.
5. The method of Claim 4 wherein the bus is an ISA bus, and the memory devices and the I/O devices are mapped to the ISA bus area of the system memory.
6. The method of Claim 4 wherein starting address, window size, and status information is written into the system memory for each of the external memory devices and I/O devices.
PCT/US2000/025429 1999-09-27 2000-09-14 Embedded computer system and method with internal bus interface logic WO2001024019A1 (en)

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US40504499 true 1999-09-27 1999-09-27
US09/405,044 1999-09-27

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes
US5671433A (en) * 1992-09-18 1997-09-23 Vadem Corporation Mappable functions from single chip/multi-chip processors for computers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671433A (en) * 1992-09-18 1997-09-23 Vadem Corporation Mappable functions from single chip/multi-chip processors for computers
US5822610A (en) * 1992-09-18 1998-10-13 Vadem Corporation Mappable functions from single chip/multi-chip processors for computers
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes

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