WO2001022482A1 - Procede de production de couches de silicium-germanium decontractees - Google Patents
Procede de production de couches de silicium-germanium decontractees Download PDFInfo
- Publication number
- WO2001022482A1 WO2001022482A1 PCT/US2000/040938 US0040938W WO0122482A1 WO 2001022482 A1 WO2001022482 A1 WO 2001022482A1 US 0040938 W US0040938 W US 0040938W WO 0122482 A1 WO0122482 A1 WO 0122482A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- germanium
- layer
- source gas
- gas
- component
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/52—Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/0251—Graded layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
Definitions
- the invention relates to the field of relaxed SiGe layers.
- CVD is, under most conditions and products, the most economical method of depositing thin layers of crystalline semiconductors.
- High thin-film growth rates are essential in producing economical relaxed SiGe materials on Si substrates, since the SiGe layers are relatively thick.
- the highest growth rates known to date, which have been deposited in non-commercial equipment, have been achieved with CVD, with a maximum growth rate of about 6 micrometers per hour.
- CVD deposition equipment can become too coated with thin film deposit in areas other than the substrate area. If this deposition is too great, it may prevent a large number of consecutive wafer deposition processes, leading to greater cost.
- An additional problem is that in attempting to deposit films at high growth rates, gas-phase nucleation can occur, in which particles of SiGe, Si, or Ge form in the gas stream and subsequently deposit on the wafer surface.
- FIG. 1 is a graph showing the growth rate of epitaxial silicon as a function of growth temperature for a variety of Si source gases;
- FIG. 2 is a graph of the threading dislocation density at the surface of a relaxed
- FIGs. 3A and 3B are schematic block diagrams of exemplary structures with a uniform cap layer of Si,. x Ge x (0 ⁇ x ⁇ l) and Si 07 Ge 03 , respectively, on a silicon substrate using a relaxed SiGe graded buffer layer in accordance with the invention.
- FIG. 1 is a graph showing the growth rate of silicon versus temperature for various source gases. Two distinct growth regimes are evident. For low temperatures, the growth rate has an exponential dependence on temperature, indicating that the growth is reaction rate or kinetically limited. For high temperatures, the growth rate has a weak dependence on temperature, indicating that the growth is mass transport or diffusion limited. Epitaxial layers are formed in the mass transport limited regime to minimize the effects of temperature variations during growth.
- germane-chlorine-based gas used to increase the decomposition temperature.
- chlorogermanes can be used to extend growth temperatures to more than 200°C over germane growth temperatures without increasing gas phase nucleation. In this way, the decomposition temperatures of the gases can be optimally chosen such that very high growth rates can be achieved at high temperatures.
- the most readily available germanium-chlorine source gas is germanium tetrachloride, (GeCl 4 ). This gas, unlike germane, can be used at growth temperatures in excess of 800°C to grow thick, relaxed SiGe layers without excessive equipment coating and particle formation. It can be combined with any of the source gases for silicon, such as silane, dichlorosilane, trichlorosilane, and silicon tetrachloride to form high quality SiGe layers.
- FIG. 2 is a graph showing experimental data of dislocation density versus growth temperature for SiGe graded layers.
- SiGe relaxed buffers with a 30% Ge final composition cannot be grown much above 800°C without experiencing severe gas phase nucleation.
- FIGs. 3A and 3B are schematic block diagrams of exemplary structures with a uniform cap layer of Si !.x Ge x (0 ⁇ x ⁇ 1) and Si 07 Ge 03 , respectively, on a silicon substrate using a relaxed SiGe graded buffer layer in accordance with the invention.
- the structures include a monocrystalline silicon substrate 300, a SiGe graded buffer layer 302, and a uniform concentration SiGe cap layer 304, 306.
- the SiGe buffer layer 302 is a series of SiGe layers with increasing Ge concentration, usually with a gradient of less than 25% Ge per micron. By increasing the Ge concentration gradually, the strain due to the lattice mismatch between Si and Ge is relieved and the threading dislocation density is minimized.
- the cap layers are high quality
- SiGe layer with uniform Ge concentration that can be used as a platform for device fabrication.
- FIG. 3 A shows a generic structure where the cap layer 304 Ge concentration can vary from 0 ⁇ x ⁇ l.
- FIG. 3B shows a structure where the cap layer 306 is Si 07 Ge 03 .
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Crystallography & Structural Chemistry (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00974128A EP1214735A1 (fr) | 1999-09-20 | 2000-09-19 | Procede de production de couches de silicium-germanium decontractees |
JP2001525758A JP2003517726A (ja) | 1999-09-20 | 2000-09-19 | 緩和シリコンゲルマニウム層の作製方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15485199P | 1999-09-20 | 1999-09-20 | |
US60/154,851 | 1999-09-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001022482A1 true WO2001022482A1 (fr) | 2001-03-29 |
WO2001022482A9 WO2001022482A9 (fr) | 2002-08-08 |
Family
ID=22553074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/040938 WO2001022482A1 (fr) | 1999-09-20 | 2000-09-19 | Procede de production de couches de silicium-germanium decontractees |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1214735A1 (fr) |
JP (1) | JP2003517726A (fr) |
WO (1) | WO2001022482A1 (fr) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003069657A1 (fr) * | 2002-02-15 | 2003-08-21 | Centre National De La Recherche Scientifique | Procede de formation de couche de carbure de silicium ou de nitrure d'element iii sur un substrat adapte |
WO2003079415A2 (fr) * | 2002-03-14 | 2003-09-25 | Amberwave Systems Corporation | Procedes de fabrication de couches contraintes sur des substrats semiconducteurs |
WO2004019391A2 (fr) | 2002-08-23 | 2004-03-04 | Amberwave Systems Corporation | Heterostructures semi-conductrices possedant des empilements de dislocations reduits et procedes associes |
WO2004086473A1 (fr) | 2003-03-19 | 2004-10-07 | Amberwave Systems Corporation | Procede de production de couches de silicium-germanium relaxees de haute qualite |
US6946371B2 (en) | 2002-06-10 | 2005-09-20 | Amberwave Systems Corporation | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
US7071014B2 (en) | 2002-10-30 | 2006-07-04 | Amberwave Systems Corporation | Methods for preserving strained semiconductor substrate layers during CMOS processing |
EP1681711A1 (fr) * | 2005-01-05 | 2006-07-19 | Siltronic AG | Plaquette de semi-conducteur avec une couche de silicium-germanium et procédé pour sa fabrication |
US7214598B2 (en) | 2002-05-31 | 2007-05-08 | Advancesis Limited | Formation of lattice-tuning semiconductor substrates |
US7288430B2 (en) | 2000-11-27 | 2007-10-30 | S.O.I.Tec Silicon On Insulator Technolgoies | Method of fabricating heteroepitaxial microstructures |
US7594967B2 (en) * | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
US7709828B2 (en) | 2001-09-24 | 2010-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | RF circuits including transistors having strained material layers |
EP4220686A1 (fr) * | 2022-01-31 | 2023-08-02 | Siltronic AG | Procédé de dépôt d'une couche tampon à gradient de contrainte relaxé en silicium-germanium sur une surface d'un substrat |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4894390B2 (ja) * | 2006-07-25 | 2012-03-14 | 信越半導体株式会社 | 半導体基板の製造方法 |
EP2104135B1 (fr) * | 2008-03-20 | 2013-06-12 | Siltronic AG | Plaquette semiconductrice dotée d'une couche hétéroépitaxiale et procédé pour la fabrication de la plaquette |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3935040A (en) * | 1971-10-20 | 1976-01-27 | Harris Corporation | Process for forming monolithic semiconductor display |
EP0514018A2 (fr) * | 1991-04-24 | 1992-11-19 | AT&T Corp. | Procédé de fabrication d'une hétéro-structure semi-conductrice à faible taux de défauts et composants obtenus par ledit procédé |
-
2000
- 2000-09-19 EP EP00974128A patent/EP1214735A1/fr not_active Withdrawn
- 2000-09-19 JP JP2001525758A patent/JP2003517726A/ja active Pending
- 2000-09-19 WO PCT/US2000/040938 patent/WO2001022482A1/fr not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3935040A (en) * | 1971-10-20 | 1976-01-27 | Harris Corporation | Process for forming monolithic semiconductor display |
EP0514018A2 (fr) * | 1991-04-24 | 1992-11-19 | AT&T Corp. | Procédé de fabrication d'une hétéro-structure semi-conductrice à faible taux de défauts et composants obtenus par ledit procédé |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7955435B2 (en) | 1999-09-20 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of producing high quality relaxed silicon germanium layers |
US7041170B2 (en) | 1999-09-20 | 2006-05-09 | Amberwave Systems Corporation | Method of producing high quality relaxed silicon germanium layers |
US7674335B2 (en) | 1999-09-20 | 2010-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of producing high quality relaxed silicon germanium layers |
US7646038B2 (en) | 2000-11-27 | 2010-01-12 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating heteroepitaxial microstructures |
US7288430B2 (en) | 2000-11-27 | 2007-10-30 | S.O.I.Tec Silicon On Insulator Technolgoies | Method of fabricating heteroepitaxial microstructures |
US7906776B2 (en) | 2001-09-24 | 2011-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | RF circuits including transistors having strained material layers |
US7709828B2 (en) | 2001-09-24 | 2010-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | RF circuits including transistors having strained material layers |
FR2836159A1 (fr) * | 2002-02-15 | 2003-08-22 | Centre Nat Rech Scient | Procede de formation de couche de carbure de silicium ou de nitrure d'element iii sur un substrat adapte |
WO2003069657A1 (fr) * | 2002-02-15 | 2003-08-21 | Centre National De La Recherche Scientifique | Procede de formation de couche de carbure de silicium ou de nitrure d'element iii sur un substrat adapte |
WO2003079415A2 (fr) * | 2002-03-14 | 2003-09-25 | Amberwave Systems Corporation | Procedes de fabrication de couches contraintes sur des substrats semiconducteurs |
WO2003079415A3 (fr) * | 2002-03-14 | 2004-01-15 | Amberwave Systems Corp | Procedes de fabrication de couches contraintes sur des substrats semiconducteurs |
US7214598B2 (en) | 2002-05-31 | 2007-05-08 | Advancesis Limited | Formation of lattice-tuning semiconductor substrates |
US6946371B2 (en) | 2002-06-10 | 2005-09-20 | Amberwave Systems Corporation | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
EP2267762A2 (fr) | 2002-08-23 | 2010-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hétérostructures semi-conductrices dotées d'une accumulation de dislocation réduite et procédés connexes |
WO2004019391A2 (fr) | 2002-08-23 | 2004-03-04 | Amberwave Systems Corporation | Heterostructures semi-conductrices possedant des empilements de dislocations reduits et procedes associes |
US7594967B2 (en) * | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
US7202121B2 (en) | 2002-10-30 | 2007-04-10 | Amberwave Systems Corporation | Methods for preserving strained semiconductor substrate layers during CMOS processing |
US7416909B2 (en) | 2002-10-30 | 2008-08-26 | Amberwave Systems Corporation | Methods for preserving strained semiconductor substrate layers during CMOS processing |
US7541208B2 (en) | 2002-10-30 | 2009-06-02 | Amberwave Systems Corporation | Methods for preserving strained semiconductor substrate layers during CMOS processing |
US7208332B2 (en) | 2002-10-30 | 2007-04-24 | Amberwave Systems Corporation | Methods for preserving strained semiconductor substrate layers during CMOS processing |
US7071014B2 (en) | 2002-10-30 | 2006-07-04 | Amberwave Systems Corporation | Methods for preserving strained semiconductor substrate layers during CMOS processing |
WO2004086473A1 (fr) | 2003-03-19 | 2004-10-07 | Amberwave Systems Corporation | Procede de production de couches de silicium-germanium relaxees de haute qualite |
JP2006523380A (ja) * | 2003-03-19 | 2006-10-12 | アンバーウェーブ システムズ コーポレイション | 高品質の緩和シリコンゲルマニウム層の製造方法 |
JP2011223020A (ja) * | 2003-03-19 | 2011-11-04 | Taiwan Semiconductor Manufactuaring Co Ltd | 高品質の緩和シリコンゲルマニウム層の製造方法 |
EP1681711A1 (fr) * | 2005-01-05 | 2006-07-19 | Siltronic AG | Plaquette de semi-conducteur avec une couche de silicium-germanium et procédé pour sa fabrication |
EP4220686A1 (fr) * | 2022-01-31 | 2023-08-02 | Siltronic AG | Procédé de dépôt d'une couche tampon à gradient de contrainte relaxé en silicium-germanium sur une surface d'un substrat |
WO2023143804A1 (fr) * | 2022-01-31 | 2023-08-03 | Siltronic Ag | Procédé de dépôt d'une couche tampon à gradient et à relaxation de contrainte de silicium-germanium sur une surface d'un substrat |
Also Published As
Publication number | Publication date |
---|---|
WO2001022482A9 (fr) | 2002-08-08 |
EP1214735A1 (fr) | 2002-06-19 |
JP2003517726A (ja) | 2003-05-27 |
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