WO2001020858A1 - Dynamic circuit emulation using atm switches - Google Patents

Dynamic circuit emulation using atm switches Download PDF

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Publication number
WO2001020858A1
WO2001020858A1 PCT/SE2000/001766 SE0001766W WO0120858A1 WO 2001020858 A1 WO2001020858 A1 WO 2001020858A1 SE 0001766 W SE0001766 W SE 0001766W WO 0120858 A1 WO0120858 A1 WO 0120858A1
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WO
WIPO (PCT)
Prior art keywords
atm
frame
mapping
port
receiving port
Prior art date
Application number
PCT/SE2000/001766
Other languages
French (fr)
Inventor
Håkan FLORIN
Erik Friman
Lars-Göran Petersen
Original Assignee
Telefonaktiebolaget Lm Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US39707299A priority Critical
Priority to US09/397,072 priority
Application filed by Telefonaktiebolaget Lm Ericsson (Publ) filed Critical Telefonaktiebolaget Lm Ericsson (Publ)
Publication of WO2001020858A1 publication Critical patent/WO2001020858A1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3081ATM peripheral units, e.g. policing, insertion or extraction
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478Provisions for broadband connections
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5638Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H04L2012/5659Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] usint the AALX
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5638Services, e.g. multimedia, GOS, QOS
    • H04L2012/5671Support of voice

Abstract

The switch for a telecommunications exchange in accordance with an embodiment of the invention adapts a time slot in an incoming TDM-frame to an ATM frame in accordance with a predetermined ATM-VCC, and further dynamically changes a number of ATM cells in the ATM frame for the predetermined ATM-VCC in accordance with a changing number of connections carried through an ATM switch fabric (40) of the exchange. The exchange comprises the ATM switch fabric; a sending port (100); and a receiving port (200). An inband synchronisation signal is carried in an ATM frame routed through the ATM switch fabric from the sending port to the receiving port for coordinating a changing frame structure between the sending port and the receiving port in accordance with the changing number of connections. According to one example implementation, the number of ATM cells in the ATM frame for the predetermined ATM-VCC varies between one and sixty four, and one ATM cell in the ATM frame for the predetermined ATM-VCC convey eleven time slots.

Description

DYNAMIC CIRCUIT EMULATION USING ATM

SWITCHES

BACKGROUND

1. FIELD OF THE INVENTION The present invention pertains to telecommunications, and particularly to switching apparatus in telephone exchanges.

2. RELATED ART AND OTHER CONSIDERATIONS

Initially, telephone networks were primarily circuit switched, with connections between users being maintained throughout the duration of a telephone call. But nowadays there is much impetus in telephony for cost efficient packet networks. In fact, more and more services are now being implemented, and in the future will be implemented, with packet switching. Yet the circuit switched networks remain, in many instances performing a role as an access network towards the packet switched networks (Internet networks mainly). To cater to this role, and for other reasons, the circuit switched network is likely to undergo some changes. Among these changes are less layers, a reduced number of exchanges, and larger exchanges with more ports.

Telecommunications networks typically include exchanges. In general, a calling party is connected to an originating exchange, which may be connected via one or more transit exchanges to a destination exchange which serves the called party. Exchanges of a telecommunications network typically include one or more switches for the routing of connections between subscribers. An exchange usually includes a switch fabric (or core), as well as a first set of ports and a second set of ports. A port of the first set receives telephony data from an upstream exchange and prepares the telephony data for transmission through the switch fabric to an appropriate one of the second set of ports. A port of the second set prepares the telephony data obtained from the switch fabric for further transmission, e.g., to yet another [downstream] exchange.

One prior art circuit switch including, e.g., the AXE-10 group switch, is depicted in Fig. 8. Fig. 8 shows that up to 16 devices 820-1, ... 820-16 can be housed in a generic device magazine 822. Each device 820 is attached to a digital link (DL) multiplexer, i.e., DL-MUX 824, by means of DL2 interface 826. Each DL2 interface 826 comprises 31 user timeslots. A timeslot in this context is equal to 64 kbps (8 bits of data repeated every 125 :s). The DL-MUX 824 multiplexes the timeslots from each DL2 interface 826 into a DL3 interface 828. The DL3 interface 828 houses 496 user timeslots. A large number of generic device magazines 822-1, ... 822-n can be attached to group switch 830, the constraining factor on such number of device magazines 822 being only the capacity of group switch 830. The group switch 30 of Fig. 1 can be a time-space-time (TST), time-space (TS) or any other circuit-based architecture, all well known to people skilled in the art.

As indicated above, the demand for an increased number of ports for an telecommunications exchange will result from accommodating packet services, and particularly Internet utilization by, e.g., residential subscribers. Residential Internet users have totally different traffic behavior compared to users for other telephony services. For example, typical telephony traffic has, on average, a call duration of about 2 minutes. On the other hand, it is common for an Internet user using dial-up access to have a usage duration of 20 minutes or more. Such increased call duration has, of course, significant impact on the load of a local exchange. The ever increasing demand for Internet access, with its increased call duration time, requires more bandwidth and more ports in the switches of an exchange. It has been estimated that, if the subsisting plain old telephone service (POTS) is to be preserved alongside such data packet utilization, a telecommunications exchange may require as many as twice as many ports as previously.

Therefore, there is a palpable need to upgrade the existing installed telephone exchanges in order to support data communications with "almost permanent" Internet access, and to do so and without affecting the existing POTS/ISDN (Integrated Services Digital network) services. One option is replacement of the entire circuit swiching components of the exchange, which is an expensive option necessitating, e.g., replacement of all software of the exchange. Another potential solution is replacement of only the switching fabric (without total replacement of the local exchange). Yet in the fabric-only replacement solution, the new switching fabric should be able to support both old PSTN/ISDN and packet data services (e.g., Internet traffic flows).

In the above regard, it has been proposed to replace the entire switching fabric so that the switching fabric is no longer a circuit switching fabric, but instead a cell switching fabric (MPSR) which is able to perform both cell switching and an emulation of circuit switching. See, Deloddere, "Evolution of a Narrowband Exchange towards Broadband", International Switching Symposium, Vol. 1, April 1995. Unfortunately, such proposal has severe disadvantages. For example, the emulation of circuit switching requires a very large overhead. In this regard, for each 64 kbps sample, 544 kbps is required internally, corresponding to 750 % overhead. The largest exchanges today may require a switching fabric size of 128 k ports. The proposed switching mechanism can be used for emulation of such a large switching fabric, but with a resulting switching fabric for ATM with about 70 Gbps. Such size is considered huge, since currently most ATM switching fabrics have a size of about 20 Gbps. The sheer size required of such proposed emulating switching fabric may defeat its effective implementation.

ATM, referenced e.g., in the proposal cited above, is a packet-oriented transfer mode which uses asynchronous time division multiplexing techniques. Packets are called cells and traditionally have a fixed size. A traditional ATM cell comprises 53 octets, five of which form a header and forty eight of which constitute a "payload" or information portion of the cell. The header of the ATM cell includes two quantities which are used to identify a connection in an ATM network over which the cell is to travel, particularly the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier). In general, the virtual is a principal path defined between two switching nodes of the network; the virtual channel is one specific connection on the respective principal path.

In general, various ATM Adaptation Layers have been standardized and are particularly useful for carrying certain types of traffic. For example, an ATM Adaptation Layer known as AAL1 (ITU standardized) has been targeted to emulate circuit switched data (e.g. voice) at the network level. But the use of AAL1 to emulate a single circuit switch in a TDM network has a problem in obtaining high bandwidth utilization combined with low delay. The two well-known techniques (single user and composite fill) for coping with this problem, along with the advantages and drawbacks accompanying each, are described below.

The first technique occurs when using AAL1 for circuit emulation for single user. If the ATM connection is used for a single 64 kbps channel, a one way packetizing delay will be about 6 ms. (47x125 :s). The delay will be even worse if subrates are used. For 16 kbps, the one way delay will be about 24 ms. and the one way delay requirements for a circuit switch is about 0.5 ms per 64 kbps connection. A known solution to this delay problem is to partly fill the ATM cells. But the partial cell filling solution will result in a large bandwidth waste (to meet the 0.5 ms delay requires that only 4 time slots are put in each ATM-cell). The bandwidth waste in this example is using 784 kbps to carry 64 kbps, i.e., 4 useful octets out of 53 (the ATM-cell size) sent every 500 :s.

The second technique, which addresses the foregoing problem of bandwidth waste, is to provide circuit emulation for composite users, i.e., composite filling. The second technique is used for structured circuit emulation of e.g. El or Tl where each timeslot has its given position. Each time slot can in its turn constitute a 64 kbps connection. The ATM-cell is internally structured in such a way that different 64 kbps circuit connections are multiplexed in the same ATM-connection. Each connection has its given position. This solution combines low delay with high bandwidth utilization. The solution is good for cases where the number of active connections between two endpoints are constant or bandwidth is available regardless of if is used or not. A typical example is trunking where a leased El between two nodes can carry thirty 64 kbps connections irrespective of whether they are used or not.

However, in a switch (where the flow of connections are diverting all the time) the composite filling solution can get fragmented. An allocated time slot in the ATM- cell payload must remain for the duration of the call. Consider, for example, the situation depicted in Fig. 9, wherein a switching system 840 with four ports 842A, 842B, 842C, and 842D are all interconnected by means of an ATM switch 844. Each port 842 towards the switch can handle a load corresponding to 496 time slots plus the overhead for ATM-cell header.

The situation of Fig. 9 depicts a first prior art composite filling emulation case having minor bandwidth waste. The case of Fig. 9 shows how 496 time slots (i.e. 64 kbps connections) are interconnected from port 842 A to port 842B. Between port 842C and port 842D another set of 496 time slots are interconnected. There is no traffic from port 842A to port 842C, or from port 842B to port 842D. A frame of 11 ATM cells is established. The first 10 ATM-cells of the frame are all filled completely and the 11th cell of the frame is half filled. The frame is repeated every 125 :s. The first ATM cell holds data for connections 1 - 47; the next ATM cell holds data for connections 48 - 94; and so forth. Each allocated time slot is mapped to a connection defined by its number in the AAL1 frame.

The situation of Fig. 10 depicts a first prior art composite filling emulation case having minor bandwidth waste. If all 64 kbps connections, except the first one in every ATM-cell, is cleared (connection 1, 48, 95...) up to the last ATM cell in the frame, it is evident that there will be many empty holes in the AAL1 frame. However, the bandwidth will not be reduced despite the fact that the used bandwidth to the remaining connections has become just a fraction. If port 842C now wants to establish connections to port 842B, there is no bandwidth available due to the holes in the ATM- cell stream from port 842A to port 842B. Any new connections between port 842 C to port 842B cannot be served. Furthermore port 842A cannot set up any connections to port 842D for the same reason.

Thus, circuit emulation of a single channel into an ATM-cell gives to much delay if filled completely or too much bandwidth waste if filled partially. On the other hand, circuit emulation with composite fill with channels from many users may result in fragmentation.

In addition to AAL1, the newly developed AAL2 can also be used to emulate circuit switched data. AAL2 provides means to multiplex up to 248 connections into one ATM connection. AAL2 is targeted to a single user per connection, but could also carry composite users though there is no defined standard for such as occurs in AAL1. AAL2 provides an independent packet of variable length with its own connection identifier. The packet header is three octets. In the AAL1 solution with a single user it is stated that more than 3 time slots (64 kbps) cannot be put in the ATM cell if the one way delay properties of 0.5 us maximum shall be maintained. The same limitation applies to AAL2, which gives a bandwidth waste of about 50% (The AAL2 packet header is 3 octets and the payload 3 octets [Note: the ATM overhead is not included in these percentages]). For subrates (i.e. 8 and 16 kbps), the overhead will be worse with the same delay constraints.

What is needed, therefore, and an object of the present invention, is a way to upgrade existing circuit switching nodes of a telecommunications network.

BRIEF SUMMARY OF THE INVENTION

To upgrade an existing circuit switch of a telecommunications exchange, the space switch in a circuit switch of TST structure is replaced with an ATM switch and a dynamically structured emulation method is employed to realize low delay and high utilization. The switch employs an ATM switch fabric or core connected between sending ports and receiving ports. In the ATM switch, at least one ATM-VCC is required for every sending port/receiving port combination, and ATM-VCC ATM cell- structured frames are transmitted every 125 μs. The number of ATM-cells in the frame for the ATM-VCC vary (e.g., from 1 to 64 ATM cells) depending on the current load situation, i.e., the number of narrowband connections that are being routed between the two ports. The invention allows narrowband connections through the switch to be added to or removed dynamically from the ATM-cell frame structure.

The switch for a telecommunications exchange in accordance with an embodiment of the invention adapts a time slot in an incoming TDM-frame to an ATM frame in accordance with a predetermined ATM-VCC, and further dynamically changes a number of ATM cells in the ATM frame for the predetermined ATM-VCC in accordance with a changing number of connections carried through an ATM switch fabric of the exchange. The exchange comprises the ATM switch fabric; a sending port; and a receiving port. An inband synchronization signal is carried in an ATM frame routed through the ATM switch fabric from the sending port to the receiving port for coordinating a changing frame structure between the sending port and the receiving port in accordance with the changing number of connections. According to one example implementation, the number of ATM cells in the ATM frame for the predetermined ATM-VCC varies between one and sixty four, and one ATM cell in the ATM frame for the predetermined ATM-VCC convey eleven time slots.

Both the sending port and the receiving port comprise a pair of mapping tables. In each port, at any given time one of the mapping tables serves as an active mapping table and the other of the mapping tables serves as an inactive mapping table. In the sending port, the active mapping table is used for preparing an ATM frame for an existing traffic situation on the predetermined ATM-VCC, while in the receiving port the active mapping table is used for decoding the ATM frame for an existing traffic situation on the predetermined ATM-VCC. In the sending port, the inactive mapping table is used for preparing an ATM frame for a changed traffic situation on the predetermined ATM-VCC, while in the receiving port the inactive mapping table is used for decoding the ATM frame for a changed traffic situation on the predetermined ATM-VCC. In response to a signal from a control unit indicating a change in the number of connections carried through the switch fabric between the sending port and the receiving port (e.g., a change in the frame structure), the roles of the sending port first mapping table and the sending port second mapping table are switched or reversed. Upon the reversal at the sending port, the sending port issues the inband synchronization signal to the receiving port. In response to the inband synchronization signal from the sending port, the roles of the receiving port first mapping table and the receiving port second mapping table are switched.

In one mode of the invention, the inband signal from the sending port includes an octet included in the ATM frame, the octet having a table bit field which is employed for the coordinating of the changing frame structure (e.g., for indicating that the receiving port first mapping table and the receiving port second mapping table are to switch roles).

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments as illustrated in the accompanying drawings in which reference characters refer to the same parts throughout the various views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

Fig. 1 is a schematic view of portions of a switch node according to an embodiment of the invention.

Fig. 2 is a schematic view of logic of a sending port of the switching node of Fig. 1.

Fig. 3 is a schematic view of logic of a receiving port of the switching node of Fig. 1.

Fig. 4 is a diagrammatic view of a signaling sequence for the switching node of

Fig. 1.

Fig. 5 is a diagrammatic view of an ATM cell frame utilized by the switching node of Fig. 1.

Fig. 6 is a diagrammatic view of DCE control octet included in the ATM cell frame of Fig. 5.

Fig. 7 is a timing diagram showing sending and receiving of frames in the switching node of Fig. 1 according to a mode of the invention.

Fig..8 is a schematic view of a prior art circuit switch.

Fig. 9 is a schematic view of a prior art circuit emulation scenario having minor bandwidth waste.

Fig. 10 is a schematic view of a prior art circuit emulation scenario having major bandwidth waste. DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

Fig. 1 shows a switching node 10 according to an embodiment of the present invention. The switching node 10 comprises a switch control unit 12, along with a plurality of ports 42 which are connected by an ATM switch 44. Although only four ports, particularly ports 42A - 42D, are shown in Fig. 1, it should be understood that such illustration is representative only, and that likely a much greater number of ports are utilized in switching node 10. Each port 42 is connected to the narrowband network by a corresponding TDM transmission link 52A -52D, respectively (such TDM transmission links being well known in the art). Fig. 1 also shows each of the ports 42A - 42D being connected by an ATM transmission link 54A - 54D, respectively, to ATM switch 44. The switch control unit 12 is connected by control lines 56A - 56D, respectively, to each of the ports 42.

Fig. 5 provides an illustration of an ATM frame 60 which is sent from a sending one of the ports 42 and through ATM switch 44 to a receiving one of the ports 42. In Fig. 1, it so happens that the sending port is port 42A and the receiving port is port 42B. Thus, the port combination is port 42 A/port 42B, for which at least one ATM-VCC (Virtual Channel Connection) is required. In accordance with the present invention, the number of ATM cells 62 carried in the frame for the ATM-VCC for the sending port/receiving port combination vary depending on the current load situation, i.e., the number of narrowband connections that are carried between the sending port and the receiving port. That is, the number of ATM cells in a frame for narrowband connections routed between any two given ports of the switch is adjusted to the actual need of such active narrowband connections. In the preferred embodiment, the number of ATM cells in a frame for the ATM-VCC for the sending port/receiving port combination can vary from one to 64 ATM cells, Fig. 5 showing an embodiment having 11 ATM cells 62-1 - 62-11.

Since the number of ATM cells carried in the frame for the ATM-VCC for the sending port/receiving port combination vary depending on the current load situation, the present invention must dynamically reconfigure the frame in accordance with the addition or removal of narrowband connections. Therefore, as explained in more detail below, the ports 42 of the present invention must each have buffers with two sides, with the first and second sides of the buffers alternating the roles of (1) serving as a writing buffer for assembly of a frame to be transmitted, (2) serving as a reading buffer for readout of an assembled frame. Likewise, each port 42 must have two mapping tables for correlating each narrowband connection with an ATM cell/time slot in the frame, and particularly an active mapping table and an inactive mapping table. The active mapping table is utilized, e.g., for preparing the frame in the writing buffer for the existing narrowband connections. When a change is to be made regarding the number of narrowband connections (e.g., addition or removal), the inactive mapping table is utilized to prepare a frame in anticipation of the change. When the change is actually made (having been prompted by signaling), the active mapping table and the inactive mapping table switch roles. Signaling is provided for indicating to the ports 42 when a frame change is to occur, so that the ports 42 can, in coordinated manner, reverse the roles of the first and second mapping tables to reflect a change in the narrowband connections for the ATM-VCC for the sending port/receiving port combination.

Each of the ports 42 of the switching node 10 of Fig. 1 have both a sending side and a receiving side. As used herein, "sending" and "receiving" are from the perspective of the ATM switch 44 of switching node 10. That is, the sending side of a port 42 receives the incoming TDM-based frames on the TDM transmission link 52 connected to the port, and sends frames of ATM cells to the ATM switch 44. The receiving side of a port 42 receives the frames of ATM cells forwarded through ATM switch 44, and is connected to an outgoing TDM transmission link 52. Fig. 2 shows logic for a sending side of a port 42 of switching node 10, and for convenience is referenced herein as a "sending port". Similarly, Fig. 3 shows logic for a receiving side of a port 42 of switching node 10, and is referenced herein as a "sending port". The logic of an example sending port 100 is shown in Fig. 2 as receiving TDM frames on TDM transmission link 52 and applying times slots of the frames both to time slot counter unit 102 and to ATM-VCC selector 104. The ATM-VCC selector 104 serves to route a time slot of an incoming TDM frame to one of plural ATM-VCC boards 106-1 through 106-n. Time slot counter unit 102 applies a time slot on an incoming TDM frame to a mapping table index selector 108. The mapping table index selector 108 routes the time slot for use as an index for one of a first mapping table 110 (mapping table 0) and a second mapping table 112 (mapping table 1). Each mapping table 110, 112 is configured by a sending control unit 114 of sending port 100. The index applied by mapping table index selector 108 is used to obtain an entry from whichever of the first mapping table 110 and second mapping table 112 is currently serving as the active mapping table. A mapping table output selector 116 selects the active mapping table (either first mapping table 110 or second mapping table 112), so that the outputted entry can be used, e.g., by sending control unit 114, to control other elements of sending port 100 and thereby configure the outgoing active frame and (when necessary) an inactive frame. In this regard, the ATM-VCC selector 104 is controlled so that an incoming time slot of the TDM frame is applied to one of the ATM-VCC boards 106-1 through 106-n. Each of the ATM-VCC boards 106 has a frame buffer 120 comprising a first side frame buffer 122 and a second side frame buffer 124. Whichever of the first side frame buffer 122 and the second side frame buffer 124 is the active writing buffer is communicated by sending control unit 114 to frame buffer feed selector 126. When it comes time to read out the frame from the active frame buffer, a frame buffer readout selector 128, under control of output control unit 130, chooses the correct one of the first side frame buffer 122 and the second side frame buffer 124 and applies the frame to FIFO unit 132. The FIFO unit 132 comprises a multiplexer 134 and FIFO registers 136-1 through 136-n fed by respective ATM-VCC boards 106-1 through 106-n.

The logic of an example receiving port 200 is shown in Fig. 3 is essentially the inverse of the sending port 100 of Fig. 2. In Fig. 3 the receiving port 200 is shown as receiving frames of ATM cells on ATM transmission link 54 from ATM switch 44. In similar manner as sending port 100, the receiving port 200 has a time slot counter unit 202; ATM-VCC selector 204; plural ATM-VCC boards 206-1 through 206-n; mapping table index selector 208; first mapping table 210; second mapping table 212; and receiving control unit 214. Each ATM-VCC boards 206 has a frame buffer 220 which includes a frame buffer first side 222; a frame buffer second side 224; a frame buffer feed selector 226; a frame buffer readout selector 228; and an input control unit 230. The receiving port 200 further has a FIFO input unit 232 which includes FIFO register 236 and ATM-VCC selector 238. The ATM-VCC selector 204 has inputs connected to outputs of the frame buffer readout selectors 228 of the plural ATM-VCC boards 206-1 through 206-n. The output of the ATM-VCC selector 204 is connected to a TDM frame generator 240.

The changes in connections (e.g., the set up or tearing down of one or more connection) are communicated to switch control unit 12 on IAM (Initial Address Message) signaling line 13 (see Fig. 1). As explained below, in accordance with the dynamic circuit emulation of the present invention, whenever a change occurs for the frame constituency (e.g., the addition or removal of a connection), the changes are first signaled by switch control unit 12 (over respective signaling lines 56) to the sending control unit 114 of the sending port 100 and to receiving control unit 214 of receiving port 200, so that the change can be implemented in the passive mapping tables of both sending port 100 and receiving port 200. Thereafter, an inband synchronization signal is provided (e.g., in the ATM cells transmitted through ATM switch 44) from the sending port 100 to the receiving port 200, notifying the receiving port 200 exactly when the change is to occur. Upon synchronization, the mapping tables of both sending port 100 and receiving port 200 change roles, so that in both sending port 100 and receiving port 200 what formerly was the inactive mapping table (used previously to handle the anticipated change) becomes the active mapping table.

What is described below is a scenario wherein port 42A of switching node 10 of Fig. 1 serves as the sending port 100 and port 42B serves as the receiving port 200. With reference to the example frame architecture of ATM frame 60 shown in Fig. 5, only one ATM cell 62-1 (the first ATM cell of a frame) is required to convey 11 time slots for the ATM-VCC between port 42A and port 42B (instead of the eleven ATM cells required in the situation of Fig. 10). The empty bandwidth space in ATM frame 60 is filled with idle cells (the usage of idle cells being well known to those skilled in the art). In operation, switch control unit 12 of the switching node 10 depicted in Fig. 1 knows when there is a need for controlling the setup/release of a connection. The switch control is a prior art function that is needed to make the switch to work in an e.g. N-ISUP (Narrowband ISDN User Part) network. The switch control unit 12 terminates the N-ISUP signaling, extracts the relevant information and transforms it into a node internal format that is used to operate the ports 42 of switching node 10. An incoming connection setup or connection release results in control signals issued from switch control unit 12 to the ports 42 involved. How switch control unit 12 processes and distributes the associated control signals are understood by those skilled in the art. An example control-signaling scheme, according to an embodiment of the invention, is showed in more detail with reference to Fig. 4 below. In a manner understood by those familiar with ATM art, the invention uses pre-setup ATM connections between the ports 42 in switching node 10.

Fig. 4 illustrates an example signaling procedure for setup of a new narrowband call through switching node 10 of Fig. 1. For simplicity reasons, the signaling scheme of Fig. 4 is limited to only one setup or tear down operation in the sequence, and only one sending and receiving port are shown.

Signal 4-1, indicates a prior art simplified call setup, based on the well-known N- ISUP. Basically, an IAM signal gives all information needed to set up a narrowband connection through switching node 10. The switch control unit 12 processes the incoming call setup and determines the sending and receiving ports for the call (e.g., the sending port being sending port 100 and the receiving port being receiving port 200 in the illustrated example of Fig. 1).

Signal 4-2, issued from switch control unit 12 to receiving port 200, prepares the receiving port 200 for the changes in ATM frame 60. The switch control unit 12 signals the exact changes that are going to take place, e.g., where to put the new time-slot in the ATM-cell frame 60. The person skilled in the art will appreciate how to set up an ATM connection between two ports, e.g., using the well-known N-ISUP (Narrowband ISDN User Part). Signal 4-3 is an acknowledgment from receiving port 200 to switch control unit 12 which advises that receiving port 200 has prepared for the expected changes in ATM frame 60. As part of the preparations for the expected changes, the receiving port 200 will update its inactive mapping table in accordance with the changes communicated in signal 4-2. The receiving port 200 is now in a state waiting for an inband synchronization signal. In this waiting state receiving port 200 will reject new signals of type 4-2. The port will remain in this waiting state until it is sent a signal of type 4-5 (and switch control unit 12 has issued signal 4-7).

Signal 4-4 is sent by switch control unit 12 to sending port 100, communicating to sending port 100 the same changes anticipated for ATM frame 60 as was previous sent (by Signal 4-2) to receiving port 200. The sending port 100 prepares its internal logic (e.g., its inactive mapping table, see Fig. 2) to reflect the changes communicated by switch control unit 12.

Immediately after sending port 100 has prepared its internal logic for the changes, sending port 100 sends Signal 4-5 to receiving port 200. Signal 4-5 is an inband signal, which means that the signal is communicated via the ATM cells in ATM frame 60 and transmitted through ATM switch 44. Signal 4-5, sent inband from sending port 100 to receiving port 200, has the function of synchronizing both sending port 100 and receiving port 200. In the example under consideration, Signal 4-5 reflects the fact that a new narrowband channel is added to the ATM-cell frame structure of Fig. 5.

Thus, the invention involves inband signaling between sending port 100 and receiving port 200. Inband signaling in this context means that additional information is added to the frame of ATM-cells between two ports (see Fig. 4). The inband signaling that is conveyed indicates changes in the frame structure, i.e. no changes or if a new narrowband channel is added or removed. The inband signaling is needed to synchronize the sending and receiving ports. Signal 4-6 is sent from receiving port 200 to switch control unit 12 to indicate to switch control unit 12 that the operation is completed between the two ports (i.e., sending port 100 and receiving port 200). In other words, Signal 4-6 communicates that receiving port 200 has detected the inband synchronization signal (Signal 4-5) and has acted accordingly. The switch control unit 12 now has the capability to start a new setup/tear down operation to receiving port 200 from any other port, i.e. to change the ATM-cell frame structure in another ATM-VCC towards the same port. The frame structure for other ATM-VCC going to other receiving ports can very well be changed simultaneously, provided that switch control unit 12 can handle signal scheme processes in parallel.

Signal 4-7, issued by switch control unit 12, confirms that the procedure for the ATM-VCC between the target ports (sending port 100 and receiving port 200 in the illustrated example) is completed. The switch control can now propagate the IAM to the next node in the network (e.g., over IAM signaling line 14 [see Fig. 1]), indicating that the connection is established in this node (the node having switching node 10) of the network.

The foregoing has described the signaling performed within switching node 10 when a connection is being set up. The reader will appreciate that essentially the same type of signaling sequence takes place when the connection is torn down.

As should be understood from the foregoing, the invention is not limited to performing only one change at a time. In other words, the frame structure can contain a multitude of changes. That is, when a switch is made to a new frame format upon communication of Signal 4-5, the frames thereafter transmitted may include plural connection changes relative to the frames transmitted prior to the switch over.

As mentioned briefly above in connection with Signal 4-6, only one of the ATM-

VCC to a specific receiving port can be changed during the signal procedure. To change connections in another ATM-VCC towards the same port it is required that switch control unit 12 wait until the Signal 4-6 is received. In the example embodiment discussed herein, the DL-MUX 824 of Fig. 8 is replaced with a port 42 which adapts the aggregated incoming DL2 lines (hereafter called a TDM-frame) to ATM-VCC, one for each port combination. Of course, the invention is not limited to a TDM-frame comprising 16 DL2. A TDM frame could very well comprise a whole STM-1 of 2000 useful narrowband channels. An important issue is synchronization of the changes in connections, in terms of added or removed narrowband channels in the ATM-cell frame structure. This change or switch over must be done without disturbing the not affected other narrowband connections.

In one mode, the invention utilizes a set of two mapping tables for each ATM- VCC, i.e. the ATM-cell frame structure. In this regard, as illustrated in Fig. 2 the sending port 100 has both first mapping table 110 and second mapping table 112, and similarly the receiving port 200 has first mapping table 210 and second mapping table 212. At any given time, one of the tables for each ATM-VCC is active and identical to the actual payload in the transferred ATM-cell frame structure. The other (inactive) table of the ATM-VCC is used to build up the new ATM-cell frame structure. When the changes in the inactive table are made, the tables alternate their roles. The inband signal (Signal 4-5 [see Fig. 4]) advises the receiving port 200 as to which table (first mapping table 210 or second mapping table 212) to use as the active table.

Between all ports which switch narrowband connections according to the invention, ATM-VCCs are established. At least one ATM-VCC per combination is required. The bandwidth requirement for each ATM-VCC is dynamic according to the actual number of established narrowband connections. The ATM-cell frame 60 (see Fig. 5) is used to carry the narrowband channels. The ATM-cell frame 60 is repeated every 125 :s in the ATM-VCC. If there are no narrowband channels connections established between the ports (ATM-VCC), there is no need to send the ATM-cell frame 60 at all. The ATM-cell frame 60 is a structure of up to 64 ATM-cells logically connected together. Each ATM-cell 62 in the frame can hold 47 narrowband (i.e. 64 kbps) connections. The number of ATM-cells in the frame corresponds to the number of established narrowband connections for the ATM-VCC for the sending port/receiving port combination. A new ATM-cell must be added to the frame for every 47 -channel boundary. According to the invention, the ATM-cell frame 60 has the property of dynamically changing the number of ATM-cells 62 the ATM-VCC for the sending port/receiving port combination in the frame according to current load situation of the ATM-VCC. This dynamic change is accomplished using an inband signaling protocol (for the Signal 4-5 [see Fig. 4]) together with dedicated sending and receiving port logic described in connection with Fig. 2 and Fig. 3, respectively.

Fig 6. shows an example format of the inband signaling employed for the synchronization Signal 4-5 discussed above (see Fig. 4). The inband signaling is supported by a Dynamic Circuit Emulation control octet DCE located first in every ATM-cell 62 in the frame 60. As indicated above, ATM frames 60 are carried in an ATM-VCC that is setup semi-permanently between two ports 42. The ATM frame 60 is sent every 125 us.

The DCE control octet of Fig. 6 is divided into three fields, in particular field 6- 1, field 6-2, and field 6-3. Field 6-1, also known as the frame bit or table bit, has a value of either 0 or 1. A 0 value for the table bit of field 6-1 indicates that first mapping table 110 is active in sending port 100 and that first mapping table 210 is active in receiving port 200. Conversely, a 1 value for the table bit of field 6-1 indicates that the second mapping table 112 is active in sending port 100, and that second mapping table 212 is active in receiving port 200.

Field 6-2 of the DCE control octet of Fig. 6 is a 6 bit binary counter (counting values from 0 to 63 inclusive). The purpose of the counter of field 6-2 is to logically connect ATM frame 60 together. In the first ATM cell 62-1 in the frame 60, the counter of field 6-2 is set to zero, in the next ATM cell 62-2 of the frame the counter of field 6-2 is set to one, and so forth. In the illustrated embodiment, the maximum allowed number of ATM cells in a frame is thus 64, equaling a maximum of 64x47=3008 narrowband channels per ATM-VCC. If more narrowband channels are required between two ports, a new ATM-VCC must be established allowing up to 3008 additional narrowband channels. Incidentally, 3008 narrowband channels (i.e. 64 kbps) is more than can be housed in a 155 Mbps TDM link that is state of the art today for such links. The counter of field 6-2 is used to detect the frame boundaries and ATM- cell loss. Since the frame is repeated, any specific precautions due to a lost ATM-cell is not needed. The old values from previous frames can remain in the table at the receiving side. (The values are updated every frame interval).

Field 6-3 of the DCE control octet of Fig. 6 is a parity bit, and protects the integrity of the DCE octet. The receiving port 200 can detect odd number of bit errors. Protection of a field or octet by means of parity is well known to people skilled in the art.

A mode of operation of sending port 100 of Fig. 2 is now described. The sending port 100 receives TDM (Time Division Multiplex) based frames repeated every 125 us. The TDM frame can have a PDH (Plesiochronous Digital Hierarchy) or SDH (Synchronous Digital Hierarchy) structure, or both types as well. Examples of frames are for PDH El and Tl (El being mostly used in Europe and Tl being used in the US). For SDH, the STM-1 (Synchronous Transfer Mode) is mostly used for narrowband connections. STM-1, in this context, is the same for both Europe and USA. The person skilled in the art understands how the TDM frame is synchronized to the 125 :s repetition rate.

The time slot counter unit 102 of sending port 100 starts in the beginning of every 125 μs interval. The time slot counter unit 102 increments by one for every time slot in the TDM frame. The time slot counter unit 102 addresses a mapping table (either first mapping table 110 or second mapping table 112) with one entry for each time slot. The data in the mapping table contains information on how to handle the incoming time slot in question. One of first mapping table 110 and second mapping table 112 is an active state, the other is in an inactive state.

By means of the entry obtained from the active mapping table, the sending control unit 114 is able to direct every time slot to its predefined ATM-VCC (e.g., to an appropriate one of the ATM-VCC boards 106) and knows where in its ATM-cell structure payload the time slot shall be put (e.g., the location in the writing frame buffer). The active mapping table holds the actual narrowband connection table to all receiving ports 200 from the sending port 100 involved. The inactive mapping table is used to prepare for changes in the narrowband connections from the sending port 100 in question. The sending control unit 114 prepares the inactive mapping table according to the information provided by Signal 4- 4. When the changes are made the active and inactive mapping tables swap roles, i.e., the active mapping table becomes the inactive mapping table and the inactive mapping table becomes the active mapping table. The swap must be synchronized with time slot counter unit 102, i.e. the swap must be made when time slot counter unit 102 turns around and starts again at zero. The swap of mapping tables in sending port 100 is also synchronized with output control unit 130 in the appropriate ATM-VCC board 106 so one 125 μs cycle later it will change between the two frame buffers 122 and 124. To wait 125 μs is necessary since that is the time it will take to fill the new frame buffer, associated to the new connection situation.

For each incoming time slot, the mapping table has an entry holding information utilized to send the incoming time slot. In this regard, the mapping table entry is used to direct the time slot to the pre-assigned ATM-VCC. The pre-assigned ATM-VCC is the VCC that carries the time slots from sending port 100 to receiving port 200. Direction of the incoming time slot to the proper pre-assigned ATM-VCC is performed by ATM- VCC selector 104 under control of sending control unit 114. The ATM-VCC selector 104 has an output which can be applied to any of the ATM-VCC boards 106, so that the incoming time slot can be routed to the pre-assigned ATM-VCC. In this regard, at least one VCC for every port combination must be pre-assigned. The VCI in the ATM-cell is used by the ATM switch 44 to switch the cell to its receiving port 200 . How to set up VCC and allocate VCI is well-known technique in the ATM community.

The mapping table entry also apprises the sending control unit 114 of the position in the writing side frame buffer (e.g., whichever of first side frame buffer 122 and second side frame buffer 124 is the writing buffer) . The incoming time slot is stored in the given position in the buffer at connection setup. The time slot order in the ATM-cell structure can be controlled completely by the mapping table.

Thus, by consultation with the active one of the mapping tables 110, 112, in sending port 100, any incoming time slot can be directed to its ATM-VCC and position in the ATM-cell structure in run time and repeated every 125 :s. In Fig. 2, frame buffer 120 has two sides 122, 124. At any given moment, one of these frame buffer sides 122, 124 is used as the writing side buffer and the other is the reading side buffer. The frame buffer readout selector 128 is used to select which of first side frame buffer 122 and second side frame buffer 124 is the reading side frame buffer. When a new frame structure is completed and synchronization has occurred, a shift or switch is made so that first side frame buffer 122 and second side frame buffer 124 change roles. The first side frame buffer 122 and second side frame buffer 124 operate independently of each other. Without such independence, some time slots could be delayed more than 125 μs while others are delayed just a couple of μs. To avoid this differing delay, the frame buffer must be doubled. During a 125 μs cycle, writing is done in one of the first side frame buffer 122 and second side frame buffer 124, while reading is done from the other. In the next cycle, the first side frame buffer 122 and second side frame buffer 124 swap roles.

The output control unit 130 of a ATM-VCC board 106 empties the active frame buffer in sequence start from address 0 to the end of last stored ATM-cell (e.g. up to 63 cells in the illustrated embodiment). The size of the ATM-cell frame (i.e. how many ATM-cells) must be stored in output control unit 130 by the sending control unit 114. The output control unit 130 generates the ATM-cell header and DCE octet in run time for every ATM-cell in the structure. The ATM-cell header is always the same while the DCE octet can change frame buffer indication (field 6-1) and the counter of field 6-2 must increment (see Fig. 6). The complete frame structure with ATM-cell headers and the DCE-octets is unloaded during the 125 μs interval.

The FIFO registers 136-1 through 136-n, one for every active ATM-VCC, accommodates ATM switch 44. By nature ATM switches generally require that an ATM-cell be delivered uninterrupted. When a complete ATM-cell is stored in a FIFO 136, the ATM switch 44 is notified. ATM switch 44 then unloads the cell and ships it to receiving port 200 according to the VCI in the ATM cell header. The FIFO registers 136-1 through 136-n are emptied in a round robin fashion in a contention situation. A mode of operation of receiving port 200 of Fig. 3 is now described. Operation of receiving port 200 is essentially the inverse of the operation of sending port 100. The incoming ATM-cells from ATM switch 44 are stored in FIFO register 236. When a whole ATM-cell is present at the output of FIFO register 236, it is extracted. Logic at the output of FIFO register 236 checks to what ATM-VCC it belongs (given by the VCI in the ATM-cell header). In accordance with the ATM-VCC of the cell, the cell is directed by ATM-VCC selector 238 to an appropriate one of the ATM-VCC boards 206-1 through 206-n.

The ATM cell payload (47 octets) is stored in the frame buffer unit 220 of the selected ATM-VCC board 206 in a position given by the counter value in the DCE octet, at the write side of the frame buffer. Each frame buffer unit 220 has two buffer sides, in particular buffer side 222 and a buffer side 224. The sides 222, 224 alternate roles as write buffer or read buffer every 125 μs interval. When a side 222 or 224 is the read side buffer, the ATM-cell frame structure payload, stored in the previous 125 μs interval, is unloaded therefrom time slot by time slot. This reading from the read side buffer is controlled by the active mapping table (i.e., whichever of first mapping table 210 and second mapping table 212 is the active mapping table). The active mapping table holds the information on how the time slots stored in frame buffer 220 from all ATM-VCCs shall be mapped into the TDM-frame. The active mapping table is addressed by time slot counter unit 202, which increments for every new time slot in the TDM-frame. The unloading depends on which standard type of TDM-frame the frame buffer unit 220 can hold, e.g. 32 time slots in an El and 2430 in an STM-1. After reaching the maximum numbers of time slots in the TDM-frame, the time slot counter unit 202 wraps around and start all over. The TDM-generator 240 is needed since some positions in the TDM frame contain other information (e.g. synchronization information) than through-connected time slots.

Thus, in receiving port 200 (like sending port 100) there is one active and one inactive mapping table. While the inactive mapping table is being used to prepare for new changes, the active mapping table is used to control unloading of all ATM-VCCs. A change of mapping table is controlled by Signal 4-2 from switch control (see Fig. 4), which Signal 4-2 contains all information to alter the inactive mapping table to the new situation. When the inactive mapping table is altered, the receiving control sends a confirmation signal (Signal 4-3 [see Fig. 4]) back to receiving control unit 214 and enters the "wait for inband synchronization signal". It also prepares input control unit 230 for the ATM-VCC in question that a change of frame code in the DCE field can be expected. When input control unit 230 for the ATM-VCC in question detects a change in frame code (e.g., a different value in field 6-1 [see Fig. 6]), notification is sent to receiving control unit 214. The receiving control unit 214 now changes the mapping tables (e.g., the active mapping table becomes inactive and vice versa). The change must be synchronized with the wrap around of the time slot counter unit 202 and when the complete new ATM-cell frame has been stored (and a swap from write side buffer to the read side buffer of the frame buffer is carried out). After that receiving control unit 214 sends Signal 4-6 (see Fig. 4) back to switch control unit 12, indicating "mission completed". The receiving control unit 214 can now enter the state "idle" and wait for next call setup, i.e. a new Signal 4-2.

Fig. 7 is a simplified timing diagram showing processing of an ATM frame 7-A in accordance with the invention, and particularly describing actions of switching node 10 with respect to ATM frame 7-A commencing from receipt of the TDM-frame, writing and reading in frame buffers, and in general the travel of the ATM frame 60 from sending port 100 to receiving port 200.

Fig. 7 shows a snapshot of example frames including frame 7-A during five 125 μs consecutive frame times, particularly frame times 7-1 through 7-5. The left hand column of Fig. 7 is divided into a box for sending port 100 and a box for receiving port 200. The box for sending port 100 has four vertically listed components labeled "TDM- frame"; FB-write"; "FB-read", and "FIFO" corresponding respectively to the incoming TDM frame; whichever frame buffer 122, 124 is the writing side frame buffer; whichever frame buffer 122, 124 is reading side frame buffer; and FIFO unit 132. Similarly, the box for receiving port 200 has four vertically listed components labeled "FIFO", "FB-write", "FB-read", and "TDM-frame", corresponding respectively to FIFO register 236; whichever frame buffer 222 or 224 is the writing side buffer; whichever frame buffer 222 or 224 is the reading side buffer; and the outgoing TDM frame output from TDM frame generator 240. In Fig. 7, graphical information is horizontally aligned with each of the vertically listed components to reflect operation of switching node 10 of the invention with respect to each component during the frame times 7-1 through 7-5. Everything described below with respect to Fig. 7 is repeated every 125 μs.

In Fig. 7, the time slots in the TDM-frames are repeated every 125 μs time frame. The time slot contents may change from frame to frame since they contain the PCM (Pulse Code Modulation) speech. The main flow takes five frame times, i.e., frame times 7-1 through 7-5. Everything depicted in dotted lines in Fig. 7 indicates this repetitiveness but will not be described in the text below. The frame buffers are not truly depicted in the time concept of Fig. 7. The frame buffers are regarded in Fig. 7 as a temporary placeholder. Time slots can be written and read from the frame buffer during the whole 125 μs interval since they contain a write and read side that alternates every 125 us frame.

At frame time 7-1, for frame 7-A the active mapping table of sending port 100 (see Fig. 2) takes the designated time slots from the TDM-frame, so that under control of sending control unit 114 the frame contents of frame 7-A are written to the frame buffer 122 or 124 (whichever is the writing side buffer) belonging to the ATM-VCC board 106 in question. The arriving time slots are written in a position in the writing side frame buffer given by the active mapping table. After writing, the frame buffer 122 or 124 contains the entire ATM-cell frame (in the preferred embodiment). The shaded frame buffer beneath indicates that it belongs to another ATM-VCC, destined to another receiving side. (The mapping table stores the time slots from the TDM-frame to that buffer as well during the 125 us period.)

Frame time 7-2 of Fig. 7 depicts the first side frame buffer 122 and first side frame buffer 122 switching states, so that with respect to frame 7-A the frame buffer into which the time slots were written during frame time 7-1 is now in a read state. The frame buffer that has just switched to the read state now contains the full ATM-cell structure (in the example shown in Fig. 7 only a few time slots are unloaded and put in FIFO unit 132 and consequentially input to the ATM switch 44. Thus, only one ATM- cell is sufficient in this case). The shadowed frame buffer of Fig. 7 does the same thing, i.e. unload its content in the form of an ATM-cell structure into the FIFO.

At frame time 7-3, the ATM-cells of frame 7-A are transferred to the receiving port 200 given by the ATM-VCC. The cells received at receiving port 200 are stored in FIFO register 236. For sake of the illustration of Fig. 7, it is assumed that 125 μs is sufficient time for the ATM cells to be routed through the ATM switch 44. However, the invention is certainly not confined to any particular time of cell travel through ATM switch 44. The FIFO register 236 aligns the delay variation to a repeated 125 μs boundary, in a manner easily understood by existing technology (e.g., letting the average waiting time be a multiple of the 125 μs interval.)

At frame time 7-4, the ATM-cell payload contents of frame 7-A in FIFO register 236 is written into the frame buffer 220 for the given ATM-VCC. Again, in Fig. 7 the shaded ATM-cell represents another ATM-VCC, coining from another sending port.

At frame time 7-5, the frame buffer 220 is now shifting, so that the one of the frame buffer first side 222 and frame buffer second side 224 into which frame 7-A was written now switches state to the read state. The active mapping table of receiving port 200 (see Fig. 3) takes the time slots from the frame buffer 220 at the point in time when it shall be put in the outgoing TDM-frame. The mapping table can read from all positions in all the frame buffers 220, belonging to different ATM-VCCs. In this way, the outgoing TDM-frame can be assembled by TDM frame generator 240.

As explained above, Fig. 2 and Fig. 3 show the duplicated mapping tables for sending port 100 and receiving port 200, respectively. While data is taken from entries in the active mapping table, during run time the other mapping table (the inactive mapping table) is used to prepare changes. Once the changes are ready, a swap of the roles of the mapping tables occurs. Such a swap must be made between two 125 μs frames, i.e. when the time slot counters wrap around. Consider a situation in which the swap of the mapping tables occurs at a boundary between frame time 7-1 and frame time 7-2. The time slots taken from the incoming TDM-frame in frame time 7-2, i.e., frame 7-B, are therefore controlled by the new mapping table and differ from the time slot in the previous frame (i.e., frame 7-B). However, it will not interfere with the read of frame 7-A from the frame buffer since those time slots of frame 7-A were stored in the previous TDM-frame and also in a physically other frame buffer.

In frame time 7-3, when the new connection situation affecting frame 7-B has propagated to the frame buffer read side (not shown in Fig. 7), the output control unit 130 of sending port 100 will generate the DCE octet (see Fig. 6) indicating that the frame is changed.

During frame time 7-5, the new connection situation (e.g., frame 7-B) will have reached the write side frame buffer of frame buffer unit 220 in the receiving port 200. The mapping table of receiving port 200 is now informed, by the DCE-octet of the new connection situation (i.e., cells in frame 7-B). The receiving port 200 will then use the mapping table to write in the frame buffer accordingly. The receiving port 200 will use the old mapping table to read from the frame buffer. Thus, it will not change the previous connection situation (for frame 7-A) since that is taken from the physically separated read side of the frame buffer, that was written in the frame buffer during the previous frame time 7-4. In a subsequent frame time 7-6 (not shown in Fig. 7), the new mapping table will be used also for the read side for handling frame 7-B. In this way a new connection situation (typified by frame 7-B) can be propagated through the switch without any loss or duplication of time slots in old connections (e.g., frame 7-A).

Thus, the present invention provides a cost efficient alternative to replacing an entire switch. The present invention replaces the DL-MUX 824 (see Fig. 8) with a time division capability and the new dynamic circuit emulation method as described herein. Further, the present invention replaces the group-switch 830 (see Fig. 8) with a standard ATM switch. Alternatively, the present invention replaces the group-switch with a cell switching fabric able to switch smaller cells than standard ATM-cells. Advantageously, the techniques of the present invention can be applied to most prior art ATM-switches. The invention is not limited to set up only narrowband calls. Any bandwidth can be accommodated. Furthermore, in the same signaling procedure several calls can be setup or torn down provided it concerns the same ATM-VCC.

The present invention thus employs circuit emulation for composite users but makes the emulation dynamic, e.g., "dynamic circuit emulation". The invention thus allows narrowband connections through the switch to be added or removed to the ATM- cell frame structure. In this regard, whenever a change in the frame structure is taking place (i.e. add or remove a connection) the changes are first signaled to both ports (sending port 100 and receiving port 200) on each side of ATM switch 44. After that, a synchronization signal 4-5 is provided inband in the frame structure to indicate at the receiver side (receiving port 200) exactly when the change takes place.

With reference to the prior art with the bandwidth waste showed in Fig. 10, a substantial saving can be made by using the invention. The fragmentation is avoided and the number of ATM cells in the frame is adjusted to the actual need of active narrowband connections. The maximum bandwidth loss corresponds to 46 time slots (e.g., if only one narrowband connection between two ports is set-up).

As understood from the foregoing, if only one narrowband channel is transported, the remaining 46 useful octets in the ATM-cell payload are wasted. By applying the same basic idea but reducing the ATM-cell payload size, e.g., to ten octets, in the last ATM cell of the frame the granularity can be improved and the waste further reduced. By using smaller ATM cells, e.g., so-called mini-cells, the bandwidth waste can be further reduced. For example, the last cell in the frame can be adapted to the actually used number of time slots (see Fig. 9). This technique can be important for subrate handling since a channel could be only one bit repeated every 125 :s. The central cell switch can be used for switching cell-based traffic as an independent function. The most common cell based traffic is ATM cells, but other formats are also possible, e.g., mini-cells that are smaller than ordinary ATM cells.

Voice transmission is an emerging new service for Internet. Due to the limited available bandwidth for Internet traffic, voice will be transferred using voice compression. The switching mechanisms for voice for Internet Protocol has to be optimized for much lower bandwidth than 64 kbits/s. The cell switch structure described above can fulfill such demands with a flexible cell size.

In ATM-based telecommunications, there is a trade off between delay and bandwidth gain. The packetizing delay is 6 ms, if one ATM-VCC per narrowband connection is used. The present invention shows how this delay can be reduced to 125 :s at the expense of bad granularity. The invention in such situation gives up to 3 Mbps bandwidth loss if the mini-cell scheme described above is not applied. By instead allowing a number of consecutive time slots for the same connection in the ATM-VCC, the granularity can be improved. For example, if 5 time slots are concatenated and allowed for the same connection, a delay of only 0.5 ms occurs, and the worst bandwidth waste is reduced to 512 kbps.

The invention facilitates economical and efficient increase of the number of 64 Kbit circuits for switch fabric sizes larger than 128 k port (e.g., 256k, 512k, etc.). to make true non-blocking large circuit switches is generally considered more costly compared to non-blocking ATM switches of similar size.

The present invention allows implementation of switching fabrics for circuit switched traffic with the cost advantage of ATM switching fabrics. Further, the present invention allows upgrades when traffic requirements so justify.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

WHAT IS CLAIMED IS:
1. A switch for a telecommunications exchange which adapts a time slot in an incoming TDM-frame to an ATM frame in accordance with a predetermined ATM- VCC, and which dynamically changes a number of ATM cells in the ATM frame for the predetermined ATM-VCC in accordance with a changing number of connections carried through an ATM switch fabric of the exchange.
2. The apparatus of claim 1, wherein the exchange comprises the switch fabric; a sending port; and a receiving port; and wherein an inband synchronization signal is carried in an ATM frame routed through the ATM switch fabric from the sending port to the receiving port for coordinating a changing frame structure between the sending port and the receiving port in accordance with the changing number of connections.
3. The apparatus of claim 2, wherein the inband signal from the sending port includes an octet included in the ATM frame, and wherein the octet has a table bit field which is employed for the coordinating of the changing frame structure.
4. The apparatus of claim 1, wherein the number of ATM cells in the ATM frame for the predetermined ATM-VCC varies between one and sixty four.
5. The apparatus of claim 1, wherein one ATM cell in the ATM frame for the predetermined ATM-VCC convey eleven time slots.
6. A switch for a telecommunications exchange comprising: a sending port; a receiving port; an ATM switch fabric connected intermediate the sending port and the receiving port; wherein, for a connection routed through the ATM switch fabric from the sending port to the receiving port, the sending port adapts a time slot in an incoming TDM- frame to an ATM frame in accordance with a predetermined ATM-VCC; a control unit which supervises the sending port and the receiving port for dynamically changing a number of ATM cells in the ATM frame for the predetermined ATM-VCC in accordance with a number of connections carried through the switch fabric between the sending port and the receiving port.
7. The apparatus of claim 6, wherein the sending port comprises: a sending port first mapping table and a sending port second mapping table, wherein the sending port first mapping table and the sending port second mapping table alternate roles of being a sending port active mapping table and a sending port inactive mapping table, the sending port active mapping table being used for preparing an ATM frame for an existing traffic situation on the predetermined ATM-VCC; wherein the sending port inactive mapping table is used by the sending port for preparing an ATM frame for a changed traffic situation on the predetermined ATM-VCC; and wherein in response to a signal from the control unit indicating a change in the number of connections carried through the switch fabric between the sending port and the receiving port, the roles of the sending port first mapping table and the sending port second mapping table are switched.
8. The apparatus of claim 7, wherein the sending port further comprises a sending port frame buffer having a first side and a second side, wherein the first side and the second side of the sending port frame buffer alternate roles of having ATM frames written therein and having ATM frames readout therefrom.
9. The apparatus of claim 7, wherein the receiving port comprises: a receiving port first mapping table and a receiving port second mapping table, wherein the receiving port first mapping table and the receiving port second mapping table alternate roles of being a receiving port active mapping table and a receiving port inactive mapping table, the receiving port active mapping table being used for decoding an ATM frame for an existing traffic situation on the predetermined ATM-VCC; wherein the receiving port inactive mapping table is used by the receiving port for decoding an ATM frame for a changed traffic situation on the predetermined ATM- VCC; and wherein in response to a signal from sending port, the roles of the receiving port first mapping table and the receiving port second mapping table are switched.
10. The apparatus of claim 9, wherein the signal from the sending port is an inband signal carried in an ATM frame routed through the ATM switch fabric from the sending port to the receiving port.
11. The apparatus of claim 10, wherein the inband signal from the sending port includes an indication that the receiving port first mapping table and the receiving port second mapping table are to switch roles.
12. The apparatus of claim 10, wherein the inband signal from the sending port includes an octet included in the ATM frame, and wherein the octet has a table bit field which indicates that the receiving port first mapping table and the receiving port second mapping table are to switch roles.
13. The apparatus of claim 9, wherein the sending port further comprises a receiving port frame buffer having a first side and a second side, wherein the first side and the second side of the receiving port frame buffer alternate roles of having ATM frames written therein and having ATM frames readout therefrom.
14. The apparatus of claim 6, wherein the number of ATM cells in the ATM frame for the predetermined ATM-VCC varies between one and sixty four.
15. The apparatus of claim 6, wherein one ATM cell in the ATM frame for the predetermined ATM-VCC convey eleven time slots.
16. A method of operating a switch in a telecommunications exchange, the method comprising: adapting, for a connection routed through an ATM switch fabric of the exchange, a time slot in an incoming TDM-frame to an ATM frame in accordance with a predetermined ATM-VCC; dynamically changing a number of ATM cells in the ATM frame for the predetermined ATM-VCC in accordance with a changing number of connections carried through the ATM switch fabric using the predetermined ATM-VCC.
17. The method of claim 16, wherein the switch includes a sending port and a receiving port, and wherein the method further comprises sending an inband synchronization signal in an ATM frame through the ATM switch fabric from the sending port to the receiving port for coordinating a changing frame structure between the sending port and the receiving port in accordance with the changing number of connections.
18. The method of claim 16, wherein the switch includes a sending port and a receiving port, and wherein the method further comprises: establishing a sending port first mapping table and a sending port second mapping table in the sending port; alternating between the sending port first mapping table and the sending port second mapping table roles of being a sending port active mapping table and a sending port inactive mapping table; using the sending port active mapping table for preparing an ATM frame for an existing traffic situation on the predetermined ATM-VCC; using the sending port inactive mapping table for preparing an ATM frame for a changed traffic situation on the predetermined ATM-VCC; and in response to a signal from a control unit, alternating the roles of the sending port first mapping table and the sending port second mapping table.
19. The method of claim 18, further comprising: providing a sending port frame buffer in the sending port, the sending port frame buffer having a first side and a second side; and alternating between the first side and the second side of the sending port frame buffer roles of having ATM frames written therein and having ATM frames readout therefrom.
20. The method of claim 18, further comprising: establishing a receiving port first mapping table and a receiving port second mapping table in the receiving port; alternating between the receiving port first mapping table and the receiving port second mapping table roles of being a receiving port active mapping table and a receiving port inactive mapping table; using the receiving port active mapping table for decoding an ATM frame for an existing traffic situation on the predetermined ATM-VCC; using the receiving port inactive mapping table for decoding an ATM frame for a changed traffic situation on the predetermined ATM-VCC; and in response to a signal from sending port, switching the roles of the sending port first mapping table and the sending port second mapping table.
21. The method of claim 20, wherein the signal from the sending port is an inband signal carried in an ATM frame routed through the ATM switch fabric from the sending port to the receiving port.
22. The method of claim 21, wherein the inband signal from the sending port includes an indication that the receiving port first mapping table and the receiving port second mapping table are to switch roles.
23. The method of claim 21, wherein the inband signal from the sending port includes an octet included in the ATM frame, and wherein the octet has a table bit field which indicates that the receiving port first mapping table and the receiving port second mapping table are to switch roles.
24. The method of claim 20, further comprising: providing in the receiving port a receiving port frame buffer having a first side and a second side, wherein the first side and the second side of the receiving port frame buffer alternate roles of having ATM frames written therein and having ATM frames readout therefrom.
25. The method of claim 16, further comprising varying the number of ATM cells in the ATM frame for the predetermined ATM-VCC between one and sixty four.
26. The method of claim 16, further comprising including eleven time slots in one ATM cell in the ATM frame for the predetermined ATM-VCC.
PCT/SE2000/001766 1999-09-16 2000-09-13 Dynamic circuit emulation using atm switches WO2001020858A1 (en)

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EP20000963226 EP1216552A1 (en) 1999-09-16 2000-09-13 Dynamic circuit emulation using atm switches
AU74671/00A AU7467100A (en) 1999-09-16 2000-09-13 Dynamic circuit emulation using atm switches

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