WO2000075967A3 - Method for fabrication of a low resistivity mosfet gate with thick metal silicide on polysilicon - Google Patents
Method for fabrication of a low resistivity mosfet gate with thick metal silicide on polysilicon Download PDFInfo
- Publication number
- WO2000075967A3 WO2000075967A3 PCT/US2000/006599 US0006599W WO0075967A3 WO 2000075967 A3 WO2000075967 A3 WO 2000075967A3 US 0006599 W US0006599 W US 0006599W WO 0075967 A3 WO0075967 A3 WO 0075967A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- polysilicon
- metal silicide
- gate
- mosfet
- present
- Prior art date
Links
- 239000002184 metal Substances 0.000 title abstract 11
- 229910021332 silicide Inorganic materials 0.000 title abstract 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title abstract 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title abstract 9
- 229920005591 polysilicon Polymers 0.000 title abstract 9
- 238000000034 method Methods 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000151 deposition Methods 0.000 abstract 2
- 238000005498 polishing Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 230000005669 field effect Effects 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00917912A EP1181711A2 (en) | 1999-06-03 | 2000-03-13 | Method for fabrication of a low resistivity mosfet gate with thick metal silicide on polysilicon |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/325,023 | 1999-06-03 | ||
US09/325,023 US6187675B1 (en) | 1999-06-03 | 1999-06-03 | Method for fabrication of a low resistivity MOSFET gate with thick metal silicide on polysilicon |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000075967A2 WO2000075967A2 (en) | 2000-12-14 |
WO2000075967A3 true WO2000075967A3 (en) | 2001-07-05 |
Family
ID=23266116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/006599 WO2000075967A2 (en) | 1999-06-03 | 2000-03-13 | Method for fabrication of a low resistivity mosfet gate with thick metal silicide on polysilicon |
Country Status (3)
Country | Link |
---|---|
US (1) | US6187675B1 (en) |
EP (1) | EP1181711A2 (en) |
WO (1) | WO2000075967A2 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6277739B1 (en) * | 2000-10-30 | 2001-08-21 | Vanguard International Semiconductor Corporation | Method of forming a barrier layer underlying a tungsten plug structure in a high aspect ratio contact hole |
US6514859B1 (en) * | 2000-12-08 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of salicide formation with a double gate silicide |
US6482739B2 (en) * | 2001-02-21 | 2002-11-19 | United Microelectronics Corp. | Method for decreasing the resistivity of the gate and the leaky junction of the source/drain |
US6784098B1 (en) * | 2001-04-30 | 2004-08-31 | Taiwan Semiconductor Manufacturing Company | Method for forming salicide process |
KR100557578B1 (en) * | 2002-12-07 | 2006-03-03 | 주식회사 하이닉스반도체 | A method for forming of a semiconductor device |
KR100480917B1 (en) * | 2003-02-19 | 2005-04-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
US6864161B1 (en) * | 2003-02-20 | 2005-03-08 | Taiwan Semiconductor Manufacturing Company | Method of forming a gate structure using a dual step polysilicon deposition procedure |
US6867130B1 (en) * | 2003-05-28 | 2005-03-15 | Advanced Micro Devices, Inc. | Enhanced silicidation of polysilicon gate electrodes |
US6974736B2 (en) * | 2004-01-09 | 2005-12-13 | International Business Machines Corporation | Method of forming FET silicide gate structures incorporating inner spacers |
FR2881575B1 (en) * | 2005-01-28 | 2007-06-01 | St Microelectronics Crolles 2 | MOS TRANSISTOR WITH TOTALLY SILICATED GRID |
US20070296052A1 (en) | 2006-06-26 | 2007-12-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming silicide regions and resulting MOS devices |
US20080233703A1 (en) * | 2007-03-21 | 2008-09-25 | Atmel Corporation | Polysilicon conductivity improvement in a salicide process technology |
KR101203239B1 (en) * | 2007-12-04 | 2012-11-20 | 가부시키가이샤 어드밴티스트 | Delay circuit, multi-stage delay circuit, time digital converter using them, semiconductor test device, ring oscillator, and delay lock loop circuit |
US7999332B2 (en) * | 2009-05-14 | 2011-08-16 | International Business Machines Corporation | Asymmetric semiconductor devices and method of fabricating |
KR20110101967A (en) * | 2010-03-10 | 2011-09-16 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0303061A2 (en) * | 1987-08-13 | 1989-02-15 | International Business Machines Corporation | Process for forming a planarized, metal-strapped polysilicon gate FET |
EP0601951A2 (en) * | 1992-12-11 | 1994-06-15 | International Business Machines Corporation | Process for improving sheet resistance of a fet device gate |
US5731239A (en) * | 1997-01-22 | 1998-03-24 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance |
US5869396A (en) * | 1996-07-15 | 1999-02-09 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a polycide gate electrode |
US5953612A (en) * | 1997-06-30 | 1999-09-14 | Vlsi Technology, Inc. | Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device |
US6025254A (en) * | 1997-12-23 | 2000-02-15 | Intel Corporation | Low resistance gate electrode layer and method of making same |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2582445B1 (en) * | 1985-05-21 | 1988-04-08 | Efcis | METHOD FOR MANUFACTURING METAL SILICIDE ELECTRODE MOS TRANSISTORS |
-
1999
- 1999-06-03 US US09/325,023 patent/US6187675B1/en not_active Expired - Lifetime
-
2000
- 2000-03-13 WO PCT/US2000/006599 patent/WO2000075967A2/en not_active Application Discontinuation
- 2000-03-13 EP EP00917912A patent/EP1181711A2/en not_active Withdrawn
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0303061A2 (en) * | 1987-08-13 | 1989-02-15 | International Business Machines Corporation | Process for forming a planarized, metal-strapped polysilicon gate FET |
EP0601951A2 (en) * | 1992-12-11 | 1994-06-15 | International Business Machines Corporation | Process for improving sheet resistance of a fet device gate |
US5869396A (en) * | 1996-07-15 | 1999-02-09 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a polycide gate electrode |
US5731239A (en) * | 1997-01-22 | 1998-03-24 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance |
US5953612A (en) * | 1997-06-30 | 1999-09-14 | Vlsi Technology, Inc. | Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device |
US6025254A (en) * | 1997-12-23 | 2000-02-15 | Intel Corporation | Low resistance gate electrode layer and method of making same |
Also Published As
Publication number | Publication date |
---|---|
US6187675B1 (en) | 2001-02-13 |
WO2000075967A2 (en) | 2000-12-14 |
EP1181711A2 (en) | 2002-02-27 |
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