WO2000074453A1 - Package for high power microelectronics - Google Patents

Package for high power microelectronics Download PDF

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Publication number
WO2000074453A1
WO2000074453A1 PCT/US2000/014821 US0014821W WO0074453A1 WO 2000074453 A1 WO2000074453 A1 WO 2000074453A1 US 0014821 W US0014821 W US 0014821W WO 0074453 A1 WO0074453 A1 WO 0074453A1
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WO
WIPO (PCT)
Prior art keywords
base
ring
package
copper alloy
cavity
Prior art date
Application number
PCT/US2000/014821
Other languages
French (fr)
Inventor
Stephen W. Struck
Steven A. Tower
Original Assignee
Olin Aegis
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olin Aegis filed Critical Olin Aegis
Priority to AU53036/00A priority Critical patent/AU5303600A/en
Publication of WO2000074453A1 publication Critical patent/WO2000074453A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Definitions

  • This invention relates to packaging for semiconductor devices, and more particularly to hybrid packages for encasing multiple high power devices in a single package.
  • a wide variety of semiconductor packaging technologies are known.
  • One basic package family is known as the TO-2XX series.
  • Such a package is disclosed as prior art in U.S. Patent No. 5,107,074.
  • the '074 patent discloses a package having a copper or copper alloy base to which a copper, copper alloy, or steel ring is affixed to define a cavity for accommodating a semiconductor device.
  • a base having a high coefficient of thermal conductivity is advantageous. Copper is one such material.
  • Heat dissipation is increasingly important as: (a) the number of separate semiconductor substrates in a given package increases; (b) the size of the substrate(s) increases; and (c) the circuitry density on such substrate(s) increases.
  • a disadvantage of utilizing copper for a package base is that the high temperature brazing of the ring to the base causes the base to anneal and soften.
  • the annealed base may yield under loading during assembly, testing or in the field, thereby transferring potentially damaging stress to the semiconductor device.
  • the stress may lead to device fracture and failure.
  • this may not be a significant problem, as given the small span across the cavity, the relatively rigid ring prevents significant deformation of the base.
  • cavity size increases, and the distance between the center of the cavity and the ring increases, such distance allows for greater deformation of the base at a distance from the ring.
  • a low temperature braze e.g., at less than 300° C.
  • Such low temperature brazing may require a relatively expensive brazing material such as gold/tin eutectic.
  • such a construction has the disadvantage of being incompatible with any subsequent high temperature operations such as glass sealing of conductors and eutectic substrate or die attach above 300°C.
  • the invention is directed to a package for housing one or ore semiconductor devices.
  • the package has a base formed of a copper alloy having a fully annealed tensile strength in excess of 40 ksi (276 MPa) at room temperature.
  • the package includes a stainless steel ring brazed atop the base with a brazing material having a melting point in excess of 700° C.
  • the combination of the ring and the base at least partially defines a cavity for containing the semiconductor device(s).
  • the ring may be the unitary combination of first and second pairs of sidewalls arrayed as a rectangle.
  • At least one sidewall includes at least one aperture for accommodating at least one lead for electrical communication between the device and the exterior of the cavity.
  • Each sidewall of the first pair may include such aperture(s) for example, as a dual inline package (DIP).
  • DIP dual inline package
  • Each sidewall of the first and second pairs of sidewalls may include such aperture(s) as a quad package.
  • the leads may be glass sealed within the associated aperture(s).
  • the base may have a coefficient of linear thermal expansion of between about 15 x 10 " 7° K and about 20 x 10N° K at 20° C.
  • the base may have a thermal conductivity of between about 230W/m/° K and about 350 W/m/° K at 20° C.
  • the package may further include a lid welded to the ring to hermetically seal the cavity containing the device(s).
  • the brazing material may be a silver/copper alloy.
  • the base may be formed of an alloy selected from C 19400 and C 19700.
  • the invention is directed to a method for packaging a large semiconductor device so as to avoid package distortion.
  • a copper alloy base is provided.
  • a steel ring is provided having an interior with a length and a width each in excess of 2.5 cm.
  • Through holes are provided in the ring.
  • Conductors are placed through associated through holes.
  • the conductors are secured to the ring by associated glass seals.
  • the ring is brazed atop the base with a brazing material having a melting point in excess of 700° C so that the base and ring interior at least partially define a cavity dimensioned to receive the large semiconductor device.
  • Implementations of the invention may include one or more of the following.
  • the securing step may occur prior to the brazing step and the brazing material may have a melting point below 900° C.
  • Such brazing material may be a silver/copper alloy.
  • the brazing step may occur prior to the securing step and the brazing material may have a melting point in excess of 900° C.
  • Such brazing material may be a gold/copper/nickel alloy.
  • the method may further include securing the large semiconductor device to the base within the ring interior. Electrical connections may be formed between the large semiconductor device and the conductors.
  • a lid may be secured atop the ring so as to encapsulate the large semiconductor device within the package interior. The lid may be so secured by seam sealing the lid to the ring.
  • the base may be provided having an annealed tensile strength of at least 40 ksi (276 MPa).
  • the base may be provided having an annealed tensile strength at least equal to an annealed tensile strength of C 19400 copper alloy.
  • the base may be provided having a thermal conductivity at least equal to a thermal conductivity of C 19400 copper alloy.
  • the base may be provided having a thickness of from about one mm to about two mm.
  • FIG. 1 is a top view of a package according to principles of the invention shown with a cover removed.
  • FIG. 2 is a cross-sectional view of the device of FIG. 1, taken along line 2-2.
  • FIG. 1 shows a package 20 for containing one or more semiconductor substrates or dies 22A and 22B.
  • the package 20 includes a base 24 formed of a flat strip of copper alloy and having any desired shape and is preferably substantially rectangular in shape with upper and lower surfaces 26 and 28 (FIG. 2) and four sides 30A, 30B, 30C, and 30D, each side meeting two adjacent sides at associated corners. The corners may be rounded to reduce tooling cost. Adjacent to each corner is an associated mounting hole 32 extending between the upper and lower surfaces 26 and 28. A ring 34 is brazed atop the upper surface 26 of the base 24. The ring 34 is located inboard of the mounting holes 32. The ring is preferably substantially rectangular in the shape.
  • the ring 34 has upper and lower surfaces 36 and 38 and, in the illustrated embodiment, is formed as the unitary combination of four walls, 40A, 40B, 40C, and 40D.
  • the ring has an inboard side surface 42 and an outboard side surface 44.
  • a lid 50 is preferably of similar size and shape as the ring 34.
  • the lid 50 has an upper surface 52 and a lower surface 54 and is secured atop the ring 34 so that the lid lower surface 54, base upper surface 26 and ring inboard surface 42 cooperate to define a cavity 60 for accommodating the dies 22A and 22B.
  • a plurality of conductors 62 and 64 extend through respective through-holes 66 and 68 in the ring 34.
  • the conductors 62 and 64 are secured to the ring 34 via glass insulators 70 and 72 (FIG.
  • the ring 34 and base 24 are separately formed and their respective through-holes 66 and 68 and mounting holes 32 are formed by punching, drilling, or the like.
  • the conductors 62 and 66 are placed within their associated insulators 70 and 72 and the insulators are inserted into the through-holes 66 and 68.
  • the conductors may be inserted into the insulators after the latter are inserted in the through-holes.
  • the insulators are melted to securely bond to both their associated conductors and the surfaces defining the associated through-holes so as to mechanically secure the conductors to the ring in an electrically insulated and environmentally sealed fashion.
  • An exemplary glass sealing temperature is about 1 ,000° C.
  • An exemplary glass is potash soda barium.
  • the ring 34 is then brazed to the base 24, the upper surface 26 of the base engaged to the lower surface 38 of the ring via the brazed joint.
  • the brazing advantageously occurs at a temperature sufficiently below the glass sealing temperature.
  • the brazing occurs at a temperature at least 100° C below the glass sealing temperature.
  • the brazing may be performed at about 800° C using a silver/copper alloy brazing material.
  • Exemplary silver/copper alloy brazing material is 72% Ag, 28% Cu, having a melting temperature of 780° C.
  • the lid 50 is separately prepared and the package may be cleaned and subjected to other preparative processing and then sold or distributed for users to incorporate the dies 22 A and 22B.
  • the dies 22A and 22B are installed within the cavity 60 such as via a low temperature soldering or epoxying of the lower surface or underside 80 of each such die to the upper surface 26 of the base 24.
  • Connections 82 and 84 are made between the inboard extremities of the conductors 62 and 64 and contacts on the upper surface 86 of each die via wirebonding or other appropriate technique.
  • the cover or lid 50 is then welded to the ring 34 for example, by seam sealing.
  • the seam sealing, glass sealing, and ring-to-base brazing cooperate to hermetically isolate the cavity 60 from the external environment.
  • the package sequentially passes through three internally connected chambers of a seam sealing machine. In the entrance chamber, the package is baked in a vacuum to remove water, cleaning chemicals, and other contaminants. The package then passes to the welding chamber wherein the lid is welded to the ring in a dry nitrogen atmosphere via a series of overlapping spot welds. The welded package then proceeds to an exit chamber which is purged with dry nitrogen to serve as a load lock chamber preventing contamination of the welding chamber. Upon removal from the exit chamber, the packaged device is ready for testing and use.
  • the lid is formed of a weld-compatible material to that of the ring.
  • the lid may be stainless steel or may be nickel.
  • the order of glass sealing and brazing is reversed.
  • the brazing is performed at an even higher temperature with an even higher melting point brazing material.
  • it may be performed at about 1,030° C with a gold/copper/nickel alloy brazing material.
  • Exemplary gold/copper alloy brazing material is 35% Au, 62% Cu, 3% Ni, having a melting temperature of 1030° C. The subsequent glass sealing at the exemplary 1,000° C thus does not compromise the braze joint.
  • Preferred materials for the base are copper alloys having: a coefficient of thermal expansion (CTE) which is close (e.g., within about 5%) to that of the stainless steel or other material used to form the ring 34 (e.g., 304 stainless steel); an annealed yield strength which exceeds that of pure copper (preferably by at least 50%); and a thermal conductivity which is as high as possible to provide an advantageous degree of heat dissipation.
  • CTE coefficient of thermal expansion
  • C 10200 (an essentially pure copper of at least 99.95% Cu by weight) has an annealed yield strength (0.2%) of about 10 ksi (69 MPa), an annealed tensile strength of about 26-38 ksi ( 179-262 MPa), a CTE of about 17 ⁇ m/m/° K (9.4 ⁇ in./inJ F), and a thermal conductivity of about 391 W/m/° K (226 Btu/ft/h/° F) at ambient room temperature conditions of 20° C (68° F).
  • Exemplary alloys useful for the base are C 19400 (nominal composition 2.1-2.6% Fe, 0.05-0.20% Zn, 0.015-0.15% P, ⁇ 0.03% Pb, ⁇ 0.03% Sn, ⁇ 0J5% total other, balance Cu) and C19700 (nominal composition 0.3-1.2% Fe, 0.1-0.4% P, 0.01-0.2% Mg, ⁇ 0J% Zn, ⁇ 0.05% Pb, ⁇ 0J% Sn, ⁇ 0.05% Co, ⁇ 0.05% Mn, ⁇ 0.05% Ni, ⁇ 0J% total other, balance Cu). Unless otherwise indicated, all compositional percentages are by weight.
  • the brazing process may fully anneal the base 24 made out of these alloys
  • the alloys have a sufficiently high yield strength in a full anneal temper to prevent deformation and thus damage to the dies upon experiencing environmental testing (including constant acceleration) or other stresses. Exemplary tests are per United States Military Standard 883E. At room temperature, these two alloys have respective annealed tensile strengths of 40-63 ksi (276-434 MPa) and 43-53 ksi
  • the package 20 is useful for containing high power devices such as those formed of relatively large dies (e.g., greater than one cm 2 ), multiple dies, or of dies having a relatively high circuit density and thus a high power (heat) dissipation (e.g., greater than about 50 W).
  • the cavity has a length (L) and a width (W) each of about 2.5 cm or greater.
  • a typical cavity height (H) will be in the vicinity of 0J cm to about 1.0 cm.
  • an advantageous cavity size range has a width from about 2.5 cm to about 5.0 cm and a length from about 5.0 cm to about 12.0 cm.
  • a preferred thickness of the base 24 is from about 0J cm to about 0J5 cm.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A package (20) for housing one or more semiconductor devices (22A; 22B) has a base (24) formed of a copper alloy having a fully annealed tensile strength in excess of 40 ksi (276MPa) at room temperature. The package includes a stainless steel ring (34) brazed atop the base with a brazing material having a melting point in excess of 700 °C. The combination of the ring and the base at least partially defines a cavity (60) for containing the semiconductor device(s). The cavity has a length and a width each in excess of 2.5 cm.

Description

PACKAGE FOR HIGH POWER MICROELECTRONICS
This invention relates to packaging for semiconductor devices, and more particularly to hybrid packages for encasing multiple high power devices in a single package. A wide variety of semiconductor packaging technologies are known. One basic package family is known as the TO-2XX series. Such a package is disclosed as prior art in U.S. Patent No. 5,107,074. The '074 patent discloses a package having a copper or copper alloy base to which a copper, copper alloy, or steel ring is affixed to define a cavity for accommodating a semiconductor device. In order to dissipate heat generated by the semiconductor device(s), use of a base having a high coefficient of thermal conductivity is advantageous. Copper is one such material. Heat dissipation is increasingly important as: (a) the number of separate semiconductor substrates in a given package increases; (b) the size of the substrate(s) increases; and (c) the circuitry density on such substrate(s) increases.
A disadvantage of utilizing copper for a package base is that the high temperature brazing of the ring to the base causes the base to anneal and soften. The annealed base may yield under loading during assembly, testing or in the field, thereby transferring potentially damaging stress to the semiconductor device. As most devices are formed of silicon or gallium arsenide, both brittle materials, the stress may lead to device fracture and failure. For relatively small packages, this may not be a significant problem, as given the small span across the cavity, the relatively rigid ring prevents significant deformation of the base. However, as cavity size increases, and the distance between the center of the cavity and the ring increases, such distance allows for greater deformation of the base at a distance from the ring. This renders such packaging unsuitable for high loading environments such as those associated with vibration, for example in aerospace or military applications. One way to address these problems is to avoid annealing the copper base. This may be achieved via the use of a low temperature braze (e.g., at less than 300° C). Such low temperature brazing may require a relatively expensive brazing material such as gold/tin eutectic. In addition to cost, such a construction has the disadvantage of being incompatible with any subsequent high temperature operations such as glass sealing of conductors and eutectic substrate or die attach above 300°C.
Accordingly, in one aspect, the invention is directed to a package for housing one or ore semiconductor devices. The package has a base formed of a copper alloy having a fully annealed tensile strength in excess of 40 ksi (276 MPa) at room temperature. The package includes a stainless steel ring brazed atop the base with a brazing material having a melting point in excess of 700° C. The combination of the ring and the base at least partially defines a cavity for containing the semiconductor device(s). The cavity has a length and a width each in excess of 2.5 cm. Implementations of the invention may include one or more of the following. The ring may be the unitary combination of first and second pairs of sidewalls arrayed as a rectangle. At least one sidewall includes at least one aperture for accommodating at least one lead for electrical communication between the device and the exterior of the cavity. Each sidewall of the first pair may include such aperture(s) for example, as a dual inline package (DIP). Each sidewall of the first and second pairs of sidewalls may include such aperture(s) as a quad package. The leads may be glass sealed within the associated aperture(s).
The base may have a coefficient of linear thermal expansion of between about 15 x 10"7° K and about 20 x 10N° K at 20° C. The base may have a thermal conductivity of between about 230W/m/° K and about 350 W/m/° K at 20° C. The package may further include a lid welded to the ring to hermetically seal the cavity containing the device(s). The brazing material may be a silver/copper alloy. The base may be formed of an alloy selected from C 19400 and C 19700.
In another aspect, the invention is directed to a method for packaging a large semiconductor device so as to avoid package distortion. A copper alloy base is provided. A steel ring is provided having an interior with a length and a width each in excess of 2.5 cm. Through holes are provided in the ring. Conductors are placed through associated through holes. The conductors are secured to the ring by associated glass seals. The ring is brazed atop the base with a brazing material having a melting point in excess of 700° C so that the base and ring interior at least partially define a cavity dimensioned to receive the large semiconductor device.
Implementations of the invention may include one or more of the following. The securing step may occur prior to the brazing step and the brazing material may have a melting point below 900° C. Such brazing material may be a silver/copper alloy. The brazing step may occur prior to the securing step and the brazing material may have a melting point in excess of 900° C. Such brazing material may be a gold/copper/nickel alloy. The method may further include securing the large semiconductor device to the base within the ring interior. Electrical connections may be formed between the large semiconductor device and the conductors. A lid may be secured atop the ring so as to encapsulate the large semiconductor device within the package interior. The lid may be so secured by seam sealing the lid to the ring. The base may be provided having an annealed tensile strength of at least 40 ksi (276 MPa). The base may be provided having an annealed tensile strength at least equal to an annealed tensile strength of C 19400 copper alloy. The base may be provided having a thermal conductivity at least equal to a thermal conductivity of C 19400 copper alloy. The base may be provided having a thickness of from about one mm to about two mm.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. FIG. 1 is a top view of a package according to principles of the invention shown with a cover removed.
FIG. 2 is a cross-sectional view of the device of FIG. 1, taken along line 2-2.
Like reference numbers and designations in the various drawings indicate like elements.
FIG. 1 shows a package 20 for containing one or more semiconductor substrates or dies 22A and 22B. The package 20 includes a base 24 formed of a flat strip of copper alloy and having any desired shape and is preferably substantially rectangular in shape with upper and lower surfaces 26 and 28 (FIG. 2) and four sides 30A, 30B, 30C, and 30D, each side meeting two adjacent sides at associated corners. The corners may be rounded to reduce tooling cost. Adjacent to each corner is an associated mounting hole 32 extending between the upper and lower surfaces 26 and 28. A ring 34 is brazed atop the upper surface 26 of the base 24. The ring 34 is located inboard of the mounting holes 32. The ring is preferably substantially rectangular in the shape. Other ring shapes and other hole locations outboard of the ring are also possible. The ring 34 has upper and lower surfaces 36 and 38 and, in the illustrated embodiment, is formed as the unitary combination of four walls, 40A, 40B, 40C, and 40D. The ring has an inboard side surface 42 and an outboard side surface 44. A lid 50 is preferably of similar size and shape as the ring 34. The lid 50 has an upper surface 52 and a lower surface 54 and is secured atop the ring 34 so that the lid lower surface 54, base upper surface 26 and ring inboard surface 42 cooperate to define a cavity 60 for accommodating the dies 22A and 22B. To provide electrical communication (signal and power) from without the package to within the package, a plurality of conductors 62 and 64 extend through respective through-holes 66 and 68 in the ring 34.
The conductors 62 and 64 are secured to the ring 34 via glass insulators 70 and 72 (FIG.
2). In an exemplary method of manufacture, the ring 34 and base 24 are separately formed and their respective through-holes 66 and 68 and mounting holes 32 are formed by punching, drilling, or the like. The conductors 62 and 66 are placed within their associated insulators 70 and 72 and the insulators are inserted into the through-holes 66 and 68. Alternatively, the conductors may be inserted into the insulators after the latter are inserted in the through-holes. In a high-temperature glass sealing operation, the insulators are melted to securely bond to both their associated conductors and the surfaces defining the associated through-holes so as to mechanically secure the conductors to the ring in an electrically insulated and environmentally sealed fashion. An exemplary glass sealing temperature is about 1 ,000° C. An exemplary glass is potash soda barium.
The ring 34 is then brazed to the base 24, the upper surface 26 of the base engaged to the lower surface 38 of the ring via the brazed joint. In this method it is required that the brazing not intolerably compromise the glass insulators 70 and 72 and their connection to the ring and conductors. To avoid such compromise, the brazing advantageously occurs at a temperature sufficiently below the glass sealing temperature. Advantageously, the brazing occurs at a temperature at least 100° C below the glass sealing temperature. For example, the brazing may be performed at about 800° C using a silver/copper alloy brazing material. Exemplary silver/copper alloy brazing material is 72% Ag, 28% Cu, having a melting temperature of 780° C. The lid 50 is separately prepared and the package may be cleaned and subjected to other preparative processing and then sold or distributed for users to incorporate the dies 22 A and 22B.
To complete the packaging of the devices, the dies 22A and 22B are installed within the cavity 60 such as via a low temperature soldering or epoxying of the lower surface or underside 80 of each such die to the upper surface 26 of the base 24. Connections 82 and 84 are made between the inboard extremities of the conductors 62 and 64 and contacts on the upper surface 86 of each die via wirebonding or other appropriate technique.
The cover or lid 50 is then welded to the ring 34 for example, by seam sealing. The seam sealing, glass sealing, and ring-to-base brazing cooperate to hermetically isolate the cavity 60 from the external environment. In an exemplary seam sealing process, the package sequentially passes through three internally connected chambers of a seam sealing machine. In the entrance chamber, the package is baked in a vacuum to remove water, cleaning chemicals, and other contaminants. The package then passes to the welding chamber wherein the lid is welded to the ring in a dry nitrogen atmosphere via a series of overlapping spot welds. The welded package then proceeds to an exit chamber which is purged with dry nitrogen to serve as a load lock chamber preventing contamination of the welding chamber. Upon removal from the exit chamber, the packaged device is ready for testing and use. To facilitate seam sealing, advantageously the lid is formed of a weld-compatible material to that of the ring. For example, where the ring is stainless steel, the lid may be stainless steel or may be nickel. In an alternative method of manufacture, the order of glass sealing and brazing is reversed. To ensure that the glass sealing process does not compromise the braze joint, the brazing is performed at an even higher temperature with an even higher melting point brazing material. For example, it may be performed at about 1,030° C with a gold/copper/nickel alloy brazing material. Exemplary gold/copper alloy brazing material is 35% Au, 62% Cu, 3% Ni, having a melting temperature of 1030° C. The subsequent glass sealing at the exemplary 1,000° C thus does not compromise the braze joint.
Preferred materials for the base are copper alloys having: a coefficient of thermal expansion (CTE) which is close (e.g., within about 5%) to that of the stainless steel or other material used to form the ring 34 (e.g., 304 stainless steel); an annealed yield strength which exceeds that of pure copper (preferably by at least 50%); and a thermal conductivity which is as high as possible to provide an advantageous degree of heat dissipation. For comparison, C 10200 (an essentially pure copper of at least 99.95% Cu by weight) has an annealed yield strength (0.2%) of about 10 ksi (69 MPa), an annealed tensile strength of about 26-38 ksi ( 179-262 MPa), a CTE of about 17 μm/m/° K (9.4 μin./inJ F), and a thermal conductivity of about 391 W/m/° K (226 Btu/ft/h/° F) at ambient room temperature conditions of 20° C (68° F).
Exemplary alloys useful for the base are C 19400 (nominal composition 2.1-2.6% Fe, 0.05-0.20% Zn, 0.015-0.15% P, ≤0.03% Pb, <0.03% Sn, <0J5% total other, balance Cu) and C19700 (nominal composition 0.3-1.2% Fe, 0.1-0.4% P, 0.01-0.2% Mg, <0J% Zn, ≤0.05% Pb, <0J% Sn, <0.05% Co, <0.05% Mn, <0.05% Ni, <0J% total other, balance Cu). Unless otherwise indicated, all compositional percentages are by weight. Even though the brazing process may fully anneal the base 24 made out of these alloys, the alloys have a sufficiently high yield strength in a full anneal temper to prevent deformation and thus damage to the dies upon experiencing environmental testing (including constant acceleration) or other stresses. Exemplary tests are per United States Military Standard 883E. At room temperature, these two alloys have respective annealed tensile strengths of 40-63 ksi (276-434 MPa) and 43-53 ksi
(297-365 MPa), CTE's of 16.3 μm/m/° K (9.0 μin./in. 1° F) and 15.8 μm m/° K (8.8 μin./in.
1° F), and thermal conductivities of 260 W/m/° K (150 Btu ft/h/0 F) and 320 W/m/° K (185 Btu ft/h/° F). Their annealed yield strengths are about twice that of C 10200. Other copper alloys (i.e., at least 50% copper) may also be useful for the base 24 if they have the desired properties. Among acceptable copper alloys is C 15000 (nominal composition 0.13-0.20% Zr, up to a residual amount of Ag, <0.05 other, balance Cu). Advantageously, the package 20 is useful for containing high power devices such as those formed of relatively large dies (e.g., greater than one cm2), multiple dies, or of dies having a relatively high circuit density and thus a high power (heat) dissipation (e.g., greater than about 50 W). Dimensionally, to accommodate the dies, the cavity has a length (L) and a width (W) each of about 2.5 cm or greater. A typical cavity height (H) will be in the vicinity of 0J cm to about 1.0 cm. For many purposes, it is believed that an advantageous cavity size range has a width from about 2.5 cm to about 5.0 cm and a length from about 5.0 cm to about 12.0 cm. For such a size range, a preferred thickness of the base 24 is from about 0J cm to about 0J5 cm.
One or more embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, a variety of package shapes, mounting features, lead layouts, and the like may be present. Accordingly, other embodiments are within the scope of the following claims.

Claims

CLAIMS 1. A package (20) for housing one or more semiconductor devices (22A; 22B), comprising: a copper alloy base (24) formed of an alloy having a fully annealed tensile strength in excess of 40 ksi (276 MPa) at 20° C; and a stainless steel (34) ring brazed atop the base with a brazing material having a melting point in excess of 700°C, the combination of the ring and the base at least partially defining a cavity (60) for containing the semiconductor device, which cavity has a length and a width each in excess of 2.5 cm.
2. The package (20) of claim 1 wherein the ring (34) is the unitary combination of first and second pairs of sidewalls (40C; 40D; 40A; 40B) arrayed as a rectangle and wherein each sidewall (40C; 40D) of the first pair includes at least one aperture (66; 68) for accommodating leads (62; 64) for electrical communication between the device and the exterior of the cavity.
3. The package (20) of claim 1 wherein the leads (62; 64) are glass sealed (70) within said at least one aperture (66; 68).
4. The package (20) of claim 1 wherein the base (24) has: a thermal conductivity of between about 230 W/m/° K and about 350 W/m/° K at 20° C; and a coefficient of linear thermal expansion of between about 15 x 10"6/° K and about 20 x 10N° K at 20° C.
5. The package (20) of any of claims 1-4 wherein the cavity (60) has a length of from about 5 cm to about 12 cm and a width from about 2.5 cm to about 5 cm.
6. The package (20) of any of claims 1-4 further comprising a lid (50) welded to the ring (34)to hermetically seal the cavity (60).
7. The package (20) of any of claims 1 -4 wherein the brazing material consists essentially of a silver/copper alloy.
8. The package (20) of any of claims 1-4 wherein the base (24) is formed of an alloy selected from C 19400 and C 19700.
9. A method for packaging a large semiconductor device (22A; 22B) so as to avoid package distortion, comprising: providing a copper alloy base (24); providing a steel ring (34) having an interior with a length and a width each in excess of 2.5 cm; providing a plurality of through holes (66; 68) in the ring; placing a plurality of conductors (62; 64) through associated ones of the through holes; securing the conductors to the ring by associated glass seals; and brazing the ring (34) atop the base (24) with a brazing material having a melting point in excess of 700°C so that the base and ring interior at least partially define a cavity (60) dimensioned to receive said large semiconductor device.
10. The method of claim 9 wherein the securing step occurs prior to the brazing step and the brazing material has a melting point below 900° C.
11. The method of claim 10 wherein the brazing material is a silver/copper alloy with less than 5% other alloying elements.
12. The method of claim 9 wherein the brazing step occurs prior to the securing step and the brazing material has a melting point in excess of 900° C.
13. The method of claim 12 wherein the brazing material is a gold/copper alloy with less than 10% other alloying elements.
14. The method of any of claims 9-13 further comprising: securing said large semiconductor device (22A; 22B) to the base within the ring interior; forming electrical connections (84) between said large semiconductor device and said plurality of conductors; and securing a lid (50) atop the ring (34) so as to encapsulate said large semiconductor device within a package interior.
15. The method of claim 14 wherein the step of securing the lid (50) comprises seam sealing the lid to the ring (34).
16. The method of claim 9 wherein the step of providing a copper alloy base (24) comprises providing such base having a fully annealed tensile strength of at least 40 ksi (276 MPa).
17. The method of claim 9 wherein the step of providing a copper alloy base (24) comprises providing such base having a fully annealed tensile strength at least equal to a fully annealed tensile strength of C 19400 copper alloy and providing such base having a thermal conductivity at least equal to a thermal conductivity of C 19400 copper alloy.
18. The method of claim 9 wherein the step of providing a copper alloy base (24) comprises providing such base having a thickness of from about 0J cm to about 0J5 cm and a fully annealed yield strength at least 50% greater than fully annealed yield strength of C 10200 copper.
19. A package (20) for housing one or more semiconductor devices (22A; 22B), comprising: a copper alloy base (24) formed of an alloy having a fully annealed yield strength at least 50% higher than a fully annealed yield strength of C 10200 copper, a coefficient of linear thermal expansion of between about 15 x 10"6/° K and about 20 x 10 "6/° K, and a thermal conductivity of at least 230 W/m/° K at 20° C; and a stainless steel ring (34) brazed atop the base with a brazing material having a melting point in excess of 700°C, the combination of the ring and the base at least partially defining a cavity for containing the semiconductor device, which cavity has a length and a width each in excess of 2.5 cm.
PCT/US2000/014821 1999-05-28 2000-05-25 Package for high power microelectronics WO2000074453A1 (en)

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US09/322,855 1999-05-28

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4563541A (en) * 1983-01-07 1986-01-07 L.C.C.-C.I.C.E.-Compagnie Europeenne De Composants Electroniques Package providing high heat dissipation, in particular for microelectronics
US5700724A (en) * 1994-08-02 1997-12-23 Philips Electronic North America Corporation Hermetically sealed package for a high power hybrid circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4563541A (en) * 1983-01-07 1986-01-07 L.C.C.-C.I.C.E.-Compagnie Europeenne De Composants Electroniques Package providing high heat dissipation, in particular for microelectronics
US5700724A (en) * 1994-08-02 1997-12-23 Philips Electronic North America Corporation Hermetically sealed package for a high power hybrid circuit

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