WO2000074068A1 - Method and apparatus for providing an embedded flash-eeprom technology - Google Patents

Method and apparatus for providing an embedded flash-eeprom technology Download PDF

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Publication number
WO2000074068A1
WO2000074068A1 PCT/US2000/040050 US0040050W WO0074068A1 WO 2000074068 A1 WO2000074068 A1 WO 2000074068A1 US 0040050 W US0040050 W US 0040050W WO 0074068 A1 WO0074068 A1 WO 0074068A1
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Prior art keywords
oxide
gate
floating gate
split
flash memory
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PCT/US2000/040050
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French (fr)
Inventor
James A. Cunningham
Richard A. Blanchard
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Koninklijke Philips Electronics N.V.
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Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to JP2001500280A priority Critical patent/JP2003500867A/en
Priority to DE60023247T priority patent/DE60023247T2/en
Priority to AU48607/00A priority patent/AU4860700A/en
Priority to EP00930854A priority patent/EP1105880B1/en
Publication of WO2000074068A1 publication Critical patent/WO2000074068A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/964—Roughened surface

Definitions

  • the present invention is generally directed to semiconductor memories, and more particularly, to the development of memory cells which can be easily integrated with high performance logic technologies.
  • State of the Art Those skilled in the art appreciate the desirability of embedding memory technology such as dynamic random access memories (DRAMs), static random access memories (SRAMs), read-only memories (ROMs), electrically erasable programmable read-only memories (EEPROMs), and flash EEPROMs into high performance logic technologies.
  • DRAMs dynamic random access memories
  • SRAMs static random access memories
  • ROMs read-only memories
  • EEPROMs electrically erasable programmable read-only memories
  • flash EEPROMs flash erasable programmable read-only memories
  • EEPROM technology is typically implemented using one of four basic cell types: (1) the one transistor stacked-gate flash EEPROM cell; (2) the one and one half transistor split-gate flash EEPROM cell; (3) the double-gate two transistor EEPROM cell; and (4) cells which use edges for control or select gates.
  • flash memory cells which form self-aligned trenches at the edge of a partially formed stack-gate structure.
  • Figure 1A shows a typical one transistor stacked-gate flash EEPROM cell.
  • Stacked-gate flash EEPROM cells are available from Intel Corp. and Advanced Micro Devices Corp. (e.g. , the Intel E28F016SA 16Mbit flash memory and the AMD AM29F016 16Mbit flash memory), having basic cell sizes of approximately 6 and 7 times the minimum feature size (f) squared (i.e., f 2 ), respectively.
  • these cells possess a very complex source-drain region which requires as many as four ion implants.
  • These submicron cells are subject to punch through, premature breakdown at the drain, and various read disturb problems.
  • the cells are susceptible to over erase, which can lead to a permanently turned-on device. These cells are also difficult to downward scale, because high voltages are required for the erase and program functions.
  • Erasure is performed by taking an extended source diffused region to a high positive value to pull electrons from the floating gate by Fowler-Nordheim (FN) tunneling to make the floating gate more positive.
  • the erase function is performed by lowering the floating gate threshold voltage V ⁇ , while programming is accomplished by applying high voltage to the drain and to the control gate formed with a second polysilicon layer (i.e. , poly 2) to inject hot electrons from a channel near the drain onto the floating gate to raise the threshold voltage. That is, programming is achieved using hot electron injection by applying high voltage to the control gate.
  • the high voltage (e.g. , approximately 12 volts) requires inclusion of separate high voltage transistors.
  • the exemplary Figure 1 cell involves using two levels of polysilicon.
  • Typical products use a NOR configuration, where each cell is configured with a bit line (BL) connection to the drain, a poly 2 control line (CL) or word line (WL), and a diffused source line (SL).
  • BL bit line
  • CL poly 2 control line
  • WL word line
  • SL diffused source line
  • the high voltages required for this device require building separate high voltage transistors which may have longer distances between the source of drain diffusion (i.e. , longer L eff ) and thicker gate oxides, thereby adding to the overall size of a memory device implemented with these cells.
  • a one and one-half transistor split-gate flash EEPROM avoids the over erase problem described with respect to the stacked-gate flash EEPROM cell, but is a larger cell size than the stacked gate.
  • a typical cell area can be on the order of approximately lOf 2 .
  • Lower n+ source regions may be created in the substrate by etching the oxide in an STI region down to the substrate. The poly 2 layer and a resist mask are used to protect other shallow trench isolation (STI) regions during etching.
  • STI shallow trench isolation
  • a double-gate two transistor EEPROM cell is shown in Figure 1C, and includes a separate select transistor to permit erasure of individual cells.
  • Such a cell is, for example, available from Atmel in its AT17C128 128k serial EEPROM, which has a cell area of approximately 11 f for 1.0 micron rules. The cell is relatively large and is not used in flash EEPROMs.
  • Figure ID illustrates an exemplary cell which uses polysilicon edges for control of select gates. For example, exemplary versions of this cell use closely spaced polysilicon edges for voltage coupling.
  • the cells are smaller than the cells discussed previously, they are very complex as reflected, for example, in the Sandisk 35 bit triple-polysilicon flash EEPROM, which is approximately 5? in cell area using 0.6 micron rules. Because of their complexity, they are unsuited to integration in high performance logic technology.
  • Figure IE shows an exemplary flash memory cell described in a document entitled "A 0.24 ⁇ m 2 Well Process with 0.18 ⁇ m Width Isolation and 3-D Interpoly Dielectric Films for 1-Gb Flash Memories", by Takashi Kobayashi et al, 1997 IEDM, page 275. Again, the process of producing such a cell is complex, and impractical for integration into high performance logic technology.
  • CMOS complementary metal oxide semiconductor
  • the applications for such an integrated technology include software updates, storing identification codes, system reconfiguration in the field, look-up tables, manufacturing codes, non- volatile data storage, smart cards which use flash embedded memory, prototyping, and various programmable logic devices and field programmable gate arrays.
  • submicron stacked gate EEPROM devices which yield devices that can be programmed at low voltages.
  • the properties are: (1) thin tunneling oxides (e.g., in a range of approximately 60 angstroms (A)-lO ⁇ A); (2) heavily-doped shallow n+ junctions with boron halo implants, giving abrupt junctions; and (3) a negative substrate bias.
  • exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split-gate cell structure.
  • An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.
  • exemplary embodiments are directed to a split-gate flash memory cell comprising: a tunnel oxide formed by oxidation of a textured monocrystalline substrate; a first floating gate electrode formed over said tunneling oxide; a gate oxide, separate from the tunneling oxide, formed on a non-textured portion of said monocrystalline substrate; and a second control electrode formed over said first floating gate electrode and said gate oxide.
  • An exemplary flash- EEPROM cell implemented in accordance with exemplary embodiments of the present invention is straightforward to integrate into high performance logic processes.
  • the cell is free from the over erase problem of one transistor stacked-gate flash EEPROM cells, and can more easily be downward scaled.
  • the cell can be programmed and erased at lower voltages, thereby eliminating process complexity associated with accommodating high on- chip voltages.
  • Figures 1A-1E illustrate exemplary conventional EEPROM cells
  • Figures 2A-2I illustrate an exemplary process flow for implementing a flash EEPROM cell in accordance with the present invention
  • Figures 3A-3C illustrate exemplary erase, program and read functions of a flash EEPROM cell in accordance with the present invention
  • Figure 4 illustrates an exemplary cell layout in accordance with the present invention.
  • Figures 2A-2I illustrate an exemplary process flow for producing a self- aligned, textured-substrate tunneling-oxide under a floating gate, and a standard oxide-nitride-oxide (ONO) dielectric over the floating gate for a high coupling ratio in accordance with exemplary embodiments of the present invention.
  • a first polysilicon layer 202 is deposited on a single crystal (i.e. , monocrystalline) silicon substrate 200.
  • the first polysilicon layer i.e. , poly 1 layer
  • the first polysilicon layer is oxidized into the substrate to form an oxidation layer 204 of, for example, approximately 30 ⁇ A, or any thickness suitable for forming an acceptable textured surface as shown in Figure 2C.
  • Figure 2C illustrates a stripping of the oxidation layer 204, resulting in the formation of a textured (i.e., rough) surface 206 on the single crystal silicon substrate 200.
  • a tunnel oxide layer 208 is grown on the textured surface 206.
  • the tunnel oxide layer is grown with a depth of, for example, approximately 60 to 100 A, and will ultimately have the floating gate formed over it.
  • Figure 2E illustrates the depositing and formation of an oxide-nitride-oxide (ONO) dielectric layer 210 after first depositing a new first polysilicon layer 212 (poly 1 layer).
  • the ONO layer 210 is deposited in known fashion, and can, for example, have a thickness of approximately 100-150 A.
  • the ONO layer 210 will constitute an interpoly dielectric formed between the poly 1 layer 212 and a later formed poly 2 layer.
  • a photoresist layer is deposited on the interpoly ONO 210 and is used to form a photoresist mask 214.
  • the photoresist mask 214 is used to perform a photoresist etch into the substrate (e.g.
  • the etch into the substrate is sufficient to remove unmasked portions of the textured surface 206.
  • the textured surface is removed in portions of the substrate to permit a regular gate oxide to be grown thereon. As such, a self-aligning process is used to ensure that the textured surface 206 is retained only beneath the remaining portions of the poly 1 layer 212.
  • Figure 2G the photoresist mask 214 has been removed and a gate oxide has been grown on exposed surfaces of the substrate and poly 1.
  • a sacrificial oxide may be formed and stripped prior to gate oxide formation as is known in the art.
  • Figure 2G illustrates a regrowth of a gate oxide 216 with a thickness of, for example, approximately 100 A.
  • a second polysilicon layer 218 i.e., poly 2 layer
  • Figure 21 shows the formation of a control gate from the poly 2 layer 218 with a stepped configuration relative to the remaining portion of the poly 1 layer 212 that constitutes the floating gate of the cell structure.
  • the control gate is formed by etching the poly 2 layer 212 using a technique similar to that described above with respect to the etching of the poly 1 layer to form the floating gate.
  • the right hand edges of the floating gate and the control gate can be aligned using a self-aligned etching procedure (i.e. , whereby the edges of the poly 2 and poly 1 layers are etched together). Afterwards, a reoxidation process can be used to grow an oxide layer 220 over the exposed surfaces of the control gate and floating gate.
  • a relatively tall gate edge on a source side of the cell i.e.
  • a flash EEPROM cell configured using a process such as that described with respect to Figure 2 can take into account the various conditions described by Bude regarding structural properties of submicron gate EEPROM devices; i.e. , use of thin tunneling oxides, heavily doped shallow n+ junctions with boron halo implants, and negative substrate bias.
  • the substrate bias can be facilitated by using a triple well process, such as a p-well in a deep n-well on a p-substrate.
  • conventional n-well on p-type material can be used for construction of the logic circuits.
  • the bias on the p-well, wnere the flash cells are constructed can be applied using on-chip voltage generation circuits, or the voltage can be supplied externally.
  • a device produced using the Figure 2 process can include erase, program and read functions that are implemented in a manner as illustrated with respect to Figures 3A-3C respectively.
  • the flash EEPROM cell is a 3.3 volt design, and all voltages used for the erase, program and read functions can be generated on-chip without high voltage transistors.
  • Figure 3 A an erase function is illustrated for a flash EEPROM cell produced using the process described with respect to Figure 2.
  • Boron halo implants 301 and 303 are formed in source and drain regions, respectively.
  • Figure 3 A illustrates heavily -doped shallow n+ junctions 302 and 304 in a p-well of substrate 300 for the source and drain portions of the cell. These regions are formed in similar fashion to the well known LDD process but with a higher dose implant. Somewhat deeper, more conductive, heavily doped regions 306 and 308 are also formed as part of the source and drain regions.
  • the source drain regions can be formed together with use of a triple well process.
  • the substrate can be negatively biased, with the p-type well being formed in a deep n-well on a p-type substrate, thereby constituting the triple well process which facilitates substrate biasing.
  • a voltage supply contact V s for the source, V d for the drain, V CG for the control gate, and V B for the substrate biasing are also provided.
  • the erase function is implemented by floating V s , placing V CG at ground, supplying a voltage pulse of, for example, 5 volts to the drain (i.e. , V d ) and placing V B at ground.
  • the threshold voltage V ⁇ at the floating gate drops below approximately 1 volt.
  • V ⁇ is relatively low.
  • the floating gate potential is about 1.0 volts (electrons depleted), which is too low to cause significant linkage by the Fowler- Nordheim process.
  • the electric field should be sufficiently high that the Fowler-Nordheim conduction is operative.
  • the actual erase time can be on the order of 5 to 10 times longer because the drain extension area under the floating gate is less than the total floating gate area, in exemplary embodiments.
  • a value of a 3 volt shift is by way of example only
  • n+ extensions shown in Figure 3 A can be formed prior to spacer formation using, for example, a phosphorus or arsenic implant of approximately 5xl0 14 atoms/cm 2 and using a drive-in/activation step with RTA such that a junction depth is approximately 0.1 to 0.2 ⁇ m. This yields an exemplary doping concentration of mid 10 19 atoms/cm 3 range. Some diffusion underlap of the floating gate is used to accomplish the erase function.
  • the values used for the various voltages of the Figure 3A erase function can be modified as desired.
  • the erase function can be performed at lower V d values by, for example, using a thinner tunneling oxide.
  • Figure 3B illustrates an exemplary program function wherein an increased threshold voltage on a floating gate electrode is caused by channel initiated secondary electrons.
  • a device configured and produced in accordance with exemplary embodiments of the present invention can be programmed using relatively low voltages.
  • the electric field should be low enough that the Fowler-Nordheim conduction mechanism is non-operative.
  • Silicon dioxide leakage current densities are, for example, on the order of 10 "15 A/cm 2 .
  • the threshold voltage at the floating gate V ⁇ of an n-channel transistor with a channel doping concentration of about 2xlO ⁇ atoms/cm 3 which is a value suitable for technologies in the 0.25 to 0.5 micron range is given by:
  • V ⁇ M s-Q F /Co+2 ⁇ F +[2 € s 6 0 qN A (2 ⁇ F +V BG )]' / VC 0 +V FG + ⁇ q/C 0
  • ⁇ MS is the metal-silicon work function
  • Q F is the fixed charge
  • ⁇ F is the Fermi potential
  • Co is the capacitance
  • e s is the dielectric constant for silicon
  • e 0 is the permitivity of free space
  • V BG is the back gate
  • V FG is the voltage left on the field gate after programming
  • ⁇ is the boron threshold-adjust implant dose
  • q is the charge on the electron.
  • V ⁇ is sufficiently high that the transistor will not turn on.
  • Programming can be done with a back gate bias, but the target threshold voltage is without that bias because the read condition is also without the bias. This lowers the charge on the floating gate, which must be held over a long time.
  • the V ⁇ target can be lower, of course, making the charge on the floating gate even lower.
  • Various other conditions can be specified for scaled technologies, as will be apparent to those skilled in the art.
  • the relatively high doping concentration in the channel, near the surface can be the accumulation of several possible boron implants including the p-well, punch through and threshold adjust.
  • Known halo implant processes can be used to produce the halo implants, and thereby improve punch through and other properties.
  • Figure 3C shows exemplary voltages associated with a read function. Hot electron reliability problems are avoided by using a low V D during the read operation. Exemplary voltages are as follows: V s and V B are at 0 volts and V CG is approximately 3.3 volts, V D is approximately 1-2 volts. A low V ⁇ constitutes an on condition representing a " 1 " and a high V ⁇ constitutes an off condition constituting a "0" condition.
  • Exemplary embodiments of a flash EEPROM cell configured as discussed with respect to Figures 3A-3C and produced using a process as described with respect to Figure 2 can be readily integrated into conventional high performance logic processes. For example, at the 0.25 micron level, it is common in conventional high performance logic technologies to first form shallow trench isolation regions using a silicon nitride layer that serves as a chemical mechanical polish (CMP) stop after filing with SiO 2 The wells can then be formed using high voltage ion implantation. The floating gates are then formed as disclosed in Figure 2.
  • the second polysilicon layer i.e., poly 2 serves as gate electrodes for the logic transistors.
  • the poly 2 layer can be formed as a polycide, or a salicide process can be used.
  • Self aligned contacts can be formed using appropriate dielectric spacers as is known by those skilled in the art.
  • the logic transistors can be formed as lightly doped drains (LDDs) with spacers. Extensions for the flash transistors can be doped at a higher level using appropriate masking an ion implantation steps.
  • LDDs lightly doped drains
  • Figure 4 is an exemplary layout of a split gate, double poly structure suitable for the novel textured substrate EEPROM cell shown in Figures 2 and 3.
  • the cell area is about 8 to lOf 2 depending on alignment tolerances.
  • n+ source line 401 Shown is n+ source line 401, floating gate 402, word line poly 2 403, self align tungsten plug contacts 404, bit line 405, STI regions 406, and drain contact 407. Not shown are their dielectrics and details of the n+ doped regions, which will be apparent to those skilled in the art.

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Abstract

Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide (208) in a manner which reduces tunneling barrier height (202), and requires minimum perturbation to conventional high performance logic technologies, without compromising logic function performance.

Description

METHOD AND APPARATUS FOR PROVIDING AN EMBEDDED FLASH-EEPROM TECHNOLOGY Related Applications:
The present application relates to a co-pending application filed concurrently herewith, entitled: METHOD AND APPARATUS FOR
PRODUCING A SINGLE POLYSILICON FLASH EEPROM (Attorney Docket No. 029300-437), the disclosure of which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION Field of the Invention
The present invention is generally directed to semiconductor memories, and more particularly, to the development of memory cells which can be easily integrated with high performance logic technologies. State of the Art Those skilled in the art appreciate the desirability of embedding memory technology such as dynamic random access memories (DRAMs), static random access memories (SRAMs), read-only memories (ROMs), electrically erasable programmable read-only memories (EEPROMs), and flash EEPROMs into high performance logic technologies. However, at present, only technologies such as SRAM and ROM are straightforward to integrate into high performance logic technologies. Technologies, such as EEPROM and DRAM technologies are highly dedicated to their specific needs, and are very complex, rendering them unsuitable for straightforward, easy integration into high performance logic technologies. For example, EEPROM technology is typically implemented using one of four basic cell types: (1) the one transistor stacked-gate flash EEPROM cell; (2) the one and one half transistor split-gate flash EEPROM cell; (3) the double-gate two transistor EEPROM cell; and (4) cells which use edges for control or select gates. There have also been proposals regarding flash memory cells which form self-aligned trenches at the edge of a partially formed stack-gate structure. However, each of these technologies suffers drawbacks which inhibits their straightforward, easy integration into high performance logic technologies. Figure 1A shows a typical one transistor stacked-gate flash EEPROM cell.
Stacked-gate flash EEPROM cells are available from Intel Corp. and Advanced Micro Devices Corp. (e.g. , the Intel E28F016SA 16Mbit flash memory and the AMD AM29F016 16Mbit flash memory), having basic cell sizes of approximately 6 and 7 times the minimum feature size (f) squared (i.e., f2), respectively. However, these cells possess a very complex source-drain region which requires as many as four ion implants. These submicron cells are subject to punch through, premature breakdown at the drain, and various read disturb problems. In addition, the cells are susceptible to over erase, which can lead to a permanently turned-on device. These cells are also difficult to downward scale, because high voltages are required for the erase and program functions. Erasure is performed by taking an extended source diffused region to a high positive value to pull electrons from the floating gate by Fowler-Nordheim (FN) tunneling to make the floating gate more positive. The erase function is performed by lowering the floating gate threshold voltage Vτ, while programming is accomplished by applying high voltage to the drain and to the control gate formed with a second polysilicon layer (i.e. , poly 2) to inject hot electrons from a channel near the drain onto the floating gate to raise the threshold voltage. That is, programming is achieved using hot electron injection by applying high voltage to the control gate. The high voltage (e.g. , approximately 12 volts) requires inclusion of separate high voltage transistors.
The exemplary Figure 1 cell involves using two levels of polysilicon. Typical products use a NOR configuration, where each cell is configured with a bit line (BL) connection to the drain, a poly 2 control line (CL) or word line (WL), and a diffused source line (SL). The high voltages required for this device require building separate high voltage transistors which may have longer distances between the source of drain diffusion (i.e. , longer Leff) and thicker gate oxides, thereby adding to the overall size of a memory device implemented with these cells.
A one and one-half transistor split-gate flash EEPROM, as shown in Figure IB, avoids the over erase problem described with respect to the stacked-gate flash EEPROM cell, but is a larger cell size than the stacked gate. For a split-gate cell using modern shallow trench isolation (STI), an n+ source line self-aligned to the poly, self-aligned tungsten plug contacts, and conservative poly 1 to poly 2 alignment tolerances, a typical cell area can be on the order of approximately lOf2. Lower n+ source regions may be created in the substrate by etching the oxide in an STI region down to the substrate. The poly 2 layer and a resist mask are used to protect other shallow trench isolation (STI) regions during etching. A double-gate two transistor EEPROM cell is shown in Figure 1C, and includes a separate select transistor to permit erasure of individual cells. Such a cell is, for example, available from Atmel in its AT17C128 128k serial EEPROM, which has a cell area of approximately 11 f for 1.0 micron rules. The cell is relatively large and is not used in flash EEPROMs. Figure ID illustrates an exemplary cell which uses polysilicon edges for control of select gates. For example, exemplary versions of this cell use closely spaced polysilicon edges for voltage coupling. Although the cells are smaller than the cells discussed previously, they are very complex as reflected, for example, in the Sandisk 35 bit triple-polysilicon flash EEPROM, which is approximately 5? in cell area using 0.6 micron rules. Because of their complexity, they are unsuited to integration in high performance logic technology.
Figure IE shows an exemplary flash memory cell described in a document entitled "A 0.24 μm 2 Well Process with 0.18μm Width Isolation and 3-D Interpoly Dielectric Films for 1-Gb Flash Memories", by Takashi Kobayashi et al, 1997 IEDM, page 275. Again, the process of producing such a cell is complex, and impractical for integration into high performance logic technology.
Because numerous applications exist for integrating flash EEPROM technology with high performance complementary metal oxide semiconductor (CMOS) logic devices (e.g., microprocessors), the development of such a technology would be highly desirable. For example, the applications for such an integrated technology include software updates, storing identification codes, system reconfiguration in the field, look-up tables, manufacturing codes, non- volatile data storage, smart cards which use flash embedded memory, prototyping, and various programmable logic devices and field programmable gate arrays.
Known process technologies do not lend themselves to easy integration of commodity flash EEPROM cells with logic devices, such as high performance CMOS devices. That is, known processes, including processes as described in a document entitled "EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Rating" , by J.D. Bude et al., 1995 IEDM, page 989 and in a document entitled "Secondary Electron Flash-A High Performance Low Power Flash Technology for 0.25 μm and Below, by J.D. Bude et al., 1997, IEDM page 279, do not sufficiently simplify the flash EEPROM cell and fabrication process to permit straightforward integration into conventional high performance logic processes. In these documents, structural properties of submicron stacked gate EEPROM devices are disclosed which yield devices that can be programmed at low voltages. The properties are: (1) thin tunneling oxides (e.g., in a range of approximately 60 angstroms (A)-lOθA); (2) heavily-doped shallow n+ junctions with boron halo implants, giving abrupt junctions; and (3) a negative substrate bias.
In addition to process compatibility problems, scaling EEPROM technology into the 0.25 μm regime and below, as is used on typical high performance logic processes, has not been realized. Those skilled in the art have suggested that scaling EEPROM devices is subject to physical limits which may inhibit a reduction in cell size (see, for example, "Nonvolatile Semiconductor Memory Technology", by William D. Brown and Joe E. Brewer, IEEE, Press 1998, page 130). Given the wide applicability of flash EEPROM technology, it would be desirable to avoid the process compatibility problems associated with integrating typical cell designs with conventional logic devices by developing a cell which can be easily integrated into high performance logic processes.
SUMMARY OF THE INVENTION Accordingly, exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split-gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.
Generally speaking, exemplary embodiments are directed to a split-gate flash memory cell comprising: a tunnel oxide formed by oxidation of a textured monocrystalline substrate; a first floating gate electrode formed over said tunneling oxide; a gate oxide, separate from the tunneling oxide, formed on a non-textured portion of said monocrystalline substrate; and a second control electrode formed over said first floating gate electrode and said gate oxide. An exemplary flash- EEPROM cell implemented in accordance with exemplary embodiments of the present invention is straightforward to integrate into high performance logic processes. In addition, the cell is free from the over erase problem of one transistor stacked-gate flash EEPROM cells, and can more easily be downward scaled. In addition, the cell can be programmed and erased at lower voltages, thereby eliminating process complexity associated with accommodating high on- chip voltages.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects and features of the present invention will become more apparent from the following detailed description of preferred embodiments when read in connection with the accompanying drawings, wherein: Figures 1A-1E illustrate exemplary conventional EEPROM cells; Figures 2A-2I illustrate an exemplary process flow for implementing a flash EEPROM cell in accordance with the present invention; Figures 3A-3C illustrate exemplary erase, program and read functions of a flash EEPROM cell in accordance with the present invention; and
Figure 4 illustrates an exemplary cell layout in accordance with the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figures 2A-2I, illustrate an exemplary process flow for producing a self- aligned, textured-substrate tunneling-oxide under a floating gate, and a standard oxide-nitride-oxide (ONO) dielectric over the floating gate for a high coupling ratio in accordance with exemplary embodiments of the present invention. In Figure 2A, a first polysilicon layer 202 is deposited on a single crystal (i.e. , monocrystalline) silicon substrate 200. In an exemplary embodiment, the first polysilicon layer (i.e. , poly 1 layer) is approximately 12θA in thickness, or any thickness on the order of 12θA.
In Figure 2B, the first polysilicon layer is oxidized into the substrate to form an oxidation layer 204 of, for example, approximately 30θA, or any thickness suitable for forming an acceptable textured surface as shown in Figure 2C. Figure 2C illustrates a stripping of the oxidation layer 204, resulting in the formation of a textured (i.e., rough) surface 206 on the single crystal silicon substrate 200. In Figure 2D, a tunnel oxide layer 208 is grown on the textured surface 206. In exemplary embodiments, the tunnel oxide layer is grown with a depth of, for example, approximately 60 to 100 A, and will ultimately have the floating gate formed over it.
Figure 2E illustrates the depositing and formation of an oxide-nitride-oxide (ONO) dielectric layer 210 after first depositing a new first polysilicon layer 212 (poly 1 layer). The ONO layer 210 is deposited in known fashion, and can, for example, have a thickness of approximately 100-150 A. The ONO layer 210 will constitute an interpoly dielectric formed between the poly 1 layer 212 and a later formed poly 2 layer. In Figure 2F, a photoresist layer is deposited on the interpoly ONO 210 and is used to form a photoresist mask 214. The photoresist mask 214 is used to perform a photoresist etch into the substrate (e.g. , to a depth on the order of approximately 10-100 A into the substrate). The etch into the substrate is sufficient to remove unmasked portions of the textured surface 206. The textured surface is removed in portions of the substrate to permit a regular gate oxide to be grown thereon. As such, a self-aligning process is used to ensure that the textured surface 206 is retained only beneath the remaining portions of the poly 1 layer 212.
In Figure 2G, the photoresist mask 214 has been removed and a gate oxide has been grown on exposed surfaces of the substrate and poly 1. A sacrificial oxide may be formed and stripped prior to gate oxide formation as is known in the art. Figure 2G illustrates a regrowth of a gate oxide 216 with a thickness of, for example, approximately 100 A. In Figure 2H, a second polysilicon layer 218 (i.e., poly 2 layer) has been deposited over the Figure 2G structure. Figure 21 shows the formation of a control gate from the poly 2 layer 218 with a stepped configuration relative to the remaining portion of the poly 1 layer 212 that constitutes the floating gate of the cell structure. The control gate is formed by etching the poly 2 layer 212 using a technique similar to that described above with respect to the etching of the poly 1 layer to form the floating gate. The right hand edges of the floating gate and the control gate (as viewed in Figure 21) can be aligned using a self-aligned etching procedure (i.e. , whereby the edges of the poly 2 and poly 1 layers are etched together). Afterwards, a reoxidation process can be used to grow an oxide layer 220 over the exposed surfaces of the control gate and floating gate. Those skilled in the art will appreciate that a relatively tall gate edge on a source side of the cell (i.e. , shown to the left in Figure 21) facilitates the use of a self-aligned contact there, because the thickness of the edge spacer will increase. Referring to Figure 3, a flash EEPROM cell configured using a process such as that described with respect to Figure 2 can take into account the various conditions described by Bude regarding structural properties of submicron gate EEPROM devices; i.e. , use of thin tunneling oxides, heavily doped shallow n+ junctions with boron halo implants, and negative substrate bias. The substrate bias can be facilitated by using a triple well process, such as a p-well in a deep n-well on a p-substrate. As such, conventional n-well on p-type material can be used for construction of the logic circuits. The bias on the p-well, wnere the flash cells are constructed, can be applied using on-chip voltage generation circuits, or the voltage can be supplied externally. As such, a device produced using the Figure 2 process can include erase, program and read functions that are implemented in a manner as illustrated with respect to Figures 3A-3C respectively.
Referring to Figures 3A-3C, relatively low programming voltages can be used in conjunction with the device produced using the Figure 2 process. In Figures 3A-3C, the flash EEPROM cell is a 3.3 volt design, and all voltages used for the erase, program and read functions can be generated on-chip without high voltage transistors.
More particularly, referring to Figure 3 A, an erase function is illustrated for a flash EEPROM cell produced using the process described with respect to Figure 2. Boron halo implants 301 and 303 are formed in source and drain regions, respectively. Figure 3 A illustrates heavily -doped shallow n+ junctions 302 and 304 in a p-well of substrate 300 for the source and drain portions of the cell. These regions are formed in similar fashion to the well known LDD process but with a higher dose implant. Somewhat deeper, more conductive, heavily doped regions 306 and 308 are also formed as part of the source and drain regions.
The source drain regions can be formed together with use of a triple well process. The substrate can be negatively biased, with the p-type well being formed in a deep n-well on a p-type substrate, thereby constituting the triple well process which facilitates substrate biasing. A voltage supply contact Vs for the source, Vd for the drain, VCG for the control gate, and VB for the substrate biasing are also provided.
The erase function is implemented by floating Vs, placing VCG at ground, supplying a voltage pulse of, for example, 5 volts to the drain (i.e. , Vd) and placing VB at ground. The threshold voltage Vτ at the floating gate drops below approximately 1 volt. Thus, for an erase condition, Vτ is relatively low. For example, for a target Vτ of 0.5 volts, the floating gate potential is about 1.0 volts (electrons depleted), which is too low to cause significant linkage by the Fowler- Nordheim process. To erase the floating gate in a relatively short time, the electric field should be sufficiently high that the Fowler-Nordheim conduction is operative.
In exemplary embodiments, for 100 A silicon dioxide dielectrics, 5 volt pulses on the drain produce currents on the order of 10"4 to 10"5 A/cm2. (This assumes that for the n+ poly-n+ substrate structure which accomplishes the tunneling, the flat band voltage which reduces the electric field across the oxide is negligible). Because the threshold shift is given roughly by Q/C0, where Q is the charge transfer to the floating gate and C0 is the floating gate-to-substrate capacity per unit area, substituting Jt for Q where J is the current density and t is time and seconds, for a three volt shift, only about 0.01 seconds are required. The actual erase time can be on the order of 5 to 10 times longer because the drain extension area under the floating gate is less than the total floating gate area, in exemplary embodiments. Those skilled in the art will appreciate that a value of a 3 volt shift is by way of example only
The n+ extensions shown in Figure 3 A can be formed prior to spacer formation using, for example, a phosphorus or arsenic implant of approximately 5xl014 atoms/cm2 and using a drive-in/activation step with RTA such that a junction depth is approximately 0.1 to 0.2 μm. This yields an exemplary doping concentration of mid 1019 atoms/cm3 range. Some diffusion underlap of the floating gate is used to accomplish the erase function.
Those skilled in the art will appreciate that the values used for the various voltages of the Figure 3A erase function, as well as those discussed with respect to Figures 3B and 3C, can be modified as desired. For example, the erase function can be performed at lower Vd values by, for example, using a thinner tunneling oxide.
Figure 3B illustrates an exemplary program function wherein an increased threshold voltage on a floating gate electrode is caused by channel initiated secondary electrons. As mentioned above, a device configured and produced in accordance with exemplary embodiments of the present invention can be programmed using relatively low voltages. For a charge to be retained over a long period of time (e.g. , many years) on the floating gate upon programming, given an exemplary Vτ of approximately 2 to 4 volts (measured at VB=0), the electric field should be low enough that the Fowler-Nordheim conduction mechanism is non-operative. Silicon dioxide leakage current densities are, for example, on the order of 10"15 A/cm2. This is achieved by forming dielectrics at an upper range of resistivities, by using dry O2 oxidation recipes known to those skilled in the art. Because the Fowler-Nordheim currents are much lower when leakage flows from negatively charged electrodes, the programmed Vτ is held by a negatively charged floating gate. The program state can be maintained a long period of time when the voltage-to-substrate electric field residing at the floating gate is small. The threshold voltage at the floating gate Vτ of an n-channel transistor with a channel doping concentration of about 2xlOπ atoms/cm3, which is a value suitable for technologies in the 0.25 to 0.5 micron range is given by:
Vτ = Ms-QF/Co+2ΦF+[2€s60qNA(2ΦF+VBG)]'/VC0+VFG+Σq/C0
where ΦMS is the metal-silicon work function, QF is the fixed charge, ΦF is the Fermi potential, Co is the capacitance, es is the dielectric constant for silicon, e0 is the permitivity of free space, VBG is the back gate, VFG is the voltage left on the field gate after programming, Σ is the boron threshold-adjust implant dose, and q is the charge on the electron.
For the programmed state, the Vτ is sufficiently high that the transistor will not turn on. Substituting VT=3V (measured at VBG=0), a low value for QF VBG=0V, using 100 A for the gate oxide thickness, other exemplary values appropriate for NA=2X1017 atoms/cm3, and ∑q=0, the voltage on the VFG is about -0.5 V (electrons accumulated). This would yield a low electric field of 0.5X106V/cm where almost no tunneling currents would flow. Programming can be done with a back gate bias, but the target threshold voltage is without that bias because the read condition is also without the bias. This lowers the charge on the floating gate, which must be held over a long time. The Vτ target can be lower, of course, making the charge on the floating gate even lower. Various other conditions can be specified for scaled technologies, as will be apparent to those skilled in the art. The relatively high doping concentration in the channel, near the surface can be the accumulation of several possible boron implants including the p-well, punch through and threshold adjust. Known halo implant processes can be used to produce the halo implants, and thereby improve punch through and other properties.
Figure 3C shows exemplary voltages associated with a read function. Hot electron reliability problems are avoided by using a low VD during the read operation. Exemplary voltages are as follows: Vs and VB are at 0 volts and VCG is approximately 3.3 volts, VD is approximately 1-2 volts. A low Vτ constitutes an on condition representing a " 1 " and a high Vτ constitutes an off condition constituting a "0" condition.
Exemplary embodiments of a flash EEPROM cell configured as discussed with respect to Figures 3A-3C and produced using a process as described with respect to Figure 2 can be readily integrated into conventional high performance logic processes. For example, at the 0.25 micron level, it is common in conventional high performance logic technologies to first form shallow trench isolation regions using a silicon nitride layer that serves as a chemical mechanical polish (CMP) stop after filing with SiO2 The wells can then be formed using high voltage ion implantation. The floating gates are then formed as disclosed in Figure 2. The second polysilicon layer (i.e., poly 2) serves as gate electrodes for the logic transistors. The poly 2 layer can be formed as a polycide, or a salicide process can be used. Self aligned contacts can be formed using appropriate dielectric spacers as is known by those skilled in the art. The logic transistors can be formed as lightly doped drains (LDDs) with spacers. Extensions for the flash transistors can be doped at a higher level using appropriate masking an ion implantation steps. Thus, those skilled in the art will appreciate that a process for forming the Figure 3 cell can be easily integrated with a high performance logic process. Figure 4 is an exemplary layout of a split gate, double poly structure suitable for the novel textured substrate EEPROM cell shown in Figures 2 and 3. The cell area is about 8 to lOf2 depending on alignment tolerances. Shown is n+ source line 401, floating gate 402, word line poly 2 403, self align tungsten plug contacts 404, bit line 405, STI regions 406, and drain contact 407. Not shown are their dielectrics and details of the n+ doped regions, which will be apparent to those skilled in the art.
Those skilled in the art will appreciate that the embodiments and processes described above are by way of example only. For example, additional steps can be added to the process discussed with respect to Figure 2 and or additional features and/or voltages can be used in conjunction with the device illustrated in Figures 3A-3C.
It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restricted. The scope of the invention is indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range and equivalence thereof are intended to be embraced therein.

Claims

WHAT IS CLAIMED IS:
1. A split-gate flash memory cell comprising: a tunnel oxide formed by oxidation of a textured monocrystalline substrate; a first floating gate electrode formed over said tunneling oxide; a gate oxide, separate from the tunneling oxide, formed on a non- textured portion of said monocrystalline substrate; and a second control electrode formed over said first floating gate electrode and said gate oxide.
2. The split-gate flash memory cell according to claim 1, wherein said first floating gate electrode is self-aligned with said tunneling oxide.
3. The split-gate flash memory cell according to claim 1, wherein an oxide-nitride-oxide dielectric is formed between said first floating gate electrode and said second control electrode.
4. The split-gate flash memory cell according to claim 1, wherein said first floating gate electrode has a thickness of approximately 12θA.
5. The split-gate flash memory cell according to claim 1, wherein said tunneling oxide has a thickness of approximately 60 to lOOA.
6. The split-gate flash memory cell according to claim 3, wherein said oxide-nitride-oxide layer has a thickness of approximately 100 to 15θA.
7. The split-gate flash memory cell according to claim 1, wherein said first floating gate electrode and said second control electrode are formed of polycrystalline silicon.
8. A method for producing a split-gate flash memory cell comprising the steps of: forming a tunnel oxide by oxidation of a textured monocrystalline substrate; forming a first floating gate electrode over said tunneling oxide; forming a gate oxide, separate from the tunneling oxide, on a non-textured portion of said monocrystalline substrate; and forming a second control electrode over said first floating gate electrode and said gate oxide.
9. The method according to claim 8, comprising: self-aligning said first floating gate with said tunneling oxide.
10. The method according to claim 8, comprising: forming an oxide-nitride-oxide dielectric between said first floating gate electrode and said second control electrode.
11. The method according to claim 8, wherein said first floating gate has a thickness of approximately 12θA.
12. The method according to claim 8, wherein said tunneling oxide has a thickness of approximately 60 to lOOA.
13. The method according to claim 11, wherein said oxide-nitride-oxide layer has a thickness of approximately 100 to 15θA.
14. The method according to claim 8, wherein said first floating gate and said second control electrode are formed of polycrystalline silicon.
15. A method for programming a split-gate flash memory cell comprising the steps of: increasing a threshold voltage on a first floating gate electrode by channel initiated secondary electrons, said first floating gate electrode being formed over a tunnel oxide that has been oxidized on a textured monocrystalline substrate; and applying a voltage to a second control electrode formed over said first floating gate electrode and a gate oxide, said gate oxide being separate from the tunneling oxide and being formed on a non-textured portion of said monocrystalline substrate.
PCT/US2000/040050 1999-05-28 2000-05-24 Method and apparatus for providing an embedded flash-eeprom technology WO2000074068A1 (en)

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AU48607/00A AU4860700A (en) 1999-05-28 2000-05-24 Method and apparatus for providing an embedded flash-eeprom technology
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1096572B8 (en) * 1999-10-25 2009-09-02 Imec Electrically programmable and erasable memory device and method of operating same
EP1172861A3 (en) * 2000-07-12 2003-11-05 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same
US6420232B1 (en) * 2000-11-14 2002-07-16 Silicon-Based Technology Corp. Methods of fabricating a scalable split-gate flash memory device having embedded triple-sides erase cathodes
JP4058232B2 (en) 2000-11-29 2008-03-05 株式会社ルネサステクノロジ Semiconductor device and IC card
TW490814B (en) * 2001-04-04 2002-06-11 Macronix Int Co Ltd Manufacturing method of memory device with floating gate
JP2003086716A (en) 2001-09-11 2003-03-20 Matsushita Electric Ind Co Ltd Non-volatile semiconductor memory and manufacturing method thereof
CN1324691C (en) * 2001-10-22 2007-07-04 旺宏电子股份有限公司 Erasing method of P type channel silicon nitride ROM
US6690601B2 (en) * 2002-03-29 2004-02-10 Macronix International Co., Ltd. Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same
US6801453B2 (en) * 2002-04-02 2004-10-05 Macronix International Co., Ltd. Method and apparatus of a read scheme for non-volatile memory
US6660588B1 (en) 2002-09-16 2003-12-09 Advanced Micro Devices, Inc. High density floating gate flash memory and fabrication processes therefor
US6815764B2 (en) * 2003-03-17 2004-11-09 Samsung Electronics Co., Ltd. Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same
DE10357777B3 (en) * 2003-09-30 2005-05-12 Infineon Technologies Ag Method for operating a memory cell array
KR100558004B1 (en) * 2003-10-22 2006-03-06 삼성전자주식회사 Programing method of a non-volatile memory device including a charge storage layer between a gate electrode and a semiconductor substrate
EP1759421A1 (en) * 2004-06-15 2007-03-07 Koninklijke Philips Electronics N.V. Non-volatile memory with erase gate on isolation zones
US6984563B1 (en) 2004-07-01 2006-01-10 Fasl Llc Floating gate semiconductor component and method of manufacture
US7242051B2 (en) * 2005-05-20 2007-07-10 Silicon Storage Technology, Inc. Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
US7796442B2 (en) * 2007-04-02 2010-09-14 Denso Corporation Nonvolatile semiconductor memory device and method of erasing and programming the same
US7687856B2 (en) * 2007-05-10 2010-03-30 Texas Instruments Incorporated Body bias to facilitate transistor matching
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US8455923B2 (en) 2010-07-01 2013-06-04 Aplus Flash Technology, Inc. Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
US8829588B2 (en) * 2011-07-26 2014-09-09 Synopsys, Inc. NVM bitcell with a replacement control gate and additional floating gate
US20140124880A1 (en) 2012-11-06 2014-05-08 International Business Machines Corporation Magnetoresistive random access memory
US8750033B2 (en) 2012-11-06 2014-06-10 International Business Machines Corporation Reading a cross point cell array
US9466731B2 (en) 2014-08-12 2016-10-11 Empire Technology Development Llc Dual channel memory
US20190207034A1 (en) * 2017-12-28 2019-07-04 Microchip Technology Incorporated Split-Gate Memory Cell With Field-Enhanced Source Junctions, And Method Of Forming Such Memory Cell
US10861550B1 (en) * 2019-06-06 2020-12-08 Microchip Technology Incorporated Flash memory cell adapted for low voltage and/or non-volatile performance

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4830974A (en) * 1988-01-11 1989-05-16 Atmel Corporation EPROM fabrication process
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US5416738A (en) * 1994-05-27 1995-05-16 Alliance Semiconductor Corporation Single transistor flash EPROM cell and method of operation
US5482879A (en) * 1995-05-12 1996-01-09 United Microelectronics Corporation Process of fabricating split gate flash memory cell

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5677867A (en) * 1991-06-12 1997-10-14 Hazani; Emanuel Memory with isolatable expandable bit lines
US4877751A (en) 1988-03-11 1989-10-31 National Semiconductor Corporation Method of forming an N+ poly-to- N+ silicon capacitor structure utilizing a deep phosphorous implant
US5095344A (en) * 1988-06-08 1992-03-10 Eliyahou Harari Highly compact eprom and flash eeprom devices
IT1232354B (en) 1989-09-04 1992-01-28 Sgs Thomson Microelectronics PROCEDURE FOR THE CREATION OF EEPROM MEMORY CELLS AT A SINGLE LEVEL OF POLYSILICIO AND THIN OXIDE USING DIFFERENTIAL OXIDATION.
US5202850A (en) * 1990-01-22 1993-04-13 Silicon Storage Technology, Inc. Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate
US5346842A (en) 1992-02-04 1994-09-13 National Semiconductor Corporation Method of making alternate metal/source virtual ground flash EPROM cell array
US5544103A (en) * 1992-03-03 1996-08-06 Xicor, Inc. Compact page-erasable eeprom non-volatile memory
US5429966A (en) * 1993-07-22 1995-07-04 National Science Council Method of fabricating a textured tunnel oxide for EEPROM applications
KR0124629B1 (en) * 1994-02-23 1997-12-11 문정환 Eeprom semiconductor memory device
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
US6043124A (en) * 1998-03-13 2000-03-28 Texas Instruments-Acer Incorporated Method for forming high density nonvolatile memories with high capacitive-coupling ratio
US6184087B1 (en) * 1998-03-23 2001-02-06 Shye-Lin Wu Method for forming high density nonvolatile memories with high capacitive-coupling ratio
US6207505B1 (en) * 1998-03-23 2001-03-27 Texas Instruments-Acer Incorporated Method for forming high density nonvolatile memories with high capacitive-coupling ratio
US6204124B1 (en) * 1998-03-23 2001-03-20 Texas Instruments - Acer Incorporated Method for forming high density nonvolatile memories with high capacitive-coupling ratio
US6177703B1 (en) * 1999-05-28 2001-01-23 Vlsi Technology, Inc. Method and apparatus for producing a single polysilicon flash EEPROM having a select transistor and a floating gate transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US4830974A (en) * 1988-01-11 1989-05-16 Atmel Corporation EPROM fabrication process
US5416738A (en) * 1994-05-27 1995-05-16 Alliance Semiconductor Corporation Single transistor flash EPROM cell and method of operation
US5482879A (en) * 1995-05-12 1996-01-09 United Microelectronics Corporation Process of fabricating split gate flash memory cell

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1105880A4 *

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