WO2000058969A1 - Device with embedded flash and eeprom memories - Google Patents
Device with embedded flash and eeprom memories Download PDFInfo
- Publication number
- WO2000058969A1 WO2000058969A1 PCT/US2000/004898 US0004898W WO0058969A1 WO 2000058969 A1 WO2000058969 A1 WO 2000058969A1 US 0004898 W US0004898 W US 0004898W WO 0058969 A1 WO0058969 A1 WO 0058969A1
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- WIPO (PCT)
- Prior art keywords
- die
- eeprom
- memories
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- well
- Prior art date
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- 239000007924 injection Substances 0.000 claims description 21
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 description 24
- 230000004888 barrier function Effects 0.000 description 14
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- 238000005516 engineering process Methods 0.000 description 12
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- 238000002955 isolation Methods 0.000 description 5
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
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- 229910052785 arsenic Inorganic materials 0.000 description 1
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- ZOXJGFHDIHLPTG-IGMARMGPSA-N boron-11 atom Chemical compound [11B] ZOXJGFHDIHLPTG-IGMARMGPSA-N 0.000 description 1
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- 239000011574 phosphorus Substances 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- flash memories and EEPROMs are closely related, in many instances flash memories are preferred because their smaller cell size means that they can be made more economically. However, flash memories and EEPROMs often have very similar cell attributes.
- a basic FLASH memory may be created and an additional FLASH portion may be adapted to emulate EEPROM memory.
- the software is stored in a boot block which is also a FLASH memory.
- the system needs a first FLASH memory to act as FLASH, a second FLASH memory to store the software needed to emulate EEPROM operation and additional FLASH memory to actually implement the FLASH-like capabilities. This results in a very costly structure whose operation is complicated. Thus, this technique has also not met with consideration administrative acceptance.
- Figure 8 is a greatly enlarged, top plan view showing the layout of a semiconductor implementation of the embodiment shown in Figure 6;
- Figure 9 is a partial three dimensional view of the cell shown in Figure 8.
- control gate 27 extends across the active region 18 which is bordered by the drain 16 of the sense transistor 12 and the source 13 of the select transistor 14.
- the select gate 11 also extends parallel to and underneath the control gate 27, bordering the edge of the control gate 27 and the region 15a.
- the control gate 27 may be non-self-aligned to the select gate 11 and the sense gate 12.
- the floating gate 22 is also situated in isolation under the control gate 27, over the active region 18.
- the relationship of the sense transistor 12 and select transistor 14 is illustrated in Figure 3.
- the floating gate 22 forms portions of the transistor which has a drain 16 and a source 13.
- the select gate 11 forms the other portion of the transistor between the source 13 and the drain 16.
- the sense transistor 12 includes a channel 25a while the select transistor 14 includes a channel 24.
- the control gate forms the plate of the capacitor whose channel is 15a.
- the select gate 14, the floating gate 22 and the control gate 27 form the gates of a transistor with a source 13 and drain 16.
- the channels 25a and 24 are P-type semiconductor material and are part of a P-well 28.
- the P-well 28 in turn is formed in an N-well 29.
- the N-well 29 is formed in a P-type substrate 38.
- substrate electrons are generated by forward biasing the source 13 which is separated from the sense transistor 12 channel 25a by the select transistor channel 24 and the region 15a under the capacitor 50. Some of the substrate electrons 60 diffuse through the region underneath the channel 24 to the channel region 25a underneath the sense transistor 12.
- the P-well potential is the voltage 70 applied to the P-well 28. Since the P-well 28 is embedded in an N-well 29, and the N-well is set at a voltage 72 approximately Vss or higher, the P-well potential Vp can be negative, typically negative one to negative two volts. Moreover, it is usually less than the effective oxide barrier height to avoid any potential disturb problem.
- the drain 16 is preferably not biased to a voltage higher than the P-well 28 to such an extent that gate induced drain leakage (GIDL) becomes a problem. With current technologies, this means that the drain 16 bias cannot be higher than the P-well 28 bias by about one volt. In addition, if the drain 16 bias significantly exceeds the P-well 28 bias, hot hole trapping may occur in the select gate oxide 52 due to the lateral junction field acceleration.
- GIDL gate induced drain leakage
- the ability to apply a positive voltage to the P-well arises because the P-well 28 is embedded in an N-well 29.
- the P-well voltage is preferably equal to or less than N-well potential to avoid P-well/N-well forward biasing.
- applying a positive voltage of Vcc or higher to the P-well, N-well and the drain 16 can eliminate hot hole trapping induced by GIDL while allowing the drain 16 voltage to be raised to Vcc or higher.
- Electrons tunnel to the drain region 16 (drain erase).
- the tunneling current depends on the voltage from the floating gate 22 to the drain 16. In one embodiment of the invention, byte erasing is used.
- the unselected word line voltage may be set to zero volts (Vss). The voltage drop across the depletion region then is less than the effective oxide barrier height.
- Cell 210 programming is achieved by Fowler-Nordheim tunneling of electrons from the floating gate 228 to the channel region 256b and the drain 238.
- the selected bit line 236b is forced to a high voltage "H" (higher than Vcc) of about 5 volts, for example.
- the unselected bit lines are maintained at Vss. If the N-well and P-well are maintained at Vcc and Vss respectively, the electric field across the junction between the drain 238 and the P-well 244 may be reduced.
- the voltage across the capacitor 257 is the difference between the floating gate 228 potential on the one hand and the drain 238 and the P-well 244 potentials. When the difference exceeds 8 to 10 volts, sufficient tunneling current is generated and the floating gate 228 can be erased to a negative potential in the time frame of a few milliseconds to a few seconds, depending on the tunneling oxide 56 thickness.
- the cells in the array may be formed using conventional process technologies such as a double poly, single metal CMOS process.
- CMOS process CMOS process.
- the illustrative parameters set forth herein contemplate a .25 ⁇ m or lower feature size with Vcc potentials of 1.8 volts. As the technology permits lowering voltages and smaller feature sizes, the parameters herein would scale accordingly.
- the FLASH and EEPROM memories are created with substantially the same process steps. By reducing the number of additional process steps, the cost of the overall device may be dramatically effected. In some embodiments, exactly the same process steps may be utilized for both memories so that no extra steps and no extra masking steps are necessary to obtain both memories on a single die.
- N-well implant is done, for example, with phosphorus 31 with a typical dose of 1 to 1.5 x 10 13 atoms per square centimeter and an energy of 160 to lOOKev.
- the N-well implant is driven using a high temperature step which may typically be 6 to 12 hours at 1 125 to 1150° C.
- the N-wells 29 and 246 are then counterdoped with a P-well implant. Typical dosages for the P-well implant
- 1 ⁇ could be 1.5 to 2.5 x 10 atoms per square centimeter with an energy of 30Kev to 180Kev using a species such as boron 11.
- the N-wells 29 and 246 and P-wells 28 and 244 are then driven, typically 6 to 10 hours at 1125 to 1 150°C. This sets the wells to the desired doping concentrations and depths.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU37078/00A AU3707800A (en) | 1999-03-26 | 2000-02-25 | Device with embedded flash and eeprom memories |
EP00915879A EP1181692A1 (en) | 1999-03-26 | 2000-02-25 | Device with embedded flash and eeprom memories |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/277,347 | 1999-03-26 | ||
US09/277,347 US6252799B1 (en) | 1997-04-11 | 1999-03-26 | Device with embedded flash and EEPROM memories |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000058969A1 true WO2000058969A1 (en) | 2000-10-05 |
Family
ID=23060470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/004898 WO2000058969A1 (en) | 1999-03-26 | 2000-02-25 | Device with embedded flash and eeprom memories |
Country Status (7)
Country | Link |
---|---|
US (2) | US6252799B1 (en) |
EP (1) | EP1181692A1 (en) |
JP (1) | JP2000277637A (en) |
CN (1) | CN1345448A (en) |
AU (1) | AU3707800A (en) |
TW (1) | TW454194B (en) |
WO (1) | WO2000058969A1 (en) |
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US7035147B2 (en) | 2003-06-17 | 2006-04-25 | Macronix International Co., Ltd. | Overerase protection of memory cells for nonvolatile memory |
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US7573745B2 (en) | 2002-07-10 | 2009-08-11 | Saifun Semiconductors Ltd. | Multiple use memory chip |
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- 2000-02-25 WO PCT/US2000/004898 patent/WO2000058969A1/en not_active Application Discontinuation
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US7031196B2 (en) | 2002-03-29 | 2006-04-18 | Macronix International Co., Ltd. | Nonvolatile semiconductor memory and operating method of the memory |
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US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
US9030877B2 (en) | 2007-08-30 | 2015-05-12 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
CN102012791A (en) * | 2010-10-15 | 2011-04-13 | 中国人民解放军国防科学技术大学 | Flash based PCIE (peripheral component interface express) board for data storage |
Also Published As
Publication number | Publication date |
---|---|
EP1181692A1 (en) | 2002-02-27 |
US6326265B1 (en) | 2001-12-04 |
JP2000277637A (en) | 2000-10-06 |
US6252799B1 (en) | 2001-06-26 |
AU3707800A (en) | 2000-10-16 |
TW454194B (en) | 2001-09-11 |
CN1345448A (en) | 2002-04-17 |
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