WO2000057472A1 - Procede pour relier un fil de connexion a un contact de connexion d'un circuit integre - Google Patents

Procede pour relier un fil de connexion a un contact de connexion d'un circuit integre Download PDF

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Publication number
WO2000057472A1
WO2000057472A1 PCT/DE2000/000907 DE0000907W WO0057472A1 WO 2000057472 A1 WO2000057472 A1 WO 2000057472A1 DE 0000907 W DE0000907 W DE 0000907W WO 0057472 A1 WO0057472 A1 WO 0057472A1
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WIPO (PCT)
Prior art keywords
connection
contact
solder layer
integrated circuit
solder
Prior art date
Application number
PCT/DE2000/000907
Other languages
German (de)
English (en)
Inventor
Holger HÜBNER
Vaidyanathan Kripesh
Original Assignee
Infineon Technologies Ag
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Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2000057472A1 publication Critical patent/WO2000057472A1/fr

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    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the invention relates to a method for connecting a connection end of a connecting wire to a connection contact of an electrically active region of an integrated circuit.
  • the invention further relates to an integrated circuit which has a connection contact and a connection wire provided on the connection contact.
  • connection contacts are made by means of wire bonding.
  • connection contacts designed as bond surfaces are provided, the surface of which has aluminum, in particular the metal alloy AlSiCu. Gold wires can be welded directly onto this surface, which are attached to the housing side of a leadframe on the other side.
  • the erfmdungsgeordere method for connecting a terminal ⁇ end of a lead wire to a terminal contact of an electrical active region of an integrated circuit has the following steps:
  • the invention is based on the basic idea of providing a very thin solder layer, which in particular has tin or indium.
  • the tin forms a copper 3-tin connection with adjacent copper from the area of the connection contact as soon as the area of the connection end of the connection wire and the surface of the connection contact is heated.
  • the heating is preferably carried out at a temperature which is below the melting temperature of the copper 3-Zmnverbmdung.
  • the copper 3-Zmnverbmdung which creates the connection between the lead wire and the terminal contact, arises from a diffusion-controlled process.
  • the solder layer is designed so thin that its thickness is less than 10 ⁇ m.
  • the solder layer is preferably kept thinner than 5 .mu.m, although thicknesses of less than a micrometer (for example 200 nm) are also conceivable. Thereby, the impact of the effect is vermie ⁇ , according to which in the first formation of a copper-tin-3- phase, this attaches to the copper of the pad and acts as a diffusion barrier. In the case of thicker solder layers, this diffusion barrier counteracts the further formation of copper-3-Zmn phase.
  • the chip as a whole no longer needs to be heated to a temperature of a few hundred degrees Celsius, which leads to undesired oxidation in the case of copper contacts.
  • a copper-6-Zmn-5 phase can also be formed in a first step until a connection with a predetermined basic strength is obtained between the connection contact and the connection wire.
  • the entire integrated circuit is stored in such a way that the final stable copper 3-Zmn phase is formed essentially completely in the solder layer.
  • the diffusion process is preferably carried out in such a way that the temperature is above the melting point of tin or indium. Accordingly, a preferred temperature amounts on heating rms of the area of the terminal end of the lead wire and / or the surface of the terminal fitting 25 ⁇ ° C and preferably up to 300 ° C. If a tin-indium mixture is used, a temperature of approximately 120 ° C. to 130 ° C. can also be used.
  • the step of heating the area of the connection end of the connection wire and the surface of the connection contact can be provided in a first sub-step as brief local heating, the heating to a temperature above the melting point of the low-melting components te or the solder of the solder-metal connection.
  • a first sub-step superimposed on the overall integrated circuit ⁇ circle - preferably with exclusion of oxygen - in egg ⁇ ner temperature at which the first sub-step erge- Bende copper-6-Zmn-5-m, a final phase stable copper fer-3-Zmn phase.
  • the step of long-term heating can take place both at a temperature below the melting point of the low-melting component and - in the event that the entire solder-metal compound has not yet been converted in the first step - at a higher temperature.
  • Long-term deposition can also take place at elevated temperature or in an oxygen-free environment.
  • a holding pressure force can be exerted on the connecting wire provided in the area of the connecting contact by means of a press ram.
  • the method according to the invention can also be carried out under a non-oxidizing atmosphere, for example with argon or nitrogen, in which case the integrated circuit can subsequently be packed in a housing or in a casting compound.
  • a non-oxidizing atmosphere for example with argon or nitrogen
  • the solder is not heated above its melting point and then cooled until it solidifies and then forms the connection between the connecting contact and the connecting wire. Rather, the solder is heated above its melting point and held at this temperature until the solder layer solidifies due to a chemical reaction with the material of the connection contact and / or with the material of the connection wire. Intermetallic phases such as copper-3-Zmn are formed.
  • the invention can also be implemented with solder layers in which metals such as indium, gallium, mercury, lead, etc. are provided.
  • soldering process according to the invention is also referred to as the "process of isothermal solidification" or "SOLID process".
  • the cheap and tried-and-tested wire bonding process can therefore also be used advantageously for copper metallization on semiconductor substrates.
  • the machines previously used can still be used. In this case, only need the bonding wires and the terminal contacts with a low melting solder such as Sn ⁇ layer or be coated with a Sn / In alloy.
  • wires can be processed from materials that are suitable for the SOLID process, such as from copper, gold,
  • Silver, nickel and other alloys for example, from the metals mentioned above and other metals.
  • a coating with suitable adhesive layers can be provided on the bonding wire or on the connection contact.
  • suitable adhesive layers for aluminum wires are, for example, titanium, titanium nitride and copper, each preferably 50 nm.
  • the solder layer is preferably applied as the last layer.
  • the connecting wire can have the shape of a flat strip, a bead-shaped thickening being formed at one end connected to a connecting contact, which is appropriate for a connecting wire with a circular cross-section.
  • the step of providing a thin solder layer can also be carried out with the aid of electroless deposition of solder material.
  • solder material can also be made with a dipping process or with laminating or plating.
  • inventive shaped Verfanren doing a Ausgestal ⁇ be emphasized tung gens of the terminal end of the lead wire with the surface of the terminal fitting is provided the step of melting of at ⁇ circuit forming a bead of melted in before the step of Caribbeanbrm-. In this case, the hot melt bead is connected to the connection contact.
  • the thermal energy stored in the molten pearl causes the diffusion process of the metal from the connecting wire m the solder layer.
  • FIG. 1 shows a cross section through a first integrated circuit at the time of its completion
  • FIG. 2 shows a cross section through a second integrated circuit at the time of its completion
  • FIG. 3 shows a cross section through a third integrated circuit according to the invention at the time of its completion.
  • FIG. 1 shows a cross section through a region of an integrated circuit 1 according to the invention at the time of its completion.
  • the integrated circuit 1 has a semiconductor substrate 2 with this view, not shown, of electrically active areas which can be accessed via a connection contact 3.
  • the connection contact 3 is made of a copper alloy.
  • a passivation layer 4 made of a polymer is applied to the top of the semiconductor substrate 2.
  • the passivation layer 4 covers the semiconductor substrate 2 as well as the connection contact 3, wherein in the area of the top of the 3 is a circuit terminal Passivi mecanics Mrs merit 5 is recessed, by which the top side of the terminal fitting 3 is access ⁇ Lich.
  • a solder layer 6 made of a Zmn alloy is applied, which has a thickness of approximately 2 ⁇ m.
  • connection end 8 placed on the solder layer 6, the connection end 8 on its side facing away from the solder layer 6 from a
  • Heating stamp 9 is applied.
  • the state shown in FIG. 1 relates to a point in time shortly before the solder layer 6 melts.
  • the procedure for completing the integrated circuit 1 is as follows.
  • the integrated circuit 1 with the semiconductor substrate 2 and the passivation layer 4 provided on the semiconductor substrate 2 is provided.
  • the passivation layer 4 in the area of the connection contact 3 is passivated the passivation layer window 5.
  • This step is also used for wire bonding and is carried out on the wave level with photolithography and dry erase technology.
  • An approximately 2 ⁇ m thick tin solder layer is then deposited on the connection contact 3 within the passivation layer window 5. This is advantageously done by electroless precipitation, in which the solder layer selectively only grows on the Cu surface of the connection contact 3 in the region of the open passivation layer window 5.
  • the electroless tin plating is a cold process, so that the Z n layer does not react with the material of the contact 3 during its deposition.
  • the connecting wire 7 consisting of gold or copper is then bonded onto the tinned connection contact 3 using conventional bonding machines. Here occurs at the Heating by the heating die 9 no welding of the surfaces of lead wire 7 and connection contact 3, but rather the lead wire 7 is connected to the terminal contact ⁇ 3 heartverlotet.
  • Figure 2 shows a cross section through a portion of a further integrated circuit 15, the m match its essential ingredients with the integrated circuit 1 via ⁇ .
  • the same components are therefore provided with the same reference numbers.
  • the integrated circuit 15 has a flat connecting strip 16 which has a metal strip 17 on its upper side and a solder layer 18 on its underside. In this case, it is no longer necessary to provide a separate solder layer on the connection contact 3 in order to connect the connection strip 16 to the connection contact 3.
  • the procedure is essentially the same as for the integrated circuit 1, the metal strip 17 first being provided with a solder layer 18 on its underside.
  • Wires with a round cross section can also be used as connecting wires, which are provided with a solder layer 18 on their outside. If a flat strip is used, as is represented by the connecting strip 16, it is sufficient to provide only the underside of the connecting strip 16 with a solder layer 18.
  • the coating can be carried out by dip-tinning, for example in that the metal strip 17, for example made of gold, passes through a bonding machine in a tinning bath before threading. Laminating or plating a thin layer of solder is also possible with bond tapes.
  • solder alloys with a low melting point can also be used, such as an Sn / In eutectic with a melting point of approximately 180 ° C.
  • SOLID soldering process comes into play, according to which the melting point of the connection resulting from the Zmn / indium and the copper is substantially higher than the temperature at which the heating stamp 9 acts on the solder layer 18. This has the advantage that the bonding can take place at a relatively low temperature, the temperature resistance of the bond point being considerably higher than is the case with conventional solder connections.
  • FIG. 3 shows an area of a further integrated circuit 25 in cross section.
  • the connecting end of the connecting wire 26 is heated in such a way that a liquid molten bead is formed there.
  • the wire section 27 With the wire section 27, the molten pearl 28 is placed on the solder layer 6 while it is still hot, whereupon a chemical reaction between the metallic material of the molten pearl 28 and the solder layer 6 takes place in a 6 m pitch.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un circuit intégré (1) comprenant un substrat à semi-conducteur (2), qui présente des zones électriquement actives auxquelles une tension électrique peut être appliquée par l'intermédiaire de contacts de connexion (3). Les contacts de connexion (3) comportent une couche de connexion en cuivre. Sur chaque contact de connexion (3), il est prévu un fil de connexion (7) et dans une zone située entre le fil de connexion (7) et le contact de connexion (3), il est prévu une couche de plomb de soudure (6) consistant principalement en un composé de métal de soudage.
PCT/DE2000/000907 1999-03-24 2000-03-24 Procede pour relier un fil de connexion a un contact de connexion d'un circuit integre WO2000057472A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19913368.9 1999-03-24
DE19913368 1999-03-24

Publications (1)

Publication Number Publication Date
WO2000057472A1 true WO2000057472A1 (fr) 2000-09-28

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Application Number Title Priority Date Filing Date
PCT/DE2000/000907 WO2000057472A1 (fr) 1999-03-24 2000-03-24 Procede pour relier un fil de connexion a un contact de connexion d'un circuit integre

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Country Link
WO (1) WO2000057472A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7911061B2 (en) 2007-06-25 2011-03-22 Infineon Technologies Ag Semiconductor device
ITTO20120374A1 (it) * 2012-04-27 2013-10-28 St Microelectronics Srl Struttura a semiconduttore con regioni conduttive a bassa temperatura di fusione e metodo per riparare una struttura a semiconduttore

Citations (7)

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Publication number Priority date Publication date Assignee Title
JPS6035552A (ja) * 1983-08-08 1985-02-23 Hitachi Ltd 半導体装置
US4651191A (en) * 1981-09-02 1987-03-17 Hitachi, Ltd. Semiconductor device and fabrication method thereof
JPS62120037A (ja) * 1985-11-20 1987-06-01 Furukawa Electric Co Ltd:The 半導体装置
JPS63283044A (ja) * 1987-05-14 1988-11-18 Nec Corp 半導体集積回路装置
JPH06196854A (ja) * 1992-12-22 1994-07-15 Yamaha Corp 着脱治具
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
JPH1116916A (ja) * 1997-06-26 1999-01-22 Tanaka Denshi Kogyo Kk バンプ電極形成方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651191A (en) * 1981-09-02 1987-03-17 Hitachi, Ltd. Semiconductor device and fabrication method thereof
JPS6035552A (ja) * 1983-08-08 1985-02-23 Hitachi Ltd 半導体装置
JPS62120037A (ja) * 1985-11-20 1987-06-01 Furukawa Electric Co Ltd:The 半導体装置
JPS63283044A (ja) * 1987-05-14 1988-11-18 Nec Corp 半導体集積回路装置
JPH06196854A (ja) * 1992-12-22 1994-07-15 Yamaha Corp 着脱治具
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
JPH1116916A (ja) * 1997-06-26 1999-01-22 Tanaka Denshi Kogyo Kk バンプ電極形成方法

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PATENT ABSTRACTS OF JAPAN vol. 009, no. 154 (E - 325) 28 June 1985 (1985-06-28) *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 338 (E - 553) 5 November 1987 (1987-11-05) *
PATENT ABSTRACTS OF JAPAN vol. 013, no. 110 (E - 728) 16 March 1989 (1989-03-16) *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 545 (E - 1617) 18 October 1994 (1994-10-18) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 04 30 April 1999 (1999-04-30) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7911061B2 (en) 2007-06-25 2011-03-22 Infineon Technologies Ag Semiconductor device
US8156643B2 (en) 2007-06-25 2012-04-17 Infineon Technologies Ag Semiconductor device
ITTO20120374A1 (it) * 2012-04-27 2013-10-28 St Microelectronics Srl Struttura a semiconduttore con regioni conduttive a bassa temperatura di fusione e metodo per riparare una struttura a semiconduttore
US9318313B2 (en) 2012-04-27 2016-04-19 Stmicroelectronics S.R.L. Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure

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