Connect public, paid and private patent data with Google Patents Public Datasets

Communications system and method with multilevel connection identification

Info

Publication number
WO2000029961A9
WO2000029961A9 PCT/US1999/026901 US9926901W WO2000029961A9 WO 2000029961 A9 WO2000029961 A9 WO 2000029961A9 US 9926901 W US9926901 W US 9926901W WO 2000029961 A9 WO2000029961 A9 WO 2000029961A9
Authority
WO
Grant status
Application
Patent type
Prior art keywords
functional
transfer
block
target
bus
Prior art date
Application number
PCT/US1999/026901
Other languages
French (fr)
Other versions
WO2000029961A1 (en )
Inventor
Drew Eric Wingard
Geert Paul Rosseel
Jay S Tomlinson
Lisa A Robinson
Original Assignee
Sonics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/40Bus networks
    • H04L12/403Bus networks with centralised control, e.g. polling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/66Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

A communication system (2000) is disclosed. One embodiment includes at least two functional blocks, wherein a first functional block (1002) communicates with a second functional block (1008) by establishing a connection, wherein the connection is a logical state in which data may pass between the first functional block (1002) and the second functional block (1008). Another embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.

Description

COMMUNICATIONS SYSTEM AND METHOD WITH MULTILEVEL CONNECTION IDENTIFICATION

FIELD OF THE INVENTION

The present invention relates to a communication system to couple computing sub-systems. BACKGROUND OF THE INVENTION

Electronic computing and communications systems continue to include greater numbers of features and to increase in complexity. At the same time, electronic computing and communications systems decrease in physical size and cost per function. Rapid advances in semiconductor technology such as four-layer deep-sub-micron complimentary metal-oxide semiconductor (CMOS) technology, have enabled true "system-on-a-chip" designs. These complex designs may incorporate, for example, one or more processor cores, a digital signal processing (DSP) core, several communications interfaces, and graphics support in application- specific logic. In some systems, one or several of these extremely complex chips must communicate with each other and with other system components. Significant new challenges arise in the integration, verification and testing of such systems because efficient communication must take place between sub-systems on a single complex chip as well as between chips on a system board. One benefit to having an efficient and flexible method for communication between sub-systems and chips is that system components can be reused in other systems with a minimum of redesign.

One challenge in the integration, verification and testing of modern electronic systems stems from the fact that modern electronic systems in many application areas have functionality, cost and form-factor requirements that mandate the sharing of resources, such as memory, among multiple functional blocks, where functional blocks can be any entity that interfaces to a communication system. In such systems, the functional blocks typically possess different performance characteristics and requirements, and the communications system and shared resources must simultaneously satisfy the total requirements. Key requirements of typical functional blocks are bandwidth and latency constraints that can vary over several orders of magnitude between functional blocks. In order to simultaneously satisfy constraints that vary so widely, communications systems must provide high degrees of predictability.

Traditional approaches to the design of communications systems for modern, complex computer systems have various strengths and weaknesses. An essential aspect of such approaches is the communications interface that various sub-systems present to one another. One approach is to define customized point- to-point interfaces between a sub-system and each peer with which it must communicate. This customized approach offers protocol simplicity, guaranteed performance, and isolation from dependencies on unrelated sub-systems. Customized interfaces, however, are by their nature inflexible. The addition of a new sub-system with a different interface requires design rework.

A second approach is to define a system using standardized interfaces. Many standardized interfaces are based on pre-established computer bus protocols. The use of computer buses allows flexibility in system design, since as many different functional blocks may be connected together as required by the system, as long as the bus has sufficient performance. It is also necessary to allocate access to the bus among various sub-systems. In the case of computer buses, resource allocation is typically referred to as arbitration.

One disadvantage of computer buses is that each sub-system or component connected to the bus is constrained to use the protocol of the bus. In some cases, this limits the performance of the sub-system. For example, a sub-system may be capable of handling multiple transaction streams simultaneously, but the bus protocol is not capable of fully supporting concurrent operations. In the case of a sub-system handling multiple transaction streams where each transaction stream has ordering constraints, it is necessary for the sub-system to identify each increment of data received or transmitted with a certain part of a certain data stream to distinguish between streams and to preserve order within a stream. This includes identifying a sub-system that is a source of a data transmission. Conventionally, such identification is limited to a non-configurable hardware identifier that is generated by a particular sub-system or component.

Current bus systems provide limited capability to preserve order in one transaction stream by supporting "split transactions" in which data from one transaction may be interleaved with data from another transaction in the same stream. In such a bus, data is tagged as belonging to one stream of data, so that it can be identified even if it arrives out of order. This requires the receiving subsystem to decode an arriving address to extract the identification information.

Current bus systems do not support true concurrency of operations for a sub-system that can process multiple streams of transactions over a single interconnect, such as a memory controller that handles access to a single dynamic random access memory (DRAM) for several clients of the DRAM. A DRAM controller may require information related to a source of an access request, a priority of an access request, ordering requirements, etc. Current communication systems do not provide for such information to be transmitted with data without placing an additional burden on the sub-system to adapt to the existing protocol.

In order for many sub-systems to operate in conventional systems using all of their capabilities, additional knowledge must be designed into the sub-systems to provide communication over existing communication systems. This makes subsystems more expensive and less flexible in the event the sub-system is later required to communicate with new sub-systems or components. Existing communication approaches thus do not meet the requirements of today's large, complex electronics systems. Therefore, it is desirable for a communications system and mechanism to allow sub-systems of a large, complex electronics system to inter-operate efficiently regardless of their varying performance characteristics and requirements.

SUMMARY OF THE INVENTION

One embodiment of the present invention includes a shared communications bus for providing flexible communication capability between electronic; subsystems. One embodiment includes a protocol that allows for identification of data transmissions at different levels of detail as required by a particular sub-system without additional knowledge being designed into the sub-system.

One embodiment of the invention includes several functional blocks, including at least one initiator functional block and one target functional block. Some initiator functional blocks may also function as target functional blocks. In one embodiment, the initiator functional block is coupled to an initiator interface module and the target functional block is coupled to a target interface module. The initiator functional block and the target functional block communicate to their respective interface modules and the interface modules communicate with each other. The initiator functional block communicates with the target functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the initiator functional block and the target functional block.

One embodiment also includes a bus configured to carry multiple signals, wherein the signals include a connection identifier signal that indicates a particular connection that a data transfer between an initiator functional block and a target functional block is part of. The connection identifier includes information about the connection, such as which functional block is the source of a transmission, a priority of a transfer request, and transfer ordering information. One embodiment also includes a thread identifier, which provides a subset of the information provided by the connection identifier. In one embodiment, the thread identifier is an identifier of local scope that identifies transfers between an interface module and a connected functional block, where in some embodiments, an interface module connects a functional block to a shared communications bus. The connection identifier is a an identifier of global scope that transfers information between interface modules or between functional blocks through their interface modules. Some functional blocks may require all the information provided by the connection identifier, while other functional blocks may require only the subset of information provided by the thread identifier. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram of one embodiment of a complex electronics system according to the present invention.

Figure 2 is an embodiment of a system module.

Figure 3 is an embodiment of a system module.

Figure 4 is an embodiment of a communications bus.

Figure 5 is a timing diagram showing pipelined write transfers.

Figure 6 is a timing diagram showing rejection of a first pipelined write transfer and a successful second write transfer

Figure 7 is a timing diagram showing interleaving of pipelined read and write transfers.

Figure 8 is a timing diagram showing interleaved connections to a single target.

Figure 9 is a timing diagram showing interleaved connections from a single initiator.

Figure 10 is a block diagram of one embodiment of part of a computer system.

Figure 11 is one embodiment of a communications bus.

Figure 12 is a block diagram of one embodiment of part of a computer system. DETAILED DESCRIPTION

The present invention is a communications system and method for allowing multiple functional blocks or sub-systems of a complex electronics system to communicate with each other through a shared communications resource, such as a shared communications bus. In one embodiment, a communications protocol allows multiple functional block on a single semiconductor device to communicate to each other. In another embodiment, the communications protocol may be used to allow multiple functional blocks on different semiconductor devices to communicate to each other through a shared off-chip communications resource, such as a bus.

In one embodiment, the present invention is a pipelined communications bus with separate command, address, and data wires. Alternative embodiments include a pipelined communications bus with multiplexed address, data, and control signals. The former embodiment offers higher performance and simpler control than the latter embodiment at the expense of extra wires. The former embodiment may be more appropriate for on-chip communications, where wires are relatively less expensive and performance requirements are usually higher. The latter embodiment offers higher per-wire transfer efficiency, because it shares the same wires among address and data transfers. The latter embodiment may be more appropriate for chip-to-chip communications between semiconductor devices, because package pins and board traces increase the per signal cost, while total required communications performance is usually lower.

Figure 1 is a block diagram of a complex electronics system 100. Shared communications bus 112 connects sub-systems 102, 104, 106, 108, and 110. Subsystems are typically functional blocks including a interface module for interfacing to a shared bus. Sub-systems may themselves include one or more functional blocks and may or may not include an integrated or physically separate interface module. In one embodiment, the sub-systems connected by communications bus 112 are separate integrated circuit chips. Sub-system 104 is an application specific integrated circuit (ASIC) which, as is known, is an integrated circuit designed to perform a particular function. Sub-system 106 is a dynamic random access memory (DRAM). Sub-system 108 is an erasable, programmable, read only memory (EPROM). Sub-system 110 is a field programmable gate array (FPGA). Sub-system 102 is a fully custom integrated circuit designed specifically to operate in system 100. Other embodiments may contain additional sub-systems of the same types as shown, or other types not shown. Other embodiments may also include fewer subsystems than the sub-systems shown in system 100. Integrated circuit 102 includes sub-systems 102A, 102B, 102C, 102D and 102E. ASIC 104 includes functional blocks 101A, 104B and 104C. FPGA 110 includes functional blocks 110A and HOB. A functional block may be a particular block of logic that performs a particular function. A functional block may also be a memory component on an integrated circuit.

System 100 is an example of a system that may consist of one or more integrated circuits or chips. A functional block may be a logic block on an integrated circuit such as, for example, functional block 102E, or a functional block may also be an integrated circuit such as fully custom integrated circuit 102 that implements a single logic function.

Shared communications bus 112 provides a shared communications bus between sub-systems of system 100. Shared communication bus 114 provides a shared communications bus between sub-systems or functional blocks on a single integrated circuit. Some of the functional blocks shown are connected to interface modules through which they send and receive signals to and from shared communications bus 112 or shared communications bus 114. Interconnect 115 is a local point-to-point interconnect for connecting interface modules to functional blocks.

Interface modules 120-127 are connected to various functional blocks as shown. In this embodiment, interface modules 120, 122, 123 and 124 are physically separated from their connected functional block (A, B, C, E and 102, respectively). Interface modules 121, and 125-128 are essentially part of their respective functional blocks or sub-systems. Some functional blocks, such as 102D, do not require a dedicated interface module. The arrangement of sub-systems, functional blocks and interface modules is flexible and is determined by the system designer. In one embodiment there are four fundamental types of functional blocks. The four fundamental types are initiator, target, bridge, and snooping blocks. A typical target is a memory device, a typical initiator is a central processing unit (CPU). Functional blocks all communicate with one another via shared communications bus 112 or shared communications bus 114 and the protocol of one embodiment. Initiator and target functional blocks may communicate a shared communications bus through interface modules. An initiator functional block may communicate with a shared communications bus through an initiator interface module and a target functional block may communicate with a shared communications bus through a target interface module.

An initiator interface module issues and receives read and write requests to and from functional blocks other than the one with which it is associated. In one embodiment, an initiator interface module is typically connected to a CPU, a digital signal processing (DSP) core, or a direct memory access (DMA) engine.

Figure 2 is a block diagram of an embodiment of an initiator interface module 800. Initiator interface module 800 includes clock generator 802, data flow block 806, arbitrator block 804, address /command decode block 808, configuration registers 810, and synchronizer 812. Initiator interface module 800 is connected to a shared communications bus 814 and to an initiator functional block 816. In one embodiment, shared communications bus 814 is a shared communications bus that connects sub-systems, as bus 112 does in Figure 1.

Clock generator 802 is used to perform clock division when initiator functional block 816 runs synchronously with respect to shared communications bus 814 but at a different frequencies. When initiator functional block 816 runs asynchronously with respect to communications bus 814, clock generator 802 is not used, but synchronizer 812 is used. Arbitrator block 804 performs arbitration for access to shared communications bus 814. In one embodiment, a multi-level arbitration scheme is used wherein arbitrator module 804 includes logic circuits that manage pre-allocated bandwidth aspects of first level arbitration and also logic that manages second level arbitration. Data flow block 806 includes data flow first-in first-out (FIFO) buffers between shared communications bus 814 and initiator functional block 816, in addition to control logic associated with managing a transaction between shared communications bus 814 and initiator functional block 816. The FIFO buffers stage both the address and data bits transferred between shared communications bus 814 and initiator functional block 816. In one embodiment, shared communications bus 814 implements a memory mapped protocol. Specific details of an underlying computer bus protocol are not significant to the invention, provided that the underlying computer bus protocol supports some operation concurrency. A preferred embodiment of a bus protocol for use with the present invention is one that supports retry transactions or split transactions, because these protocols provide a mechanism to deliver operation concurrency by interrupting a multi-cycle transaction to allow transfers belonging to other unrelated transactions to take place. These protocols allow for higher transfer efficiencies because independent transactions may use the bus while an initiator waits for a long latency target to return data that has been previously requested by an initiator.

Address /command decode block 808 decodes an address on shared communications bus 814 to determine if a write is to be performed to registers associated with initiator functional block 816. Address /command decode block 808 also decodes incoming commands. Configuration registers 810 store bits that determine the state of module 800, including bandwidth allocation and client address base. One register 810 stores an identification (ID) which is a set of bits uniquely identifying initiator functional block 816.

Figure 3 is a block diagram of an embodiment of a target interface module 900. Target interface module 900 is connected to shared communications bus 914 and to target functional block 918. Target interface module 900 includes clock generator 902, data flow block 906, address /command decode block 908, synchronizer 912, and state registers in state control block 916. Blocks of target interface module 900 that are named similarly to blocks of initiator module 800 function in substantially the same way as explained with respect to initiator block 800. State registers and state control block 916 include registers that store, for example, client address base and an identifier for target functional block 918.

In one embodiment, an initiator functional block such as initiator functional block 816 may also act as a target functional block in that it has the capability to respond to signals from other functional blocks or sub-systems as well as to initiate actions by sending signals to other functional blocks or sub-systems.

Figure 4 is a block diagram of a part of a computer system 1000 according to one embodiment. Figure 4 is useful in illustrating multilevel connection identification. System 1000 includes initiator functional block 1002, which is connected to initiator interface module 1004 by interconnect 1010. Initiator interface module 1004 is connected to target interface module 1006 by shared communications bus 1012. Target interface module 1006 is connected to target functional block 1008 by an interconnect 1010. Typically, shared communications bus 1012 is analogous to shared communications bus 112 of Figure 1 or to shared communications bus 114 of Figure 1. Interconnects 1010 are typically analogous to interconnect 115 of Figure 1 in that they connect functional blocks to interface modules and are point-to-point, rather than shared, interconnects. Interconnects 1010 are typically physically shorter than shared communications bus 1012 because of their local nature. As will be explained more fully below, system 1000 uses two different levels of connection identification depending upon the requirements of a particular functional block. "Global" connection identification information is sent on shared communications bus 1012, while "local" connection information, or thread identification information, is sent in interconnects 1010.

Figure 5 is a block diagram of one embodiment of a shared communications bus 1012. Shared communications bus 1012 is shown connected to entities A, B, C, D and E, which may be interface modules or functional blocks. Shared communications bus 1012 is composed of a set of wires. Data wires 230 provide direct, high efficiency transport of data traffic between functional blocks on shared communications bus 1012. In one embodiment, shared communications bus 1012 supports a bus protocol that is a framed, time division multiplexed, fully pipelined, fixed latency communication protocol using separate address, data and connection identification wires. The bus protocol supports fine grained interleaving of transfers to enable high operation concurrency, and uses retry transactions to efficiently implement read transactions from target devices with long or variable latency. Details of the arbitration method used to access shared communications bus 1012 are not required to understand the present invention. The delay from when an initiator functional block drives the command and address until the target functional block drives the response is known as the latency of shared communications bus 1012. The bus protocol supports arbitration among many initiator functional blocks and target functional blocks for access to the bus. In the embodiment shown, arbitration for access to shared communications bus 1012 is performed by an initiator interface module, such as module 1004 of Figure 4. In other embodiments, arbitration is performed by functional blocks directly, or by a combination of interface modules and functional blocks. In one embodiment, a bus grant lasts for one pipelined bus cycle. The protocol does not forbid a single functional block from becoming a bus owner for consecutive bus cycles, but does require that the functional block successfully win arbitration on consecutive cycles to earn the right.

Shared communications bus 1012 includes separate address, data, and control wires. Other embodiments may include multiplexed address, data, and control signals that share a wire or wires. Such an embodiment would provide high per-wire transfer efficiency because wires are shared among address and data transfers. A non-multiplexed embodiment of shared communications bus 1012 may be more appropriate for communication between functional blocks on a single integrated circuit chip because wires are relatively inexpensive and performance requirements are usually higher on a single integrated circuit chip. Clock line 220 is a global signal wire that provides a time reference signal to which all other shared communications bus 1012 signals are synchronized. Reset line 222 is a global signal wire that forces each connected functional block into a default state from which system configuration may begin. Command line 224 carries a multi-bit signal driven by an initiator bus owner. In various embodiments, the multi-bit command signal may convey various types of information. For example, a command signal may indicate a transfer type, information regarding duration of a connection, and expected initiator and target behavior during the connection. In one embodiment, the command signal includes one or more bits indicating the beginning and end of a connection. In one embodiment, for example, one bit may indicate the status of a connection. If the bit is zero, the current transfer is the final transfer in the connection. After the receipt of a zero connection status bit, the next receipt of a connection status bit that is a logic one indicates that the transfer is the first in a newly opened connection. Each subsequently received one connection status bit then indicates that the connection is still open.

Supported transfer types in this embodiment include, but are not limited to read and write transfers. Address lines 228 carry a multi-bit signal driven by an initiator bus owner to specify the address of the object to be read or written during the current transfer. Response lines 232 carry a multi-bit signal driven by a target to indicate the status of the current transfer. Supported responses include, but are not limited to the following responses. A NULL response indicates that the current transfer is to be aborted, presumably because the address does not select any target. A data valid and accepted (DVA) response indicates, in the case of a read, that the target is returning requested data on data lines 230. In the case of a write, a DVA response indicates that the target is accepting the provided data from data lines 230. A BUSY response indicates that the selected target has a resource conflict and cannot service the current request. In this case an initiator should reattempt the transfer again later. A RETRY response indicates that the selected target could not deliver the requested read data in time, but promises to do so at a later time. In this case an initiator must reattempt the transfer at a later time.

Connection identifier (CONNID) lines 226 carry a multi-bit signal driven by an initiator bus owner to indicate which connection the current transfer is part of. A connection is a logical state, established by an initiator, in which data may pass between the initiator and an associated target. The CONNID typically transmits information including the identity of the functional block initiating the transfer and ordering information regarding an order in which the transfer must be processed. In one embodiment, the information conveyed by the CONNID includes information regarding the priority of the transfer with respect to other transfers. In one embodiment the CONNID is a eight-bit code. An initiator interface module sends a unique CONNID along with an initial address transfer of a connection. Later transfers associated with this connection (for example, data transfers) also provide the CONNID value so both sender and receiver (as well as any device monitoring transfers on shared communications bus 1012) can unambiguously identify transfers associated with the connection. One advantage of using a CONNID is that transfers belonging to different transactions can be interleaved arbitrarily between multiple devices on a per cycle basis. In one embodiment, shared communications bus 1012 implements a fully pipelined protocol that requires strict control over transaction ordering in order to guarantee proper system operation. Without the use of a CONNID, ordering constraints within a particular transaction may be violated because transfers associated with a particular connection are not identified.

Because a first command may be rejected by a BUSY response while a later command is already in flight, it is essential to provide mechanisms that allow full control over which commands complete. If such control is not present, ambiguous system behavior can result. For instance, if a single initiator interface module issues a sequence of dependent read and write commands, a busy response to one of the commands could result in later commands returning the wrong data. One solution to such problems is to avoid overlapping dependent commands. This solution, however, increases the latency of every dependent command in order to ensure proper results. The present invention uses a CONNID signal, in part, to allow overlapping of dependent commands. Therefore, use of a CONNID improves system performance and efficiency. Another benefit of the CONNID of the present invention is that communication system predictability is enhanced because it allows a shared functional block to respond to requests based upon quality of service guarantees that may vary between connections. For example, data requested to operate a computer display cannot tolerate unpredictable delay because delay causes the display to flicker. Therefore, the CONNID may be used to prioritize data requests from a display controller so that requests from the display controller to a common resource are serviced before other requests. The present invention also allows for flexible reconfiguration of the CONNID to retune system performance.

Figure 6 is a timing diagram of a pipelined write transaction consisting of two write transfers on shared communications bus 1012. Reference may also be made to Figure 5. A single pipelined bus transfer, as shown in Figure 6, includes an arbitration cycle (not shown), followed by a command /address /CONNID (CMD 324/ADDR 328/CONNID 326) cycle (referred to as a request, or REQ cycle), and completed by a DATA 330/RESP 342 cycle (referred to as a response, or RESP cycle). In one embodiment, the number of cycles between a REQ cycle and a RESP cycle is chosen at system implementation time based upon the operating frequency and module latencies to optimize system performance. The REQ-RESP latency, in one embodiment, is two cycles and is labeled above the DATA 330 signal line on Figure 6. Therefore, a complete transfer time includes four shared communications bus 1012 cycles, arbitration, request, delay and response.

Two transfers are shown in Figure 6. On cycle 1, initiator E drives REQ fields 340 to request a WRITE transfer to address ADDRE0. This process is referred to as issuing the transfer request. In one embodiment, a single target is selected to receive the write data by decoding an external address portion of ADDRE0. On cycle 3 (a REQ-RESP latency later), initiator E drives write data DATAEO on the DATA wires; simultaneously, the selected target A drives RESP wires 342 with the DVA code, indicating that A accepts the write data. By the end of cycle 3, target A has acquired the write data, and initiator E detects that target A was able to accept the write data; and the transfer has thus completed successfully.

Meanwhile (i.e. still in cycle 3), initiator E issues a pipelined WRITE transfer (address ADDREl) to target A. The write data and target response for this transfer both occur on cycle 5, where the transfer completes successfully. Proper operation of many systems and sub-systems rely on the proper ordering of related transfers. Thus, proper system operation may require that the cycle 3 WRITE complete after the cycle 1 WRITE transfer. In Figure 6, the CONNID field conveys crucial information about the origin of the transfer that can be used to enforce proper ordering. A preferred embodiment of ordering restrictions is that the initiator and target collaborate to ensure proper ordering, even during pipelined transfers. This is important, because transfer pipelining reduces the total latency of a set of transfers (perhaps a single transaction), thus improving system performance (by reducing latency and increasing usable bandwidth).

According to the algorithm of one embodiment:

1. An initiator may issue a transfer Y: a) if transfer Y is the oldest, non-Issued, non-retired transfer among the set of transfer requests it has with matching CONNID, or b) if all of the older non-retired transfers with matching CONNID are currently issued to the same target as transfer Y. If issued under this provision, transfer Y is considered pipelined with the older non-retired transfers.

2. A target that responds to a transfer X in such a way that the initiator might not retire the transfer must respond BUSY to all later transfers with the same CONNID as transfer X that are pipelined with X.

Note that an older transfer Y that is issued after a newer transfer X with matching CONNID is not considered pipelined with X, even if Y Issues before X completes. This situation is illustrated in Figure 7. If target A has a resource conflict that temporarily prevents it from accepting DATAEO associated with the WRITE ADDREO from cycle 1, then A responds BUSY. Step 2 of the foregoing algorithm requires that A also reject (using BUSY) any other pipelined transfers from the same CONNID (in this case, CONNID 1), since the initiator cannot possibly know about the resource conflict until after the REQ-RESP latency has passed. Thus, target A must BUSY the WRITE ADDREl that is issued in cycle 3, because it has the same CONNID and was issued before the initiator could interpret the BUSY response to the first write transfer, and is thus a pipelined transfer. Furthermore, the second attempt (issued in cycle 4) of the WRITE ADDREO transfer is allowed to complete because it is not a pipelined transfer, even though it overlaps the cycle 3 WRITE ADDREl transfer.

Note that target A determines that the cycle 4 write is not pipelined with any earlier transfers because of when it occurs and which CONNID it presents, and not because of either the CMD nor the ADDR values. Step 1 of the algorithm guarantees that an initiator will only issue a transfer that is the oldest non-issued, non-retired transfer within a given connection. Thus, once the first WRITE ADDREO receives the BUSY response in cycle 3, it is no longer issued, and so it becomes the only CONNID = 1 transfer eligible for issue. It is therefore impossible for a properly operating initiator to issue a pipelined transfer in cycle 4, given that an initial cycle 1 transfer received a BUSY response and the REQ-RESP latency is two cycles.

One embodiment of the initiator maintains a time-ordered queue consisting of the desired transfers within a given CONNID. Each transfer is marked as non- issued and non-retired as they are entered into the queue. It is further marked as pipelined if the immediately older entry in the queue is non-retired and addresses the same target; otherwise, the new transfer is marked non-pipelined. Each time a transfer issues it is marked as issued. When a transfer completes (i.e., when the RESP cycle is finished) the transfer is marked non-issued. If the transfer completes successfully, it is marked as retired and may be deleted from the queue. If the transfer does not complete successfully, it will typically be re-attempted, and thus can go back into arbitration for re-issue. If the transfer does not complete successfully, and it will not be re-attempted, then it should not be marked as retired until the next transfer, if it exists, is not marked as issued. This restriction prevents the initiator logic from issuing out of order. As the oldest non-Retired transfer issues, it is marked as issued. This allows the second-oldest non-retired transfer to arbitrate to issue until the older transfer completes (and is thus marked as non- issued), if it is marked as pipelined.

An embodiment of the target implementation maintains a time-ordered queue whose depth matches the REQ-RESP latency. The queue operates off of the bus clock, and the oldest entry in the queue is retired on each bus cycle; simultaneously, a new entry is added to the queue on each bus cycle. The CONNID from the current REQ phase is copied into the new queue entry. In addition, if the current REQ phase contains a valid transfer that selects the target (via the External Address), then "first" and "busy" fields in the new queue entry may be set; otherwise, the first and busy bits are cleared. The first bit will be set if the current transfer will receive a BUSY response (due to a resource conflict) and no earlier transfer in the queue has the same CONNID and has its first bit set. The first bit implies that the current transfer is the first of a set of potentially-pipelined transfers that will need to be BUSY'd to enforce ordering. The busy bit is set if either the target has a resource conflict or one of the earlier transfers in the queue has the same CONNID and has the first bit set. This logic enforces the REQ-RESP pipeline latency, ensuring that the target accepts no pipelined transfers until the initiator can react to the BUSY response to the transfer marked first.

Application of the algorithm to the initiators and targets in the communication system provides the ability to pipeline transfers (which increases per-connection bandwidth and reduces total transaction latency) while maintaining transaction ordering. The algorithm therefore facilitates high per-connection performance. The fundamental interleaved structure of the pipelined bus allows for high system performance, because multiple logical transactions may overlap one another, thus allowing sustained system bandwidth that exceeds the peak per- connection bandwidths. For instance, Figure 8 demonstrates a system configuration in which initiator E needs to transfer data to target A on every other bus cycle, while initiator D requests data from target B on every other bus cycle. Since the communication system supports fine interleaving (per bus cycle), the transactions are composed of individual transfers that issue at the natural data rate of the functional blocks; this reduces buffering requirements in the functional blocks, and thus reduces system cost. The total system bandwidth in this example is twice the peak bandwidth of any of the functional blocks, and thus high system performance is realized.

The present invention adds additional system-level improvements in the area of efficiency and predictability. First, the connection identifier allows the target to be selective in which requests it must reject to preserve in-order operation. The system only need guarantee ordering among transfers with the same CONNID, so the target must reject (using BUSY) only pipelined transfers. This means that the target may accept transfers presented with other CONNID values even while rejecting a particular CONNID. This situation is presented in Figure 9, which adds an interleaved read transfer from initiator D to the pipelined write transfer of Figure 7. All four transfers in Figure 9 select target A, and A has a resource conflict that prevents successful completion of the WRITE ADDREO that issues in cycle 1. While the rejection of the first write prevents A from accepting any other transfers from CONNID 1 until cycle 4, A may accept the unrelated READ ADDRDO request of cycle 2 if A has sufficient resources. Thus, overall system efficiency is increased, since fewer bus cycles are wasted (as would be the case if target A could not distinguish between connections).

Second, in one embodiment the connection identifier allows the target to choose which requests it rejects. The target may associate meanings such as transfer priority to the CONNID values, and therefore decide which requests to act upon based upon a combination of the CONNID value and the internal state of the target. For instance, a target might have separate queues for storing transfer requests of different priorities. Referring to Figure 9, the target might have a queue for low priority requests (which present with an odd CONNID) and a queue for high priority requests (which present with an even CONNID). Thus, the CONNID 1 WRITE ADDREO request of cycle 1 would be rejected if the low-priority queue were full, whereas the CONNID 2 READ ADDRDO transfer could be completed successfully based upon available high-priority queue resources. Such differences in transfer priorities are very common in highly-integrated electronic systems, and the ability for the target to deliver higher quality of service to higher priority transfer requests adds significantly to the overall predictability of the system.

As Figure 9 implies, the algorithm described above allows a target to actively satisfy transfer requests from multiple CONNID values at the same time. Thus, there may be multiple logical transactions in flight to and/or from the same target, provided that they have separate CONNID values. Thus, the present invention supports multiple connections per target functional block.

Additionally, an initiator may require the ability to present multiple transactions to the communications system at the same time. Such a capability is very useful for initiator such as direct memory access (DMA) devices, which transfer data between two targets. In such an application, the DMA initiator would present a read transaction using a first CONNID to a first target that is the source of the data, and furthermore present a write transaction using a second CONNID to a second target that is the data destination. At the transfer level, the read and write transfers could be interleaved. This reduces the amount of data storage in the DMA initiator, thus reducing system cost. Such an arrangement is shown in Figure 10, where initiator E interleaves pipelined read transfers from target A with pipelined write transfers to target B. Thus, the present invention supports multiple connections per initiator functional block. The control structures required to support implementation of the present invention, as described above with respect to the algorithm, are simple and require much less area than the data buffering area associated with traditional protocols that do not provide efficient fine interleaving of transfers. Thus, the present invention minimizes communication system area and complexity, while delivering high performance and flexibility.

Finally, the CONNID values that are associated with particular initiator transactions should typically be chosen to provide useful information such as transfer priorities but also to minimize implementation cost. It is useful to choose the specific CONNID values at system design time, so the values can be guaranteed to be unique and can be ordered to simplify comparison and other operations. Furthermore, it is frequently useful to be able to change the CONNID values during operation of the communications system so as to alter the performance and predictability aspects of the system. Preferred implementations of the present invention enable flexible system configuration by storing the CONNID values in ROM or RAM resources of the functional blocks, so they may be readily reconfigured at either system build time or system run time.

Figure 11 shows an interconnect 1010, which is a point-to-point interconnect as shown in Figure 4. Interconnect 1010 includes additional signals as compared to the protocol described with reference to Figure 5. As will be explained below, some of the additional signals are particularly useful as signals sent over point-to-point interconnects such as interconnects 1010. The protocol of interconnect 1010 controls point-to-point transfers between a master entity 1102 and a slave entity 1104 over a dedicated (non-shared) interconnect. Referring to Figure 5, a master entity may be, for example, initiator functional block 1002 or target interface module 1006. A slave entity may be, for example, initiator interface module 1004 or target functional block 1008. Signals shown in Figure 11 are labeled with signal names. In addition, some signal names are followed by a notation or notations in parentheses or brackets. The notations are as follows:

(I) The signal is optional and is independently configurable

(A) The signal must be configured together with signals having similar notations

(Al) The signal is independently configurable if (A) interface modules exist

[#] Maximum signal width

The clock signal is the clock of a connected functional block. The command (Cmd) signal indicates the type of transfer on the bus. Commands can be issued independent of data. The address (Addr) signal is typically an indication of a particular resource that an initiator functional block wishes to access. Request Accept (ReqAccept) is a handshake signal whereby slave 1104 allows master 1102 to release Cmd, Addr and DataOut from one transfer and reuse them for another transfer. If slave 1104 is busy and cannot participate in a requested transfer, master 1102 must continue to present Cmd, Addr and DataOut. DataOut is data sent from a master to a slave, typically in a write transfer. Dataln typically carries read data.

Response (Resp) and Dataln are signals sent from slave 1104 to master 1102. Resp indicates that a transfer request that was received by slave 1104 has been serviced. Response accept (RespAccept) is a handshake signal used to indicate whether the master allows the slave to release Resp and Dataln.

Signals Clock, Cmd, Addr, DataOut, ReqAccept, Resp, Dataln, and RespAccept, in one embodiment, make up a basic set of interface module signals. For some functional blocks, the basic set may be adequate for communication purposes.

In other embodiments, some or all of the remaining signals of bus 1012 may be used. In one embodiment, Width is a three-bit signal that indicates a width of a transfer and is useful in a connection that includes transfers of variable width. Burst is a multibit signal that allow individual commands to be associated within a connection. Burst provides an indication of the nature of future transfers, such as how many there will be and any address patterns to be expected. Burst has a standard end marker. Some bits of the Burst field are reserved for user-defined fields, so that a connection may be ignorant of some specific protocol details within a connection.

Interrupt and error signals are an important part of most computer systems. Interrupt and error signals generated by initiator or target functional blocks are shown, but the description of their functionality is dependent upon the nature of a particular functional block and is not important to understanding the invention.

Request Thread Identifier (ReqThreadlD), in one embodiment, is a four-bit signal that provides the thread number associated with a current transaction intended for slave 1104. All commands executed with a particular thread ID must execute in order with respect to one another, but they may execute out of order with respect to commands from other threads. Response Thread Identifier (RespThreadlD) provides a thread number associated with a current response. Because responses in a thread may return out of order with respect to other threads, RespThreadlD is necessary to identify which thread's command is being responded to. In one embodiment, ReqThreadlD and RespThreadlD are optional signals, but if one is used, both must be used.

Request Thread Busy (ReqThreadBusy) allows the slave to indicate to the master that it cannot take any new requests associated with certain threads. In one embodiment, the ReqThreadBusy signal is a vector having one signal per thread, and a signal asserted indicates that the associated thread is busy.

Response Thread Busy (RespThreadBusy) allows the master to indicate to the slave that it cannot take any responses (e.g., on reads) associated with certain threads. The RespThreadBusy signal is a vector having one signal per thread, and a signal asserted indicates that the associated thread is busy.

Request Connection Identifier (ReqConnlD) provides the CONNID associated with the current transaction intended for the target. CONNIDs provide a mechanism by which a system entity may associate particular transactions with the system entity. One use of the CONNID is in establishing request priority among various initiators. Another use is in associating actions or data transfers with initiator identity rather than the address presented with the transaction request.

The embodiment of Figure 11 provides end-to-end connection identification with CONNID as well as point-to-point, or more local identification with Thread ID. A Thread ID is an identifier of local scope that simply identifies transfers between the interface module and its connected functional block. In contrast, the CONNID is an identifier of global scope that identifies transfers between two interface modules (and, if required, their connected functional blocks).

A Thread ID should be small enough to directly index tables within the connected interface module and functional block. In contrast, there are usually more CONNIDs in a system than any one interface module is prepared to simultaneously accept. Using a CONNID in place of a Thread ID requires expensive matching logic in the interface module to associate a returned CONNID with specific requests or buffer entries.

Using a networking analogy, the Thread ID is a level-2 (data link layer) concept, whereas the CONNID is more like a level-3 (transport/session layer) concept. Some functional blocks only operate at level-2, so it is undesirable to burden the functional block or its interface module with the expense of dealing with level-3 resources. Alternatively, some functional blocks need the features of level-3 connections, so in this case it is practical to pass the CONNID through to the functional block.

Referring to Figure 4, a CONNID is required to be unique when transferred between interface modules 1004 and 1006 on shared communications bus 1012. The CONNID may be sent over a local interconnect, such as interconnect 1010. In many cases, however, it is much more efficient to use only Thread ID between a functional block and its interface module. For example initiator functional block 1002 may not require all the information provided by the CONNID. Also, in some systems, multiple identical initiator functional blocks 1002 may exist with the same CONNID so that a particular target functional block 1008 receiving a transfer will not know which connection it is actually part of unless logic in initiator interface module 1004 translates the "local" CONNID to a unique "global" CONNID. The design and implementation of such a translation functionality in an interface module is complicated and expensive. In such cases, the CONNID may be sent between interface modules over shared communications bus 1012 while the Thread ID is sent between a functional block and an interface module.

In the case of an initiator functional block, a one-to-one static correspondence may exist between Thread ID and CONNID. For example if the Thread ID is "1", a single CONNID is mapped for a particular interface module, solving the problem of multiple, identical functional blocks.

In the case of a target functional block, there is a one-to-one dynamic correspondence between a Thread ID and a CONNID. If a target functional block supports two simultaneous threads, the target interface module acquires the CONNID of an open connection and associates it with a thread as needed. For example, a target interface module receives a CONNID of "7", and then maps CONNID 7 to thread "0". Thereafter, all transfers with CONNID 7 are associated with thread 0 until connection 7 is closed.

Referring to Figure 12, an example of a use of Thread ID, consider a series of identical direct memory access (DMA) engines in a system. In Figure 12, elements 1202 are identical DMA engines, each connected to an initiator interface module 1204. Initiator interface modules 1204 are connected to shared communications bus 1212. Target interface module 1206 is also connected to shared communications bus 1212 and transmits data from bus 1212 to DRAM controller 1208, which is a target functional block. Target interface module 1206 is connected to DRAM controller 1208 by interconnect 1214. DRAM controller 1208 controls access to DRAM 1213. A DMA a engine is an example of an initiator functional block that also functions as a target functional block. When the DMA engine is programmed by software, it acts as a target. Thereafter, the DMA engine is an initiator. Because a DMA engine performs both read and write operations, two connections can be associated with a single DMA engine. If some buffering is available in the DMA engine, read and write operations may be decoupled so that both types of operations can be performed concurrently. A read may occur from a long latency storage device which requires the read data to be buffered on the DMA engine before a write operation writes the data. In one embodiment, each of DMA engines 1202 uses a Thread ID to identify the read stream and a different Thread ID to identify the write stream. The DMA engine does not require more information, such as what other functional block participates in a transaction. Therefore, a CONNID is not required to be sent from the DMA engine 1202 to a connected interface module 1204. Mapping of a Thread ID to a CONNID occurs in the interface module 1204.

In one embodiment, each initiator interface module 1204 maps a unique CONNID to each of two Thread Ids from a connected DMA engine 1202. Each of DMA engines 1202 use a single bit, for example, Thread ID of Figure 11, to distinguish between its two threads. For each transfer over shared communications bus a unique CONNID is sent to target interface module 1206. The CONNID may include priority information, for example, assigning high priority to requests for graphics data. The high priority graphics data request is immediately serviced by DRAM controller 1208 while lower priority request may be required to wait.

Because intelligence is designed into the interface modules and the communications protocols, less intelligence is required of the functional block such as the DRAM controller 1208 and the DMA engines 1202. This has the advantage of making functional blocks more portable or reusable as systems evolve. For example, a DMA engine used for a high priority application may be switched with a DMA engine used for a lower priority application simply by changing their respective connected interface modules.

In one embodiment, target and initiator interface modules are programmed at the transistor level so that their precise function, including their CONNID assignment, is fixed at power-up. In another embodiment, the design of interface modules is in RAM so that the interface module is a reprogrammable resource. In this case, the interface module is reprogrammed, including reassignment of CONNIDs, by software.

The present invention has been described in terms of specific embodiments. For example, embodiments of the present invention have been shown as systems of particular configurations, including protocols having particular signals. One of ordinary skill in the art will recognize that different system configurations and different signals may be used without departing from the spirit and scope of the invention as set forth in the claims.

Claims

IN THE CLAIMSWhat is claimed is:
1. A communication system comprising: at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block; and a bus coupled to each of the functional blocks and configured to carry a plurality of signals, wherein the plurality of signals comprises a connection identifier that indicates a particular connection that a data transfer is part of.
2. The communication system of claim 1, wherein the plurality of signals further comprises a thread identifier that indicates a transaction stream that the data transfer is part of.
3. The communication system of claim 2, further comprising: an initiator functional block that sends transfer requests; an initiator interface module coupled to the initiator functional block and to the bus; a target functional block that responds to transfer requests; and a target interface module coupled to the target functional block, wherein the connection identifier is sent with a transfer request from the initiator interface module to the target interface module.
4. The communication system of claim 3, wherein the thread identifier is sent from the target interface module to the target functional block and from the initiator interface module to the initiator functional block.
5. The communication system of claim 4, wherein the connection identifier is sent from the target interface module to the target functional block and from the initiator interface module to the initiator functional block.
6. The communication system of claim 5 wherein the connection identifier is a multi-bit value that encodes information including: a transfer priority; a transfer order; and an functional block that originated the transfer.
7. The communication system of claim 6, wherein the connection identifier is one of a plurality of connection identifiers associated with an initiator functional block, and wherein the connection identifier is mapped to a thread identifier by the initiator interface module.
8. The communication system of claim 7, wherein the connection identifier is one of a plurality of connection identifiers associated with a target functional block that supports simultaneous connections, and wherein the target functional block acquires a connection identifier of an open connection and maps the connection identifier to a thread identifier.
9. The communication system of claim 2, wherein the plurality of signals further comprises: a request thread ID signal that indicates a thread number associated with a current transaction intended for a target functional block; a response thread ID signal that indicates a thread that a transfer from the target functional block is part of; a request thread busy signal that indicates that indicates to an initiator functional block that the target functional block cannot receive new requests associated with certain threads; and a response thread busy signal that indicates that the initiator functional block cannot receive any new responses from the target functional block that are associated with certain threads.
10. A method for communicating between functional blocks in a computer system, the method comprising the steps of: establishing a plurality of connection identifiers, wherein each connection identifier associates a particular data transfer with a particular connection, wherein a connection is a logical state in which data may pass between an initiator functional block of the plurality of functional blocks and a target functional block of the plurality of functional blocks, and wherein a connection is established when a particular data transfer is initiated; and allowing an initiator functional block to issue a first transfer "Y" if the transfer "Y" is an oldest, non-issued, non-retired transfer among a set of transfer requests with a same connection identifier as the transfer "Y".
11. The method of claim 10, further comprising the step of allowing the initiator functional block to issue the transfer "Y" if every non-retired transfer with the same connection identifier is older than the transfer "Y" and is currently issued to a same target functional block as the transfer "Y".
12. The method of claim 11, wherein if the transfer "Y" is issued, the transfer "Y" is considered pipelined with the older, non-retired transfers.
13. The method of claim 10, further comprising the step of the target functional block giving a BUSY response to every later transfer that is pipelined with the transfer "X" and has a same connection identifier as the transfer "X" if the target functional block responds to the transfer "X" so that an initiator initiating the transfer "X" may not retire the transfer "X".
14. The method of claim 13, wherein a transfer "Y" that is issued after a transfer "X", is older than the transfer "X", and has a same connection identifier as the transfer "X" is considered not pipelined with the transaction "X".
15. The method of claim 12, wherein a target functional block determines whether a transfer is a pipelined transfer based upon when the transfer occurs and upon a connection identifier associated with the transfer.
16. The method of claim 14, further comprising the steps of: an initiator functional block maintaining a time-ordered queue of desired transfers with a same connection identifier; the initiating functional block marking a transfer as non-issued and non- retired as it is entered into the queue.
17. The method of claim 16, further comprising the steps of: if a next oldest entry is non-retired and addresses a same target functional block, marking the transfer as pipelined; else marking the transfer as non-pipelined.
18. The method of claim 17, further comprising the step of, when a transfer issues, marking the transfer as issued.
19. The method of claim 18, further comprising the step of, when a transfer is completed, marking the transfer as non-issued.
20. The method of claim 19, further comprising the step of, if the transfer is successfully completed, marking the transfer as retired; and deleting the transfer from the queue.
21. The method of claim 20, further comprising the step of, if the transfer is not successfully completed, re-attempting the transfer.
22. The method of claim 14, further comprising the step of the target functional block maintaining a time-ordered queue having a depth that is a number of bus clock cycles between a request for a transfer and a response to the request.
23. The method of claim 22, further comprising the steps of: on each cycle of the bus clock, retiring an oldest entry in the time-ordered queue; and on each cycle of the bus clock, adding a new entry to the time-ordered queue, including a connection identifier associated with a current request for a transfer.
24. The method of claim 23, further comprising the steps of: if a current request for a transfer contain s a valid transfer that selects the target functional block, allowing a FIRST bit and a BUSY bit of an entry in the time- ordered queue to be set, wherein a set FIRST bit implies that an associated transfer is a first transfer of a set of potentially pipelined transfers; else clearing the FIRST bit and the BUSY bit.
25. The method of claim 24, further comprising the step of setting the FIRST bit if: no transfer in the time-ordered queue is earlier than a current transfer, has a same connection identifier as the current transfer and has an associated FIRST bit set; and the current transfer will receive a BUSY response due to a resource conflict.
26. The method of claim 24, further comprising the step of setting the BUSY bit if: the target functional block has a resource conflict; or an earlier transfer in the time-ordered queue has an associated FIRST bit set and has a same connection identifier as a current transfer.
27. The method of claim 26, further comprising the step of using a connection identifier to enforce ordering among transfers.
28. The method of claim 27, further comprising the step of: in response to a first request for a data transfer issued in a first bus cycle, the target functional block setting a BUSY bit in a first time-ordered queue entry, wherein a first connection identifier is associated with the first request; and in response to a second request for a data transfer in a next bus cycle subsequent to the first bus cycle, the target functional block clearing a BUSY bit in a second time-ordered queue entry and performing an action in connection with executing the data transfer requested in the second request.
PCT/US1999/026901 1998-11-13 1999-11-12 Communications system and method with multilevel connection identification WO2000029961A9 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09191291 US6182183B1 (en) 1998-11-13 1998-11-13 Communications system and method with multilevel connection identification
US09/191,291 1998-11-13

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP19990965799 EP1131729B1 (en) 1998-11-13 1999-11-12 Communications system and method with multilevel connection identification
JP2000582902A JP4083987B2 (en) 1998-11-13 1999-11-12 Communication system having a multilevel connection identification

Publications (2)

Publication Number Publication Date
WO2000029961A1 true WO2000029961A1 (en) 2000-05-25
WO2000029961A9 true true WO2000029961A9 (en) 2000-09-28

Family

ID=22704891

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/026901 WO2000029961A9 (en) 1998-11-13 1999-11-12 Communications system and method with multilevel connection identification

Country Status (4)

Country Link
US (5) US6182183B1 (en)
JP (1) JP4083987B2 (en)
EP (2) EP1131729B1 (en)
WO (1) WO2000029961A9 (en)

Families Citing this family (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182183B1 (en) * 1998-11-13 2001-01-30 Sonics, Inc. Communications system and method with multilevel connection identification
US6338103B1 (en) * 1999-03-24 2002-01-08 International Business Machines Corporation System for high-speed data transfer using a sequence of overlapped global pointer signals for generating corresponding sequence of non-overlapped local pointer signals
US6725441B1 (en) * 2000-03-22 2004-04-20 Xilinx, Inc. Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices
US7162615B1 (en) 2000-06-12 2007-01-09 Mips Technologies, Inc. Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch
US7325221B1 (en) 2000-08-08 2008-01-29 Sonics, Incorporated Logic system with configurable interface
DE10055163B4 (en) * 2000-11-08 2013-01-03 Bayerische Motoren Werke Aktiengesellschaft Data, particularly in motor vehicles
US6634016B1 (en) * 2000-12-01 2003-10-14 Advanced Micro Devices, Inc. Arrangement for partitioning logic into multiple field programmable gate arrays
US7165094B2 (en) * 2001-03-09 2007-01-16 Sonics, Inc. Communications system and method with non-blocking shared interface
US6785753B2 (en) 2001-06-01 2004-08-31 Sonics, Inc. Method and apparatus for response modes in pipelined environment
US20030004699A1 (en) * 2001-06-04 2003-01-02 Choi Charles Y. Method and apparatus for evaluating an integrated circuit model
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en) * 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7487505B2 (en) * 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US6857035B1 (en) 2001-09-13 2005-02-15 Altera Corporation Methods and apparatus for bus mastering and arbitration
US7610451B2 (en) * 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
JP3759054B2 (en) * 2002-03-01 2006-03-22 Necエレクトロニクス株式会社 Bus system
US7194566B2 (en) * 2002-05-03 2007-03-20 Sonics, Inc. Communication system and method with configurable posting points
US7356633B2 (en) * 2002-05-03 2008-04-08 Sonics, Inc. Composing on-chip interconnects with configurable interfaces
US7254603B2 (en) * 2002-05-03 2007-08-07 Sonics, Inc. On-chip inter-network performance optimization using configurable performance parameters
US7302691B2 (en) * 2002-05-10 2007-11-27 Sonics, Incorporated Scalable low bandwidth multicast handling in mixed core systems
US6880133B2 (en) * 2002-05-15 2005-04-12 Sonics, Inc. Method and apparatus for optimizing distributed multiplexed bus interconnects
US7337275B2 (en) * 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US6976106B2 (en) * 2002-11-01 2005-12-13 Sonics, Inc. Method and apparatus for speculative response arbitration to improve system latency
US7243264B2 (en) * 2002-11-01 2007-07-10 Sonics, Inc. Method and apparatus for error handling in networks
US7266786B2 (en) * 2002-11-05 2007-09-04 Sonics, Inc. Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems
US7603441B2 (en) * 2002-12-27 2009-10-13 Sonics, Inc. Method and apparatus for automatic configuration of multiple on-chip interconnects
US7149829B2 (en) * 2003-04-18 2006-12-12 Sonics, Inc. Various methods and apparatuses for arbitration among blocks of functionality
US20040210696A1 (en) * 2003-04-18 2004-10-21 Meyer Michael J. Method and apparatus for round robin resource arbitration
CN100422974C (en) 2003-05-07 2008-10-01 皇家飞利浦电子股份有限公司 Processing system and method for transmitting data
EP1623331A1 (en) * 2003-05-07 2006-02-08 Philips Electronics N.V. Processing system and method for transmitting data
WO2004100005A1 (en) * 2003-05-08 2004-11-18 Koninklijke Philips Electronics N.V. Processing system and method for communicating data
US7194658B2 (en) * 2003-07-24 2007-03-20 Sonics, Inc. Various methods and apparatuses for interfacing of a protocol monitor to protocol checkers and functional checkers
US8949548B2 (en) 2003-09-12 2015-02-03 Broadcom Corporation System and method of sharing memory by arbitrating through an internal data bus
US7296105B2 (en) * 2003-10-03 2007-11-13 Sonics, Inc. Method and apparatus for configuring an interconnect to implement arbitration
US8504992B2 (en) * 2003-10-31 2013-08-06 Sonics, Inc. Method and apparatus for establishing a quality of service model
US7213099B2 (en) * 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
US7185309B1 (en) 2004-01-30 2007-02-27 Xilinx, Inc. Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip
US7770179B1 (en) 2004-01-30 2010-08-03 Xilinx, Inc. Method and apparatus for multithreading on a programmable logic device
US7823162B1 (en) 2004-01-30 2010-10-26 Xilinx, Inc. Thread circuits and a broadcast channel in programmable logic
US7228520B1 (en) 2004-01-30 2007-06-05 Xilinx, Inc. Method and apparatus for a programmable interface of a soft platform on a programmable logic device
US7552042B1 (en) 2004-01-30 2009-06-23 Xilinx, Inc. Method for message processing on a programmable logic device
US7353484B1 (en) * 2004-02-09 2008-04-01 Altera Corporation Methods and apparatus for variable latency support
US7475168B2 (en) * 2004-03-11 2009-01-06 Sonics, Inc. Various methods and apparatus for width and burst conversion
US7543088B2 (en) * 2004-03-11 2009-06-02 Sonics, Inc. Various methods and apparatuses for width and burst conversion
US7136987B2 (en) * 2004-03-30 2006-11-14 Intel Corporation Memory configuration apparatus, systems, and methods
FR2870373B1 (en) * 2004-05-13 2006-07-28 St Microelectronics Sa gel management of a functional module in a system on a chip
US7254658B2 (en) * 2004-06-08 2007-08-07 Arm Limited Write transaction interleaving
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling
DE602004012106T2 (en) * 2004-10-11 2009-02-19 Texas Instruments France Multi-channel DMA with shared FIFO buffer
WO2006042108A1 (en) * 2004-10-11 2006-04-20 Texas Instruments Incorporated Multi-threaded direct memory access
WO2006042261A1 (en) * 2004-10-11 2006-04-20 Texas Instruments Incorporated Multi-channel direct memory access with shared first-in-first-out memory
EP1645968B1 (en) 2004-10-11 2008-03-19 Texas Instruments Incorporated Multi-threaded DMA
US7739436B2 (en) * 2004-11-01 2010-06-15 Sonics, Inc. Method and apparatus for round robin resource arbitration with a fast request to grant response
US7277975B2 (en) * 2004-11-02 2007-10-02 Sonics, Inc. Methods and apparatuses for decoupling a request from one or more solicited responses
US8032676B2 (en) * 2004-11-02 2011-10-04 Sonics, Inc. Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device
US7155554B2 (en) * 2004-11-02 2006-12-26 Sonics, Inc. Methods and apparatuses for generating a single request for block transactions over a communication fabric
WO2006048826A1 (en) * 2004-11-08 2006-05-11 Koninklijke Philips Electronics N.V. Integrated circuit and method for data transfer in a network on chip environment
US7644201B2 (en) * 2004-11-17 2010-01-05 International Business Machines Corporation Method and system for performance enhancement via transaction verification using a counter value in a polled data storage environment
US20060225015A1 (en) * 2005-03-31 2006-10-05 Kamil Synek Various methods and apparatuses for flexible hierarchy grouping
US20060282498A1 (en) * 2005-06-09 2006-12-14 Hitach, Ltd. Sensor network system, method for data processing of a sensor network system
US7694249B2 (en) * 2005-10-07 2010-04-06 Sonics, Inc. Various methods and apparatuses for estimating characteristics of an electronic system's design
JP4701152B2 (en) * 2006-10-20 2011-06-15 富士通株式会社 Data relay apparatus, data relay method and a data relay program
US8020124B2 (en) * 2006-11-20 2011-09-13 Sonics, Inc. Various methods and apparatuses for cycle accurate C-models of components
US20080120082A1 (en) * 2006-11-20 2008-05-22 Herve Jacques Alexanian Transaction Co-Validation Across Abstraction Layers
US8868397B2 (en) * 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US7814243B2 (en) * 2007-06-01 2010-10-12 Sonics, Inc. Shared storage for multi-threaded ordered queues in an interconnect
US8296430B2 (en) 2007-06-18 2012-10-23 International Business Machines Corporation Administering an epoch initiated for remote memory access
US8108648B2 (en) * 2007-06-25 2012-01-31 Sonics, Inc. Various methods and apparatus for address tiling
US8407433B2 (en) * 2007-06-25 2013-03-26 Sonics, Inc. Interconnect implementing internal controls
US8438320B2 (en) * 2007-06-25 2013-05-07 Sonics, Inc. Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
DE602007004209D1 (en) * 2007-08-13 2010-02-25 Accenture Global Services Gmbh News sequencer for correlated business events
US8713569B2 (en) * 2007-09-26 2014-04-29 Intel Corporation Dynamic association and disassociation of threads to device functions based on requestor identification
US9065839B2 (en) * 2007-10-02 2015-06-23 International Business Machines Corporation Minimally buffered data transfers between nodes in a data communications network
US20090113308A1 (en) * 2007-10-26 2009-04-30 Gheorghe Almasi Administering Communications Schedules for Data Communications Among Compute Nodes in a Data Communications Network of a Parallel Computer
US8229723B2 (en) * 2007-12-07 2012-07-24 Sonics, Inc. Performance software instrumentation and analysis for electronic design automation
US8044303B2 (en) * 2008-03-04 2011-10-25 Inventec Corporation Trace carrier
US8073820B2 (en) 2008-04-07 2011-12-06 Sonics, Inc. Method and system for a database to monitor and analyze performance of an electronic design
US20090274049A1 (en) * 2008-05-02 2009-11-05 Realtek Semiconductor Corp. Non-blocked network system and packet arbitration method thereof
US8817619B2 (en) * 2008-06-27 2014-08-26 Realtek Semiconductor Corp. Network system with quality of service management and associated management method
US8032329B2 (en) * 2008-09-04 2011-10-04 Sonics, Inc. Method and system to monitor, debug, and analyze performance of an electronic design
US8001510B1 (en) * 2008-09-05 2011-08-16 Xilinx, Inc. Automated method of architecture mapping selection from constrained high level language description via element characterization
JP5445073B2 (en) * 2009-11-27 2014-03-19 セイコーエプソン株式会社 System and data transfer method therefor comprising a plurality of storage devices
US20110213949A1 (en) * 2010-03-01 2011-09-01 Sonics, Inc. Methods and apparatus for optimizing concurrency in multiple core systems
US8365186B2 (en) 2010-04-14 2013-01-29 International Business Machines Corporation Runtime optimization of an application executing on a parallel computer
US8504730B2 (en) * 2010-07-30 2013-08-06 International Business Machines Corporation Administering connection identifiers for collective operations in a parallel computer
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US8601288B2 (en) 2010-08-31 2013-12-03 Sonics, Inc. Intelligent power controller
US8438306B2 (en) 2010-11-02 2013-05-07 Sonics, Inc. Apparatus and methods for on layer concurrency in an integrated circuit
US9405700B2 (en) 2010-11-04 2016-08-02 Sonics, Inc. Methods and apparatus for virtualization in an integrated circuit
JP5644443B2 (en) * 2010-12-03 2014-12-24 富士通株式会社 Communication device and the duplexing method
US8565120B2 (en) 2011-01-05 2013-10-22 International Business Machines Corporation Locality mapping in a distributed processing system
US9317637B2 (en) 2011-01-14 2016-04-19 International Business Machines Corporation Distributed hardware device simulation
US8689228B2 (en) 2011-07-19 2014-04-01 International Business Machines Corporation Identifying data communications algorithms of all other tasks in a single collective operation in a distributed processing system
US8711867B2 (en) 2011-08-26 2014-04-29 Sonics, Inc. Credit flow control scheme in a router with flexible link widths utilizing minimal storage
US8514889B2 (en) 2011-08-26 2013-08-20 Sonics, Inc. Use of common data format to facilitate link width conversion in a router with flexible link widths
US8798038B2 (en) 2011-08-26 2014-08-05 Sonics, Inc. Efficient header generation in packetized protocols for flexible system on chip architectures
US8930602B2 (en) 2011-08-31 2015-01-06 Intel Corporation Providing adaptive bandwidth allocation for a fixed priority arbiter
US9021156B2 (en) 2011-08-31 2015-04-28 Prashanth Nimmala Integrating intellectual property (IP) blocks into a processor
US9250948B2 (en) 2011-09-13 2016-02-02 International Business Machines Corporation Establishing a group of endpoints in a parallel computer
US8868941B2 (en) 2011-09-19 2014-10-21 Sonics, Inc. Apparatus and methods for an interconnect power manager
US8805926B2 (en) 2011-09-29 2014-08-12 Intel Corporation Common idle state, active state and credit management for an interface
US8711875B2 (en) 2011-09-29 2014-04-29 Intel Corporation Aggregating completion messages in a sideband interface
US8929373B2 (en) 2011-09-29 2015-01-06 Intel Corporation Sending packets with expanded headers
US8713234B2 (en) 2011-09-29 2014-04-29 Intel Corporation Supporting multiple channels of a single interface
US8713240B2 (en) 2011-09-29 2014-04-29 Intel Corporation Providing multiple decode options for a system-on-chip (SoC) fabric
US8874976B2 (en) 2011-09-29 2014-10-28 Intel Corporation Providing error handling support to legacy devices
US8775700B2 (en) 2011-09-29 2014-07-08 Intel Corporation Issuing requests to a fabric
US9053251B2 (en) 2011-11-29 2015-06-09 Intel Corporation Providing a sideband message interface for system on a chip (SoC)
US9348775B2 (en) 2012-03-16 2016-05-24 Analog Devices, Inc. Out-of-order execution of bus transactions
US9225665B2 (en) * 2012-09-25 2015-12-29 Qualcomm Technologies, Inc. Network on a chip socket protocol

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564899A (en) * 1982-09-28 1986-01-14 Elxsi I/O Channel bus
US4706190A (en) * 1983-09-22 1987-11-10 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in digital computer system
JPH0562384B2 (en) 1984-07-24 1993-09-08 Fuji Photo Film Co Ltd
US5101479A (en) * 1989-07-21 1992-03-31 Clearpoint Research Corporation Bus device for generating and responding to slave response codes
JP2992621B2 (en) 1990-11-30 1999-12-20 富士通株式会社 Rock transfer system
US5274783A (en) 1991-06-28 1993-12-28 Digital Equipment Corporation SCSI interface employing bus extender and auxiliary bus
JPH05313923A (en) 1992-05-07 1993-11-26 Ricoh Co Ltd Exclusive controller for shared resources
JP3167228B2 (en) * 1993-09-20 2001-05-21 富士通株式会社 Vcc table access methods and virtual channel converter
US5548767A (en) * 1993-10-06 1996-08-20 Intel Corporation Method and apparatus for streamlined handshaking between state machines
US5634081A (en) * 1994-03-01 1997-05-27 Adaptec, Inc. System for starting and completing a data transfer for a subsequently received autotransfer command after receiving a first SCSI data transfer command that is not autotransfer
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
JP3515263B2 (en) * 1995-05-18 2004-04-05 株式会社東芝 Router device, a data communication network system, node device, the data transfer method and a network connection method
US5729529A (en) * 1995-07-06 1998-03-17 Telefonaktiebolaget Lm Ericsson (Publ.) Timing and synchronization technique for ATM system
US5748914A (en) * 1995-10-19 1998-05-05 Rambus, Inc. Protocol for communication with dynamic memory
US5822553A (en) * 1996-03-13 1998-10-13 Diamond Multimedia Systems, Inc. Multiple parallel digital data stream channel controller architecture
US5878045A (en) * 1996-04-26 1999-03-02 Motorola, Inc. Method and apparatus for converting data streams in a cell based communications system
US6167486A (en) * 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
JPH10171750A (en) * 1996-12-09 1998-06-26 Fujitsu Ltd Inter-memory data transfer system
US6002692A (en) * 1996-12-30 1999-12-14 Hyundai Electronics America Line interface unit for adapting broad bandwidth network to lower bandwidth network fabric
US6078736A (en) * 1997-08-28 2000-06-20 Xilinx, Inc. Method of designing FPGAs for dynamically reconfigurable computing
JPH1173258A (en) * 1997-08-28 1999-03-16 Toshiba Corp Low power consumption bus structure and method for controlling the same and system for synthesizing low power consumption bus structure and method therefor and portable information equipment
US5948089A (en) * 1997-09-05 1999-09-07 Sonics, Inc. Fully-pipelined fixed-latency communications system with a real time dynamic bandwidth allocation
US6147890A (en) * 1997-12-30 2000-11-14 Kawasaki Steel Corporation FPGA with embedded content-addressable memory
US6005412A (en) * 1998-04-08 1999-12-21 S3 Incorporated AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip
US6601138B2 (en) * 1998-06-05 2003-07-29 International Business Machines Corporation Apparatus system and method for N-way RAID controller having improved performance and fault tolerance
US6182183B1 (en) 1998-11-13 2001-01-30 Sonics, Inc. Communications system and method with multilevel connection identification
US6493776B1 (en) * 1999-08-12 2002-12-10 Mips Technologies, Inc. Scalable on-chip system bus
US7325221B1 (en) * 2000-08-08 2008-01-29 Sonics, Incorporated Logic system with configurable interface
US7165094B2 (en) * 2001-03-09 2007-01-16 Sonics, Inc. Communications system and method with non-blocking shared interface
US20030004699A1 (en) * 2001-06-04 2003-01-02 Choi Charles Y. Method and apparatus for evaluating an integrated circuit model

Also Published As

Publication number Publication date Type
EP1131729B1 (en) 2012-03-28 grant
US20080183926A1 (en) 2008-07-31 application
US20040177186A1 (en) 2004-09-09 application
US7120712B2 (en) 2006-10-10 grant
EP2306328A2 (en) 2011-04-06 application
US6725313B1 (en) 2004-04-20 grant
US7647441B2 (en) 2010-01-12 grant
US20070094429A1 (en) 2007-04-26 application
JP4083987B2 (en) 2008-04-30 grant
JP2002530744A (en) 2002-09-17 application
WO2000029961A1 (en) 2000-05-25 application
EP2306328B1 (en) 2013-06-05 grant
EP2306328A3 (en) 2012-05-16 application
US6182183B1 (en) 2001-01-30 grant
EP1131729A4 (en) 2005-02-09 application
EP1131729A1 (en) 2001-09-12 application

Similar Documents

Publication Publication Date Title
US5396602A (en) Arbitration logic for multiple bus computer system
US5525971A (en) Integrated circuit
US6862608B2 (en) System and method for a distributed shared memory
US6205508B1 (en) Method for distributing interrupts in a multi-processor system
US6016528A (en) Priority arbitration system providing low latency and guaranteed access for devices
US5301283A (en) Dynamic arbitration for system bus control in multiprocessor data processing system
US6574688B1 (en) Port manager controller for connecting various function modules
US6715023B1 (en) PCI bus switch architecture
US6499079B1 (en) Subordinate bridge structure for a point-to-point computer interconnection bus
US6760793B2 (en) Transaction credit control for serial I/O systems
US6493776B1 (en) Scalable on-chip system bus
US5379434A (en) Apparatus and method for managing interrupts in a multiprocessor system
US6745369B1 (en) Bus architecture for system on a chip
US20050177664A1 (en) Bus system and method thereof
US6757768B1 (en) Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node
US7673087B1 (en) Arbitration for an embedded processor block core in an integrated circuit
US5634015A (en) Generic high bandwidth adapter providing data communications between diverse communication networks and computer system
US5459840A (en) Input/output bus architecture with parallel arbitration
US5546543A (en) Method for assigning priority to receive and transmit requests in response to occupancy of receive and transmit buffers when transmission and reception are in progress
US4763249A (en) Bus device for use in a computer system having a synchronous bus
US5131085A (en) High performance shared main storage interface
US20040024948A1 (en) Response reordering mechanism
US6653859B2 (en) Heterogeneous integrated circuit with reconfigurable logic cores
US5581709A (en) Multiple computer system using I/O port adaptor to selectively route transaction packets to host or shared I/O device
US7340548B2 (en) On-chip bus

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: C2

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

COP Corrected version of pamphlet

Free format text: PAGES 1/9-9/9, DRAWINGS, REPLACED BY NEW PAGES 1/12-12/12; DUE TO LATE TRANSMITTAL BY THE RECEIVINGOFFICE

AL Designated countries for regional patents

Kind code of ref document: C2

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 1999965799

Country of ref document: EP

ENP Entry into the national phase in:

Ref country code: JP

Ref document number: 2000 582902

Kind code of ref document: A

Format of ref document f/p: F

WWP Wipo information: published in national office

Ref document number: 1999965799

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642