WO2000016400A1 - Applications of protective ceramics - Google Patents

Applications of protective ceramics Download PDF

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Publication number
WO2000016400A1
WO2000016400A1 PCT/CN1999/000147 CN9900147W WO0016400A1 WO 2000016400 A1 WO2000016400 A1 WO 2000016400A1 CN 9900147 W CN9900147 W CN 9900147W WO 0016400 A1 WO0016400 A1 WO 0016400A1
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capacitor
ceramic material
metal
element according
protective ceramic
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PCT/CN1999/000147
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French (fr)
Chinese (zh)
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WO2000016400A8 (en
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Guobiao Zhang
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Guobiao Zhang
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Publication of WO2000016400A8 publication Critical patent/WO2000016400A8/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

Definitions

  • the present invention belongs to the field of integrated circuits, and more specifically, relates to the application of protective ceramic materials in the following fields, including: field-programmable gate array (FPGA) and anti-fuse in programmable read-only memory (PROM). ), Storage capacitors of dynamic random access memory (DRAM), Josephson junctions in superconducting circuits, and other capacitor-like elements.
  • FPGA field-programmable gate array
  • PROM programmable read-only memory
  • DRAM dynamic random access memory
  • Josephson junctions in superconducting circuits and other capacitor-like elements.
  • An antifuse is a field programming element used in a field programming gate array (FPGA), a programmable read-only memory (PROM), and the like. Its structure is similar to that of a capacitor: it has two electrodes and an insulating film sandwiched between the two electrodes. This insulating film is also called anti-fuse film. It puts the anti-fuse in a high-resistance OFF state before programming. After applying a programming voltage and current, the anti-fuse is programmed to its ON state, and Shows low resistance, causing electrical conduction between the two electrodes.
  • FPGA field programming gate array
  • PROM programmable read-only memory
  • the anti-fuse insulation material is called anti-fuse material, and it is the key to the success of anti-fuse technology.
  • anti-fuse material There are millions of antifuse in an FPGA or PROM. They should all show similar characteristics.
  • unprogrammed antifuse has a small leakage current. If the leakage current in an unprogrammed antifuse is so large that the two electrodes appear to be conducting, the FPGA or PROM will exhibit an incorrect logic function, resulting in a reduction in yield. In order to improve the yield, it is necessary to ensure that the antifuse is free from defects. If the area of each antifuse is 1 ⁇ m 2 , the total area of the antifuse in an FPGA or PROM will exceed 1 mm 2 . Therefore, the quality of the anti-fuse material is good enough to generate at least a capacitor-like element with a defect density of less than 1 / mm 2 .
  • Metal-to-metal antifuse has been extensively studied for use in next-generation FPGAs and PROMs.
  • a major problem is to find a high quality antifuse material.
  • the use of high-temperature-produced metal oxides as antifuse materials is attracting increasing interest, such as US Patent 5,070,384 (April 12, 1990) to McCollum et al., Which provides a use of titanium oxide as antifuse Material anti-fuse film; U.S. Patent 5,347,832 to Tung et al. (December 20, 1994) describes the use of titanium oxide and tungsten oxide as anti-fuse materials. Fuse film.
  • titanium oxide and tungsten oxide are not protective oxides.
  • DRAM Dynamic random access memory
  • Each DRAM cell contains an access transistor and a storage capacitor.
  • the storage capacitor consists of two opposite electrodes and an insulating film. Digital information is represented by the charge stored on the access capacitor.
  • a DRAM chip contains 256 megabits of information. This means that there is a 256 megabyte storage capacitor on this DRAM chip. These capacitors should have similar characteristics, for example, they can hold enough charge on the electrode for a long enough time. If the leakage current of a capacitor is too large, these stored charges may be leaked before the next refresh signal arrives, so the stored information will be lost. To ensure that a DRAM chip has proper function, the leakage current of the storage capacitor should be small, controllable and repeatable. This requirement should apply to all storage capacitors in a DRAM chip.
  • the integrity of the insulating material is the key to ensuring that the leakage current of each storage capacitor is small, controllable and repeatable. If there are micro holes in the insulating material, such defects can lead to excessive leakage currents.
  • the defect density of the insulating material on the DRAM chip should be limited to a certain degree. As a simple estimate, the area of each storage capacitor is 2 ⁇ m 2. Then, the total area of the insulating material on a gigabit DRAM chip will exceed 20 cm 2 . Therefore, even with the scheme of using extra memory cells, the defect density of the insulating film should be lower than ⁇ l / mm 2 .
  • Silicon oxide / nitrogen oxide / (oxide) has been used as an insulating material for dynamic memories.
  • the integrity of its insulating medium is well documented.
  • the dielectric constant of silicon oxide is 3.9, which is relatively small.
  • the capacitance requirement of a storage capacitor in a 1 Gigabit DRAM is 25 to 40fF. If ON (O) is used as an insulating material, the capacitance area of a memory cell should be at least 2 ⁇ m 2. On the other hand, the area of each memory cell should not exceed 0.2 ⁇ m 2. Therefore, it is necessary to satisfy both The requirement of memory cell area is very difficult. Therefore, more and more attention is being paid to metal oxides having a large dielectric constant and reducing the capacitance area.
  • the dielectric constants of metal oxides are relatively large, so that they are suitable as insulation materials for storage capacitors.
  • Many examples of metal oxides with large dielectric constants can be found in the past technology of dynamic memories.
  • US Patent 4,937,650 to Shinriki et al. (June 26, 1990) and US Patent 5,439,840 to August et al. (August 8, 1995) describe the use of tantalum oxide (Ta 2 0 5 ), titanium oxide (Ti 0 2 ), etc. Technology as an insulating material. To date, no reports of the success of these materials have been seen. The reason is that these materials have a high defect density. At first, people suspected that these defects were introduced during the production process, but the use of advanced production methods did not solve the problem.
  • tantalum oxide (Ta 2 0 5 ) and titanium oxide (Ti0 2 ) are non-protective oxides, that is, they have a porous structure (Shackelford, "Introduction to Materials Science for Engineers", Second edition, 609-610 pages, 1988). Therefore, the use of any of these materials cannot achieve a high yield of integrated circuits.
  • Superconducting circuits have advantages such as high speed and low energy consumption.
  • Josephson junctions are key components of superconducting circuits. Its structure is similar to a capacitor, that is, a thin layer of insulating material is sandwiched between two superconducting materials. This insulating material is used as a tunnel film.
  • the insulating material used in the prior art is alumina (Al 2 0 3 ), but if the process of manufacturing alumina is not optimized, the Josephson junction may still contain defects. At the same time, we can find more insulation materials suitable for superconducting circuits in superconducting circuits.
  • FPGA field-programmable gate array
  • PROM programmable read-only memory
  • DRAM dynamic memory
  • superconducting circuits depends to a large extent on the insulation material. Integrity. If the leakage current from any one of the antifuse, storage capacitor, or Josephson junction is too large, the function of the entire chip will be greatly affected. The main cause of excessive leakage current is the micropores in the insulating material. The metal particles falling into the micropores will form an electrical connection between two opposite electrodes. For FPGAs, PROM. DRAMs and superconducting circuits, the ideal insulating material should be free of micropores.
  • the inventors studied a group of protective covering materials identified by metallurgy. These protective covering materials are non-porous and can densely cover the underlying metal. Etching agents, such as oxygen, cannot penetrate these covering materials. There is then no chemical reaction between the etchant and the metal covered by the protective covering material. Guarantee these covering materials The key protective factor is that they do not have micropores. Therefore, when these protective covering materials are used as an insulating material like a capacitor element in an integrated circuit such as a DRAM, a large leakage current can be prevented from flowing between the electrodes.
  • the criteria for the identification of protective covering materials originally developed in metallurgy can be used as the criteria for the identification of ideal insulating materials for use in integrated circuits.
  • An overview of the identification of protective ceramics is provided below. These discussions can be applied to both protective covering materials in metallurgy and protective insulating materials in integrated circuits.
  • Ceramic is a compound that is formed by combining at least one metal element and at least one of the following five non-metal elements (carbon, nitrogen, oxygen, thorium, sulfur) (Table 1).
  • ceramics can have a polycrystalline structure or an amorphous structure (amorphous ceramics are also referred to as glass).
  • Some examples of ceramics are A1 2 0 3 and Cr 2 0 3 combatIn general, ceramics are refractory. They are stable at high temperatures. As a result, they can withstand the harsh production environments of integrated circuit manufacturing processes.
  • Pilling-Bedworth ratio (Shackelford,
  • Pilling-Bedworth ratio R of a ceramic is defined as the ratio of the volume of the ceramic to the volume of the metal used to form the ceramic.
  • the metal used to form this ceramic is less than 1, the ceramic tends to be porous and cannot cover the entire metal surface, so it is not protective; if R is equal to or slightly greater than 1, the ceramic is protective; if R is much greater than 1, the ceramic There will be large compressive stress, which will cause the ceramic coating to peel and crack.
  • Table 1 In the periodic table, ceramics are formed by combining at least one metal element (light color) and at least one of five non-metal elements (carbon, nitrogen, oxygen, phosphorus, sulfur) (black).
  • a metal oxide is used as a specific example to explain how to use Pilling-Bedworth ratio to identify the inherent protection of a metal oxide.
  • the Pilling-Bedworth ratio R of a metal oxide is defined as: the ratio of the volume of metal oxide formed by the reaction of metal and oxygen to the volume of metal used
  • M and D are the molecular weight and density of the metal oxide (metal) a (oxygen) b
  • m and d are the atomic weight and density of the metal
  • a is the number of metal atoms in the metal oxide molecular formula.
  • Table 2 shows how the Pilling-Bedworth ratio can be used to identify the inherent protection of a metal oxide. Table 2 is different
  • the Pilling-Bedworth ratio of the protective oxide is greater than 1, preferably less than 2.
  • R there are other factors that must be met to form protective oxygen.
  • Compounds such as similar thermal expansion coefficients between metals and oxides and good adhesion between metals and oxides are two of the factors.
  • Silicon oxide has been used in integrated circuits for decades and is probably by far the most ideal insulating material. Although silicon oxide is an inherently protective oxide, micropores are still produced when silicon oxide is produced dry. The protection (integrity) of silicon oxide can be improved by changing the substrate preparation and production processes. Many articles have been published in this regard. For example, Offenberg et al. Suggested that UV ozone be used to treat silicon substrates before producing silicon oxide (Vacuum Science and Technology Magazine A, Vol. 9, N0.3, pages 1058 ⁇ 1065, May 1991 / June issue); Moazzami et al.
  • Table 3 shows the Pilling-Bedworth ratio of various metal oxides, nitrides, carbides, phosphides, and sulfides. Below table 3 is a list of protective ceramics. Table 3.Pilling-Bedworth ratio of different ceramic materials.
  • Intrinsically protective metal oxides are Be, Cu, Al, Si, Cr, Mn, Fe, Co, Ni, Pd, Pb, Ce, Sc, Zn, Zr,
  • La, Y, Nb, Rh, Pt and other oxides La, Y, Nb, Rh, Pt and other oxides.
  • Intrinsically protective metal nitrides include nitrides of Ti, V, Cr, Fe, Cu, Zn, Zr, Nb, Ta, Al, Ge, etc.
  • 'Intrinsically protective metal carbides include Ti, Si, V, Cr, Mn, Fe, Ni, Y, Zr, Nb, Mo, La, Hf, Ta, W, Al and other carbides.
  • Intrinsically protective metal phosphides include Ti, Fe, Co, Ni, Cu, Cd, Sn and other phosphides.
  • Intrinsically protective metal sulfides include sulfides of Cu, Ag, In, Sn, TI, Pb, and Bi. Summary of the Invention
  • the object of the present invention is to provide a capacitor-like element with high yield and good durability; Another object of the present invention is to provide an integrated circuit with a capacitor-like element having high yield and good durability.
  • the above object can be achieved by the capacitance-like element and integrated circuit of the present invention.
  • the capacitance-like element of the present invention includes: a first bottom electrode composed of a conductor and having an upper surface, a second top electrode composed of a conductor, and a second electrode disposed between the first bottom electrode and the second top power stage.
  • An insulating film characterized in that: the insulating film contains at least one layer of protective ceramic material, which is composed of at least one metal element and at least one non-metal element among carbon, nitrogen, oxygen, phosphorus, and sulfur
  • the integrated circuit of the present invention includes a semiconductor integrated circuit and a superconducting integrated circuit.
  • a field programming gate array in the integrated circuit an anti-fuse in a programmable read-only memory, and a capacitor in a dynamic random access memory.
  • the Josephson junction in a storage capacitor or a superconducting circuit is the above-mentioned capacitive element.
  • a protective ceramic material is used as the insulating material between the two electrodes, it can provide anti-fuse structures with low defect density and good durability, capacitors or storage capacitors, and capacitor-like elements such as Josephson junctions.
  • the capacitor-like element using the protective ceramic material as the insulating material of the present invention can be produced using a standard semiconductor manufacturing process, and thus a conventional semiconductor manufacturing process can be used to conveniently produce a field-programmable gate array with high yield and programmable Read-only memory, dynamic memory, and superconducting circuits.
  • Figure 1 is a cross-sectional view of a protective ceramic material applied to an antifuse film.
  • Figure 2 is a sectional view of a storage capacitor using a protective ceramic material in a dynamic memory.
  • Figure 3 is a cross-sectional view of a Josephson junction using a protective ceramic material in a superconducting circuit.
  • the cross-sectional view of Figure 1 shows the application of protective ceramics to antifuse films in FPGAs and PROMs.
  • the antifuse structure has a bottom electrode 20, a top electrode 22, and an insulated antifuse film 24.
  • the bottom electrode contains metal materials, where metal materials refer to metal elements, metal alloys, and metal compounds.
  • the bottom electrode 20 may also be a composite film, including an adhesion film, a conductive film, a barrier film, and a base film. An adhesion film is not necessary and depends on the situation.
  • the conductive film may contain a good conductor, for example, aluminum (A1), silver (Ag), copper (Cu), or gold (Au), and its thickness is between 100 nm and 200 ⁇ m, preferably about 500 nm. It provides a good conductive path for electrical signals.
  • the barrier film contains refractory metal, for example, tungsten (W), 3 ⁇ 4 (Mo), titanium (Ti), or titanium tungsten alloy (TiW).
  • the thickness is between 50 and 300 nm, and preferably 100 nm. It ensures that no chemical reaction occurs between the anti-fuse film 24 and the conducting film during the high-temperature production process.
  • the necessity of the barrier film greatly depends on the reactivity between the conductive material and the anti-fuse material. If the anti-fuse material is stable around 4501: and does not react with the conductive material, then there is no need to use a barrier film between the conductive film and the anti-fuse film 24. If the antifuse material is a metal oxide formed by oxidizing the upper surface of the bottom electrode 20, then a base film is required. This base film is the uppermost layer of the bottom electrode 20, and it contains a metal element forming the metal oxide. Its thickness is between 5 and 100 nm, preferably 20 nm. For example, if the antifuse material is chromium oxide grown at a high temperature, the base film needs to be a chromium (Cr) film.
  • the anti-fuse film 24 contains one or more films. Among these films 24a, 24b, at least one layer contains a protective ceramic material, and its Pilling-Bedworth ratio should be greater than 1, preferably less than 2, these protective ceramic materials. Examples include Be, Cu, Al, Si, Cr, Mn, Co, Ni, Pd, Pb, and Ce oxides.
  • the thickness of the anti-fuse film 24 is between 3 and 300 nm, which can ensure that the programming voltage is between 5 and 20 volts.
  • the protective ceramic can be formed by a growth method or a deposition method.
  • the growth method refers to combining at least one of the five non-metal elements carbon, nitrogen, oxygen, phosphorus, and sulfur into the surface of the bottom electrode 20.
  • the growth method includes methods such as high temperature oxidation, plasma oxidation, anodization, and ion implantation.
  • the deposition method forms a ceramic material outside the bottom electrode 20.
  • the deposition method includes a direct sputtering method, a reactive sputtering method, a CVD method, or the like. The following uses chromium oxide as an example to introduce these methods.
  • Chromium oxide is formed in an aerobic environment at high temperature, which is similar to the high temperature oxidation of silicon.
  • the thickness of chromium oxide can be controlled by changing the temperature and oxidation time. related Introduction to Materials Science for Engineers, 2nd ed. Pp.607-608, 1998.
  • Plasma oxidation method Chromium oxide is formed in an oxygen plasma at room temperature or high temperature. During the plasma oxidation process, oxygen ions in the plasma have more opportunities to react with chromium. Therefore, the oxidation process takes less time. References on plasma oxidation are
  • Anodizing method There are several methods for anodizing: a. Gaseous anodizing method; b. Liquid anodizing method; c. Solid anodizing method. The following uses gaseous anodization as an example. The glow discharge of oxygen was started, and then a negative voltage was applied to the surface of chromium with respect to the ionized oxygen, so that the oxygen ions were accelerated toward the surface of chromium. Because the oxygen ion is relatively fast, it can penetrate the formed chromium oxide relatively easily and react with the chromium below it. Accordingly, the growth rate of chromium oxide is relatively fast. References on anodizing include
  • Ion implantation method oxygen is implanted on the surface of chromium, and then annealed at high temperature, so that the injected oxygen reacts with chromium to form chromium oxide.
  • One possible method is to use plasma immersion ion implantation (PIII). This process is similar to the process of manufacturing SIMOX. But its ion implantation energy is much smaller, see Yu, et al "Trench doping conformity by plasma immersion ion implantation (PHI)", IEEE Electron Device Letters, 15, no. 6, pp.196-8, 1994.
  • Chromium oxide is formed by sputtering a chromium oxide target in an argon atmosphere. During the sputtering process, hydrogen can also be introduced into the deposition chamber at the same time, which can reduce the density of dangling bonds.
  • Reactive sputtering method A chromium target is used instead of a chromium oxide target in sputtering.
  • the sputtering environment is a mixture of argon and oxygen ions (including hydrogen ions). Chromium reacts with oxygen during sputtering from the target to the substrate and forms chromium oxide.
  • Chromium oxide can be formed using a CVD method similar to that for forming silicon oxide.
  • the reaction gas is introduced into the deposition chamber, and different ions react to form chromium oxide.
  • the combination of the above two or more methods may have different structures. Combining the chromium oxide formed by different methods can improve the uniformity of chromium oxide and reduce its uniformity.
  • the defect density for example, the first layer of chromium oxide film can be formed by high temperature oxidation, and the second layer of chromium oxide film can be formed by CVD method. This way It is very unlikely that the micropores in one layer of chromium oxide film overlap with the micropores in the second layer of chromium oxide film, thereby effectively reducing the defect density.
  • the formation methods of the above-mentioned several protective ceramic materials are all conventional methods in the manufacturing process of semiconductor integrated circuits and superconducting circuits. That is, the manufacturing process of the capacitor-like element of the present invention is compatible with the manufacturing process of the integrated circuit. Therefore, due to the use of the capacitor-like device of the present invention, a field-programmable gate array, a programmable read-only memory, a dynamic memory, and a superconducting circuit with high yield and good durability can be produced by using a standard semiconductor production process.
  • the insulating material 24 does not necessarily contain only one ceramic, and may be formed using a mixed multilayer structure in order to take advantage of different characteristics of different ceramic materials, for example, a layer may be oxidized Chromium is stacked with a layer of silicon oxide to reduce defect density.
  • the bottom electrode 20 In order to improve the yield, in addition to using a protective ceramic material, the bottom electrode 20 should be kept free of foreign particles.
  • the sputtered film may contain a large amount of foreign particles. These particles may damage the anti-fuse film 24. Therefore, the finished product will be reduced. rate.
  • Evaporation on the other hand, is a relatively clean process that introduces less dust. Therefore, an evaporation method can be used to form a portion of the bottom electrode 20, at least a base film of the bottom electrode 20.
  • the top electrode 22 is formed by pattern conversion. It contains a barrier film and a conductive film, and its material and thickness are similar to those of the bottom electrode 20.
  • FIG. 2 is an example in which a protective ceramic material is applied to a storage capacitor in a DRAM.
  • the storage capacitor has a bottom electrode 30, a top electrode 32, and an insulating film 34. Suitable refractory metals include tungsten (W) and platinum (Pt).
  • the bottom electrode 30 may also include a multilayer metal material film.
  • the first layer is an adhesion film, which is composed of titanium nitride (TiN), chromium (Cr), titanium (Ti), and the like.
  • the second layer contains a highly conductive material, such as copper or aluminum, and its thickness is between 100 nm and 1.5 ⁇ m, preferably 600 nm. This film provides a low-resistance path for electrical signals.
  • a blocking film may be provided on the conductive film, and the blocking film contains titanium tungsten alloy (TiW), titanium nitride (TiN), tungsten (W), and the like.
  • TiW titanium tungsten alloy
  • TiN titanium nitride
  • W tungsten
  • the insulating material 34 is formed by oxidizing the upper surface of the bottom electrode 30, a base film is also required.
  • the base film is the uppermost layer of the bottom electrode 30. It contains a metal element for forming a metal oxide, and its thickness is between 5 and 100 nm, preferably 20 nm.
  • the base film needs to be composed of chromium, and the thickness of the entire bottom electrode 30 is between 0.2 and 2 ⁇ m, and preferably 0, 6 ⁇ m.
  • Insulating film 34 may have a multilayer structure, in FIG. 2 3 4a, 34b ... there is at least one layer of protective ceramic.
  • the Pilling-Bedworth ratio of protective ceramics should be greater than 1, preferably less than 2.
  • Some examples are the oxides of Be, Cu, AI, Cr, Mn, Fe, Co, Ni, Pd, Pb, Zn and Ce. They can be manufactured by the method described above, and their thickness is between 2 ⁇ 300nm. Fortunately, it is 10nm.
  • insulating material 34 has a high dielectric constant £. Table 4 gives some protection of the metal oxide dielectric constant £.
  • NiO CoO 50% molar ratio
  • the top electrode 32 is also formed by pattern conversion. It contains a barrier film and a conductive film, and its material and thickness are similar to those of the bottom electrode 30.
  • FIG. 3 shows the application of a protective ceramic material to the Josephson junction in a superconducting circuit.
  • Josephson junction has a bottom electrode 40, a top electrode 42, and an insulating film 44.
  • the bottom electrode 40 includes a superconducting film, and may further include a base film.
  • Superconducting films contain niobium or other superconducting materials. Its thickness is between 50 ⁇ and 1 ⁇ , preferably 300 nm.
  • the base film contains a metal forming a protective ceramic material. Its composition and thickness are similar to those of the base film in FIG. 2.
  • the insulating film 44 is used as a tunnel film, and it contains at least one layer of protective ceramic material with a thickness between 2 and 30 nm, preferably 7 nm. This protective ceramic material can be manufactured by the methods discussed above.
  • the top electrode 42 contains a superconducting material, and its composition and thickness are similar to those of the bottom electrode 40.

Abstract

This invention relates to applications of protective ceramics material to integrated circuits. It is beneficial for an FPGA, PROM, DRAM and superconductive circuit to use a protective ceramic which can densely cover metal surface and is free of defects. As a result, a high yield can be ensured. The Pilling-Bedwirth ratio is a good indicator of the protective nature of an insulating material. It is desirable to limit the Pilling-Bedworth ratio larger than 1 and preferably smaller than 2. Multiple layers of ceramics can be used to further reduce the defect density and improve yield.

Description

保护性陶瓷材料的应用  Application of protective ceramic materials
技术领域 Technical field
本发明属于集成电路领域, 更确切地说, 是关于保护性陶瓷材料在 如下领域中的应用, 包括: 场编程门阵列 ( FPGA ) 和可编程只读存储 器 ( PROM ) 中的反熔丝 ( antifuse ) 、 动态随机存取存储器 ( DRAM ) 的存储电容、 超导电路中的约瑟夫逊( Josephson ) 结等似电 容元件。  The present invention belongs to the field of integrated circuits, and more specifically, relates to the application of protective ceramic materials in the following fields, including: field-programmable gate array (FPGA) and anti-fuse in programmable read-only memory (PROM). ), Storage capacitors of dynamic random access memory (DRAM), Josephson junctions in superconducting circuits, and other capacitor-like elements.
背景技术 Background technique
反熔丝 (antifuse ) 是一个场编程门阵列 (FPGA ) 、 可编程只读存 储器(PROM ) 等使用的场编程元件。 它的结构和电容的结构类似: 有 两个电极和一夹在两个电极之间的绝缘膜。 该绝缘膜也被称为反熔丝 膜, 它使反熔丝在编程前处于一个高电阻的 OFF态, 在加上一个编程电 压和电流之后, 反熔丝被编程到它的 ON态, 并显示低电阻, 从而导致两 个电极之间的电导通。  An antifuse is a field programming element used in a field programming gate array (FPGA), a programmable read-only memory (PROM), and the like. Its structure is similar to that of a capacitor: it has two electrodes and an insulating film sandwiched between the two electrodes. This insulating film is also called anti-fuse film. It puts the anti-fuse in a high-resistance OFF state before programming. After applying a programming voltage and current, the anti-fuse is programmed to its ON state, and Shows low resistance, causing electrical conduction between the two electrodes.
反熔丝的绝缘材料被称作反熔丝材料, 它是反熔丝技术成功的关 键。 在一个 FPGA或 PROM中有上百万个反熔丝, 它们都应表现出相似 的特征, 譬如说, 未编程的反熔丝有小的漏电流。 如果一个未编程的反 熔丝中的漏电流大到使两个电极像导通一样, 这个 FPGA或 PROM就会 展示一个错误的逻辑功能, 从而导致成品率降低。 为了提高成品率, 有 必要保证反熔丝没有缺陷。 如果每个反熔丝的面积是 Ιμπι2, 那么, 一个 FPGA或 PROM中的反熔丝的总面积会超过 lmm2。 因此, 反熔丝材料的 质量要好到至少可以生成缺陷密度小于 1/mm2的似电容元件。 The anti-fuse insulation material is called anti-fuse material, and it is the key to the success of anti-fuse technology. There are millions of antifuse in an FPGA or PROM. They should all show similar characteristics. For example, unprogrammed antifuse has a small leakage current. If the leakage current in an unprogrammed antifuse is so large that the two electrodes appear to be conducting, the FPGA or PROM will exhibit an incorrect logic function, resulting in a reduction in yield. In order to improve the yield, it is necessary to ensure that the antifuse is free from defects. If the area of each antifuse is 1 μm 2 , the total area of the antifuse in an FPGA or PROM will exceed 1 mm 2 . Therefore, the quality of the anti-fuse material is good enough to generate at least a capacitor-like element with a defect density of less than 1 / mm 2 .
金属―金属反熔丝被广泛地研究以应用于下一代的 FPGA和 PROM。 一个主要的问题是要寻找一种高质量的反熔丝材料。 现在, 使 用高温生成的金属氧化物作为反熔丝材料正引起越来越多的兴趣, 如授 予 McCollum等的美国专利 5,070,384 ( 1990年 4月 12日) , 提供了一个使 用氧化钛作为反熔丝材料的反熔丝膜; 授予 Tung等的美国专利 5,347,832 ( 1994年 12月 20日) , 描述了使用氧化钛、 氧化钨作为反熔丝材料的反 熔丝膜。 遗憾的是, 氧化钛、 氧化钨不是保护性氧化物, 因为它们具有 多孔状的结构, 故具有大的缺陷密度( Shackelford, "Introduction to Materials Science for Engineers", 第二版, 609— 610百, 1988年) 。 使 用这些反熔丝材料能否达到可以接受的成品率是有疑问的。 为了达到高 的成品率, 我们需要去寻找一种具有低缺陷密度的反熔丝材料。 Metal-to-metal antifuse has been extensively studied for use in next-generation FPGAs and PROMs. A major problem is to find a high quality antifuse material. At present, the use of high-temperature-produced metal oxides as antifuse materials is attracting increasing interest, such as US Patent 5,070,384 (April 12, 1990) to McCollum et al., Which provides a use of titanium oxide as antifuse Material anti-fuse film; U.S. Patent 5,347,832 to Tung et al. (December 20, 1994) describes the use of titanium oxide and tungsten oxide as anti-fuse materials. Fuse film. Unfortunately, titanium oxide and tungsten oxide are not protective oxides. Because they have a porous structure, they have a large defect density (Shackelford, "Introduction to Materials Science for Engineers", Second Edition, 609-610 hundred, 1988). It is questionable whether these antifuse materials can achieve acceptable yields. To achieve high yields, we need to find an antifuse material with a low defect density.
动态随机存取存储器(DRAM ) 含有存储元阵列。 每个 DRAM的存 储元含有一个存取晶体管和存储电容。 存储电容由两个相对的电极和一 个绝缘膜组成, 数字信息由存储在存取电容上的电荷来表示。  Dynamic random access memory (DRAM) contains an array of memory cells. Each DRAM cell contains an access transistor and a storage capacitor. The storage capacitor consists of two opposite electrodes and an insulating film. Digital information is represented by the charge stored on the access capacitor.
目前, 一个 DRAM芯片含有 256兆比特的信息。 这就意味着在这个 DRAM芯片上有 256兆存储电容。 这些电容都应有类似的特征, 如, 它 们能使足够多的电荷在电极上保持足够长的时间。 如果一个电容的漏电 流太大, 那么, 这些存储的电荷在下一个刷新信号到来之前可能会漏 掉, 因此, 存储的信息会丢失。 为了保证一个 DRAM芯片有适当的功 能, 存储电容的漏电流应该很小、 并可控制和重复。 这个要求应该对 DRAM芯片中的所有存储电容都适用。  Currently, a DRAM chip contains 256 megabits of information. This means that there is a 256 megabyte storage capacitor on this DRAM chip. These capacitors should have similar characteristics, for example, they can hold enough charge on the electrode for a long enough time. If the leakage current of a capacitor is too large, these stored charges may be leaked before the next refresh signal arrives, so the stored information will be lost. To ensure that a DRAM chip has proper function, the leakage current of the storage capacitor should be small, controllable and repeatable. This requirement should apply to all storage capacitors in a DRAM chip.
绝缘材料的完整性是保证每个存储电容的漏电流很小、 并可控制和 重复的关键。 如果绝缘材料上有微孔, 这种缺陷可导致过大的漏电流。 为了保证成品率, DRAM芯片上的绝缘材料的缺陷密度应限制在一定程 度之下。 作为一个简单的估计, 每个存储电容的面积是 2μπι2, 那么, 在 一个千兆比特的 DRAM的芯片上绝缘材料的总面积就会超过 20cm2。 因 此, 即使使用多余存储元的方案, 绝缘膜的缺陷密度也应该低于〜 l/mm2The integrity of the insulating material is the key to ensuring that the leakage current of each storage capacitor is small, controllable and repeatable. If there are micro holes in the insulating material, such defects can lead to excessive leakage currents. In order to ensure the yield, the defect density of the insulating material on the DRAM chip should be limited to a certain degree. As a simple estimate, the area of each storage capacitor is 2 μm 2. Then, the total area of the insulating material on a gigabit DRAM chip will exceed 20 cm 2 . Therefore, even with the scheme of using extra memory cells, the defect density of the insulating film should be lower than ~ l / mm 2 .
氧化硅 /氧化氮 / (氧化物) ( ON(O) ) 已经被用作动态存储器的绝 缘材料。 它的绝缘介质的完整性有很好的纪录。 但是, 氧化硅的介电常 数为 3.9, 比较小。 在 1千兆比特的 DRAM中的存储电容器的电容要求是 在 25 ~ 40fF。 如果 ON ( O )被用作绝缘材料, 一个存储元的电容面积应 该至少是 2μιη2, 另一方面, 每个存储元的面积不超过 0.2μπι2, 因此, 要 同时满足这两个关于电容和存储元面积的要求是很困难的。 所以, 人们 把越来越多的注意力放到介电常数较大、 可以減小电容面积的金属氧化 物上。 一般说来, 金属氧化物的介电常数比较大, 这样使它们适合于作存 储电容的绝缘材料, 在以往的动态存储器的技术中可以发现很多大介电 常数金属氧化物的例子。 授予 Shinriki等的美国专利 4,937,650 ( 1990年 6 月 26日) 和授予 Jones等的美国专利 5,439,840 ( 1995年 8月 8日 )描述了使 用氧化钽( Ta205 ) 、 氧化钛(Ti02 ) 等作为绝缘材料的技术。 但迄今 为止, 仍未见到关于这些材料成功的报导。 其原因是这些材料的缺陷密 度很高。 开始, 人们怀疑这些缺陷是在生产过程中引入的, 但是使用先 进的生产手段并未能解决这个问题。 实际上, 这些缺陷并不是由外因引 起的, 而是由材料本身的内因引起的。 因为氧化钽( Ta205 ) 和氧化钛 ( Ti02 ) 本身是非保护性氧化物, 也就是说, 它们本身就有一个多孔性 的结构 ( . Shackelford, "Introduction to Materials Science for Engineers", 第二版, 609 - 610页, 1988年) 。 因此, 使用上述这些材 料都不能使集成电路达到高的成品率。 Silicon oxide / nitrogen oxide / (oxide) (ON (O)) has been used as an insulating material for dynamic memories. The integrity of its insulating medium is well documented. However, the dielectric constant of silicon oxide is 3.9, which is relatively small. The capacitance requirement of a storage capacitor in a 1 Gigabit DRAM is 25 to 40fF. If ON (O) is used as an insulating material, the capacitance area of a memory cell should be at least 2 μm 2. On the other hand, the area of each memory cell should not exceed 0.2 μm 2. Therefore, it is necessary to satisfy both The requirement of memory cell area is very difficult. Therefore, more and more attention is being paid to metal oxides having a large dielectric constant and reducing the capacitance area. Generally speaking, the dielectric constants of metal oxides are relatively large, so that they are suitable as insulation materials for storage capacitors. Many examples of metal oxides with large dielectric constants can be found in the past technology of dynamic memories. US Patent 4,937,650 to Shinriki et al. (June 26, 1990) and US Patent 5,439,840 to August et al. (August 8, 1995) describe the use of tantalum oxide (Ta 2 0 5 ), titanium oxide (Ti 0 2 ), etc. Technology as an insulating material. To date, no reports of the success of these materials have been seen. The reason is that these materials have a high defect density. At first, people suspected that these defects were introduced during the production process, but the use of advanced production methods did not solve the problem. In fact, these defects are not caused by external factors, but by internal factors of the material itself. Because tantalum oxide (Ta 2 0 5 ) and titanium oxide (Ti0 2 ) are non-protective oxides, that is, they have a porous structure (Shackelford, "Introduction to Materials Science for Engineers", Second edition, 609-610 pages, 1988). Therefore, the use of any of these materials cannot achieve a high yield of integrated circuits.
超导电路有高速、 低能耗等优点, Josephson结是超导电路的关键 元件。 它的结构也与电容类似, 即, 一层薄的绝缘材料被夹在两个超导 材料之间。 这个绝缘材料被用作一个隧道膜。 在现有技术中使用的绝缘 材料是氧化铝 (Α1203 ) , 但如果制造氧化铝的工艺流程没有被优化的 话, Josephson结仍可能含有缺陷。 同时, 在超导电路中我们能找到更多 的适用于超导电路的绝缘材料。 Superconducting circuits have advantages such as high speed and low energy consumption. Josephson junctions are key components of superconducting circuits. Its structure is similar to a capacitor, that is, a thin layer of insulating material is sandwiched between two superconducting materials. This insulating material is used as a tunnel film. The insulating material used in the prior art is alumina (Al 2 0 3 ), but if the process of manufacturing alumina is not optimized, the Josephson junction may still contain defects. At the same time, we can find more insulation materials suitable for superconducting circuits in superconducting circuits.
由上面对现有技术的描述可知, 场编程门阵列 (FPGA ) 、 可编程 只读存储器 (PROM ) 、 动态存储器 (DRAM ) 以及超导电路等的成品 率在很大程度上依赖于绝缘材料的完整性。 如果任何一个反熔丝、 存储 电容器或 Josephson结的漏电流过大, 那么整个芯片的功能就会受到极大 影响。 引起过大漏电流的主要原因是绝缘材料中的微孔, 落入微孔中的 金属微粒会在两个相对的电极之间形成一个电连接。 对 FPGA、 PROM. DRAM和超导电路来说, 理想的绝缘材料应该没有微孔。  From the above description of the prior art, it can be known that the yield of field-programmable gate array (FPGA), programmable read-only memory (PROM), dynamic memory (DRAM), and superconducting circuits depends to a large extent on the insulation material. Integrity. If the leakage current from any one of the antifuse, storage capacitor, or Josephson junction is too large, the function of the entire chip will be greatly affected. The main cause of excessive leakage current is the micropores in the insulating material. The metal particles falling into the micropores will form an electrical connection between two opposite electrodes. For FPGAs, PROM. DRAMs and superconducting circuits, the ideal insulating material should be free of micropores.
为了找到无微孔绝缘材料, 本发明人研究了冶金学鉴定出的一组保 护性覆盖材料。 这些保护性覆盖材料是非多孔性的、 并能密集覆盖住下 面的金属。 侵蚀剂, 如氧, 不能够穿过这些覆盖材料。 于是, 在侵蚀剂 和被保护性覆盖材料覆盖的金属之间没有化学反应。 保证这些覆盖材料 具有保护性的关键因素是它们没有微孔。 因此, 当这些保护性覆盖材料 被用作像 DRAM之类的集成电路中的似电容元件的绝缘材料时, 可以防 止在电极之间流过大的漏电流。 总的说来, 最初在冶金学中发展出的鉴 定保护性覆盖材料的准则, 尤其是鉴定保护性陶瓷的准则, 可以用来作 为鉴定在集成电路中使用的理想绝缘材料的准则。 下面将提供一个关 f 鉴定保护性陶瓷的总述。 这些讨论可以同时应用在冶金学中的保护性覆 盖材料和集成电路中的保护性绝缘材料。 To find microporous insulation materials, the inventors studied a group of protective covering materials identified by metallurgy. These protective covering materials are non-porous and can densely cover the underlying metal. Etching agents, such as oxygen, cannot penetrate these covering materials. There is then no chemical reaction between the etchant and the metal covered by the protective covering material. Guarantee these covering materials The key protective factor is that they do not have micropores. Therefore, when these protective covering materials are used as an insulating material like a capacitor element in an integrated circuit such as a DRAM, a large leakage current can be prevented from flowing between the electrodes. In general, the criteria for the identification of protective covering materials originally developed in metallurgy, especially the criteria for the identification of protective ceramics, can be used as the criteria for the identification of ideal insulating materials for use in integrated circuits. An overview of the identification of protective ceramics is provided below. These discussions can be applied to both protective covering materials in metallurgy and protective insulating materials in integrated circuits.
陶瓷是一种化合物, 它由至少一种金属元素和以下五种非金属元素 (碳、 氮、 氧、 嶙、 硫) 中的至少一种化合而成(表 1 ) 。 这里陶瓷可以 有多晶结构或无定形结构 (无定形陶瓷也被称作玻璃) , 一些陶瓷的例 子是 A1203和 Cr203„ —般说来, 陶瓷是耐熔的, 它们在高温下很稳定。 因此, 它们可以承受集成电路制造工艺中很严酷的生产环境。 Ceramic is a compound that is formed by combining at least one metal element and at least one of the following five non-metal elements (carbon, nitrogen, oxygen, thorium, sulfur) (Table 1). Here ceramics can have a polycrystalline structure or an amorphous structure (amorphous ceramics are also referred to as glass). Some examples of ceramics are A1 2 0 3 and Cr 2 0 3 „In general, ceramics are refractory. They are stable at high temperatures. As a result, they can withstand the harsh production environments of integrated circuit manufacturing processes.
为了鉴定一种陶瓷材料其本身是否具有保护性, 或者说, 该陶瓷材 料是否具有固有保护性, Pilling-Bedworth比 ( Shackelford, In order to determine whether a ceramic material is protective in itself, or whether the ceramic material is inherently protective, Pilling-Bedworth ratio (Shackelford,
"Inroduction to Materials Science for Engineers" , 第二版, 609-610 页, 1988年) 是一个很有用的指标。 一个陶瓷的 Pilling-Bedworth比 R被定 义为该陶瓷的体积和用来形成此陶瓷所用金属体积之比 "Inroduction to Materials Science for Engineers", Second Edition, pages 609-610, 1988) is a useful indicator. The Pilling-Bedworth ratio R of a ceramic is defined as the ratio of the volume of the ceramic to the volume of the metal used to form the ceramic.
_ ― ~—— V陶瓷  _ ― ~ —— V ceramic
V形成此陶瓷所用之金属 如果 R小于 1 , 陶瓷倾向于多孔状, 不能覆盖整个金属表面, 因而不具保护性; 如果 R等于或稍大于 1 , 陶瓷具有保护性; 如果 R 远大于 1 , 陶瓷内会存在着大的压应力, 从而导致陶瓷覆盖层剥落 和裂开。 表 1 在元素周期表中, 陶瓷是由至少一种金属元素 (淡色) 和五种非金属元素 (碳、 氮, 氧、 磷、 硫)(黑色) 中的至少一种化合而成 这里用金属氧化物作一个具体例子来解释怎么利用 Pilling- Bedworth比来鉴定一个金属氧化物的固有保护性。 一个金属氧化物的 Pilling-Bedworth比 R被定义为: 通过金属和氧气反应形成的金属氧化物 的体积与所使用的金属体积之比 If the metal used to form this ceramic is less than 1, the ceramic tends to be porous and cannot cover the entire metal surface, so it is not protective; if R is equal to or slightly greater than 1, the ceramic is protective; if R is much greater than 1, the ceramic There will be large compressive stress, which will cause the ceramic coating to peel and crack. Table 1 In the periodic table, ceramics are formed by combining at least one metal element (light color) and at least one of five non-metal elements (carbon, nitrogen, oxygen, phosphorus, sulfur) (black). Here a metal oxide is used as a specific example to explain how to use Pilling-Bedworth ratio to identify the inherent protection of a metal oxide. The Pilling-Bedworth ratio R of a metal oxide is defined as: the ratio of the volume of metal oxide formed by the reaction of metal and oxygen to the volume of metal used
= Md  = Md
R = amD R = amD
这里, M、 D是金属氧化物 (金属) a (氧) b的分子量和密度, m、 d是金 属的原子量和密度, a是金属氧化物分子式中金属原子的个数。 表 2表示 如何用 Pilling-Bedworth比来鉴定一个金属氧化物的固有保护性。 表 2不同Here, M and D are the molecular weight and density of the metal oxide (metal) a (oxygen) b , m and d are the atomic weight and density of the metal, and a is the number of metal atoms in the metal oxide molecular formula. Table 2 shows how the Pilling-Bedworth ratio can be used to identify the inherent protection of a metal oxide. Table 2 is different
从表 2看, 一般说来, 保护性氧化物的 Pilling-Bedworth比大于 1, 最好是小于 2。 除了 R以外, 还要满足一些別的因素才能够形成保护性氧 化物, 如金属和氧化物之间有相近的热膨胀系数以及金属和氧化物之间 有较好的附着性就是其中的两个因素。 From Table 2, generally speaking, the Pilling-Bedworth ratio of the protective oxide is greater than 1, preferably less than 2. In addition to R, there are other factors that must be met to form protective oxygen. Compounds such as similar thermal expansion coefficients between metals and oxides and good adhesion between metals and oxides are two of the factors.
如果一个金属氧化物不具有固有保护性, 那么, 无论怎样努力来改 善它们的生产流程, 这种金属氧化物也不能在集成电路中被成功地用作 绝缘材料。 这就是为什么氧化钛( Ti02 ) 和氧化钽(Ta205 ) 未能成^ 地使用于 DRAM的原因。 换句话说, 具有固有保护性是一种金属氧化物 另一方面, 当一个金属材料被应用在集成电路中时, 除了这些内在 因素(固有保护性) 外, 一些外在因素也会起到很重要的作用。 这些外 因包括衬底的准备以及氧化物的生产流程。 以下将以氧化硅为例来解释 这些外因的作用。 If a metal oxide is not inherently protective, then no matter how much effort is made to improve their production process, this metal oxide cannot be successfully used as an insulating material in integrated circuits. This is why titanium oxide (Ti0 2 ) and tantalum oxide (Ta 2 0 5 ) have not been successfully used in DRAM. In other words, inherent protection is a metal oxide. On the other hand, when a metal material is used in an integrated circuit, in addition to these inherent factors (intrinsic protection), some external factors will also play a very important role. Important role. These external factors include substrate preparation and oxide production processes. The role of these external factors will be explained below using silicon oxide as an example.
氧化硅已经在集成电路中应用了几十年, 它可能是到目前为止最理 想的绝缘材料。 虽然氧化硅是一个固有的保护性氧化物, 但当用干法生 成氧化硅时, 仍会产生微孔。 通过改变衬底的准备和生产流程可以改善 氧化硅的保护性(完整性) 。 这方面已经发表了很多文章, 如 Offenberg 等建议在生产氧化硅之前利用 UV臭氧来处理硅衬底 (真空科技杂志 A,Vol. 9, N0.3, 第 1058~1065页, 1991年 5月 /6月号) ; Moazzami等利用 堆叠的高温生长 /LPCVD氧化硅来减少微孔密度( "超大规模集成电路 中高盾量叠层热 /LPCVD栅氧化物技术" 1EEE电子器件通讯, Vol. 14, NO. 2, 第 72〜73页, 1993年 2月 ) 。  Silicon oxide has been used in integrated circuits for decades and is probably by far the most ideal insulating material. Although silicon oxide is an inherently protective oxide, micropores are still produced when silicon oxide is produced dry. The protection (integrity) of silicon oxide can be improved by changing the substrate preparation and production processes. Many articles have been published in this regard. For example, Offenberg et al. Suggested that UV ozone be used to treat silicon substrates before producing silicon oxide (Vacuum Science and Technology Magazine A, Vol. 9, N0.3, pages 1058 ~ 1065, May 1991 / June issue); Moazzami et al. Used stacked high-temperature growth / LPCVD silicon oxide to reduce micropore density ("High Shielded Stack Thermal / LPCVD Gate Oxide Technology in VLSI" 1EEE Electronic Device Newsletter, Vol. 14, NO 2, 2, pp. 72-73, February 1993).
以上讨论主要针对的是金属元素的氧化物, 不过此结论对金属合金 的氧化物也成立。 对其它诸如金属的氮化物、 碳化物、 磷化物和硫化 物, 类似的讨论也成立。 表 3给出了多种金属氧化物、 氮化物、 碳化物、 磷化物和硫化物的 Pilling-Bedworth比。 在表 3的下面有一保护性陶瓷的 一览表。 表 3 不同陶瓷材料的 Pilling-Bedworth比 . The above discussion has mainly focused on oxides of metal elements, but this conclusion holds true for oxides of metal alloys. Similar discussions hold for other metals such as nitrides, carbides, phosphides, and sulfides. Table 3 shows the Pilling-Bedworth ratio of various metal oxides, nitrides, carbides, phosphides, and sulfides. Below table 3 is a list of protective ceramics. Table 3.Pilling-Bedworth ratio of different ceramic materials.
(数据来自 "CRC Handbook for Physics and Chemistry" ) (Data from "CRC Handbook for Physics and Chemistry")
*斜体表示非保护性陶瓷材料  * Italics indicate non-protective ceramic materials
固有保护性金属氧化物有 Be, Cu, Al, Si, Cr, Mn, Fe, Co, Ni, Pd, Pb, Ce, Sc, Zn, Zr,Intrinsically protective metal oxides are Be, Cu, Al, Si, Cr, Mn, Fe, Co, Ni, Pd, Pb, Ce, Sc, Zn, Zr,
La, Y, Nb, Rh, Pt等的氧化物。 La, Y, Nb, Rh, Pt and other oxides.
固有保护性金属氮化物有 Ti, V, Cr, Fe, Cu, Zn, Zr, Nb, Ta, Al, Ge等的氮化物' 固有保护性金属碳化物有 Ti, Si, V, Cr, Mn, Fe, Ni, Y, Zr, Nb, Mo, La, Hf, Ta, W, Al等 的碳化物。  Intrinsically protective metal nitrides include nitrides of Ti, V, Cr, Fe, Cu, Zn, Zr, Nb, Ta, Al, Ge, etc. 'Intrinsically protective metal carbides include Ti, Si, V, Cr, Mn, Fe, Ni, Y, Zr, Nb, Mo, La, Hf, Ta, W, Al and other carbides.
固有保护性金属磷化物有 Ti, Fe, Co, Ni, Cu,Cd, Sn等的磷化物。  Intrinsically protective metal phosphides include Ti, Fe, Co, Ni, Cu, Cd, Sn and other phosphides.
固有保护性金属硫化物有 Cu, Ag, In, Sn, TI, Pb, Bi等的硫化物。 发明内容  Intrinsically protective metal sulfides include sulfides of Cu, Ag, In, Sn, TI, Pb, and Bi. Summary of the Invention
本发明的目的是提供一种成品率高且耐久性好的似电容元件; 本发明的又一个目的是提供一种具有成品率高且耐久性好的似电容 元件的集成电路。 The object of the present invention is to provide a capacitor-like element with high yield and good durability; Another object of the present invention is to provide an integrated circuit with a capacitor-like element having high yield and good durability.
上述目的可以通过本发明的似电容元件及集成电路来实现。 本发明 的似电容元件包括: 一由导体构成并具有一上表面的第一底电极、 一由 导体构成的第二顶电极, 以及一位于所述第一底电极和第二顶电级之 的绝缘膜, 其特征在于: 所述绝缘膜含有至少一层保护性陶瓷材料, 该 陶瓷材料是由至少一种金属元素与碳、 氮、 氧、 磷和硫中的至少一种非 金属元素之间的化合物组成的, 本发明的集成电路包括半导体集成电路 和超导集成电路, 所述集成电路中的场编程门阵列或可编程只读存储器 中的反熔丝、 动态随机存取存储器中的电容或存储电容或超导电路中的 约瑟夫逊结为上述似电容元件。  The above object can be achieved by the capacitance-like element and integrated circuit of the present invention. The capacitance-like element of the present invention includes: a first bottom electrode composed of a conductor and having an upper surface, a second top electrode composed of a conductor, and a second electrode disposed between the first bottom electrode and the second top power stage. An insulating film, characterized in that: the insulating film contains at least one layer of protective ceramic material, which is composed of at least one metal element and at least one non-metal element among carbon, nitrogen, oxygen, phosphorus, and sulfur The integrated circuit of the present invention includes a semiconductor integrated circuit and a superconducting integrated circuit. A field programming gate array in the integrated circuit, an anti-fuse in a programmable read-only memory, and a capacitor in a dynamic random access memory. Or the Josephson junction in a storage capacitor or a superconducting circuit is the above-mentioned capacitive element.
由于使用了保护性陶瓷材料作为两电极之间的绝缘材料, 从而可以 提供缺陷密度很低且耐久性好的反熔丝结构、 电容或存储电容、 约瑟夫 逊结等似电容元件。 此外, 本发明的以保护性陶瓷材料作绝缘材料的似 电容元件可以使用标准的半导体制造工艺来生产, 因而可以利用常规的 半导体生产工艺方便地生产出成品率高的场编程门阵列、 可编程只读存 储器、 动态存储器以及超导电路。  Since a protective ceramic material is used as the insulating material between the two electrodes, it can provide anti-fuse structures with low defect density and good durability, capacitors or storage capacitors, and capacitor-like elements such as Josephson junctions. In addition, the capacitor-like element using the protective ceramic material as the insulating material of the present invention can be produced using a standard semiconductor manufacturing process, and thus a conventional semiconductor manufacturing process can be used to conveniently produce a field-programmable gate array with high yield and programmable Read-only memory, dynamic memory, and superconducting circuits.
下面将结合附图描述本发明。  The invention will be described below with reference to the drawings.
图 1是一个将保护性陶瓷材料应用在反熔丝膜中的断面图。  Figure 1 is a cross-sectional view of a protective ceramic material applied to an antifuse film.
图 2是一个将保护性陶瓷材料应用在动态存储器中的存储电容的断 面图。  Figure 2 is a sectional view of a storage capacitor using a protective ceramic material in a dynamic memory.
图 3是一个将保护性陶瓷材料应用在超导电路中的 Josephson结的断 面图。  Figure 3 is a cross-sectional view of a Josephson junction using a protective ceramic material in a superconducting circuit.
最佳实施方式  Best practice
图 1的断面图表示将保护性陶瓷应用在 FPGA和 PROM中的反熔丝 膜。 反熔丝结构有一底电极 20、 顶电极 22和一绝缘的反熔丝膜 24。 熟悉 本专业的技术人员应了解底电极含有金属材料, 这里金属材料是指金属 元素、 金属合金和金属化合物。 底电极 20也可以是一复合膜, 包括粘连 膜、 导通膜、 阻挡膜以及一个基膜。 粘连膜并非必要, 视具体情况而 定。 它通常使用钛( Ti ) 、 氮化钛 (TiN)、 铬 (Cr)或钛钨合金( TiW ) 等, 厚度为 10 ~ lOOnm, 最好是 50nm。 它可以增强底电极 20和其衬底材 料之间的粘连。 导通膜可含一良导体, 譬如说, 铝 (A1 ) 、 银(Ag ) 、 铜 ( Cu ) 或金(Au ) , 其厚度在 100nm ~ 200μιη之间, 最好是 500nm左 右。 它为电信号提供一个好的导电路径。 阻挡膜含有耐熔金属, 譬如 说, 钨 ( W ) 、 ¾ ( Mo ) 、 钛( Ti ) 或钛钨合金 ( TiW ) , 其厚度在 50 ~ 300nm之间, 最好是 100nm。 它保证反熔丝膜 24与导通膜之间在高 温生产流程中不会发生化学反应。 对熟悉本专业的技术人员来说, 阻挡 膜的必要性极大地依赖于导通材料和反熔丝材料之间的反应性。 如果反 熔丝材料在 4501:左右很稳定, 并不和导通材料反应, 那么, 就没有必要 在导通膜和反熔丝膜 24之间使用阻挡膜。 如果反熔丝材料是通过氧化底 电极 20的上表面形成的金属氧化物, 那么, 就需要一个基膜。 这个基膜 在底电极 20的最上层, 它包含有形成此金属氧化物的金属元素。 其厚度 在 5 ~ 100nm之间, 最好是 20nm。 例如, 如果反熔丝材料是高温生长的 氧化铬, 那么, 基膜就需是一层铬( Cr ) 膜。 The cross-sectional view of Figure 1 shows the application of protective ceramics to antifuse films in FPGAs and PROMs. The antifuse structure has a bottom electrode 20, a top electrode 22, and an insulated antifuse film 24. Those skilled in the art should understand that the bottom electrode contains metal materials, where metal materials refer to metal elements, metal alloys, and metal compounds. The bottom electrode 20 may also be a composite film, including an adhesion film, a conductive film, a barrier film, and a base film. An adhesion film is not necessary and depends on the situation. It usually uses titanium (Ti), titanium nitride (TiN), chromium (Cr) or titanium tungsten alloy (TiW) Etc., the thickness is 10 ~ 100nm, preferably 50nm. It can enhance the adhesion between the bottom electrode 20 and its substrate material. The conductive film may contain a good conductor, for example, aluminum (A1), silver (Ag), copper (Cu), or gold (Au), and its thickness is between 100 nm and 200 μm, preferably about 500 nm. It provides a good conductive path for electrical signals. The barrier film contains refractory metal, for example, tungsten (W), ¾ (Mo), titanium (Ti), or titanium tungsten alloy (TiW). The thickness is between 50 and 300 nm, and preferably 100 nm. It ensures that no chemical reaction occurs between the anti-fuse film 24 and the conducting film during the high-temperature production process. For those skilled in the art, the necessity of the barrier film greatly depends on the reactivity between the conductive material and the anti-fuse material. If the anti-fuse material is stable around 4501: and does not react with the conductive material, then there is no need to use a barrier film between the conductive film and the anti-fuse film 24. If the antifuse material is a metal oxide formed by oxidizing the upper surface of the bottom electrode 20, then a base film is required. This base film is the uppermost layer of the bottom electrode 20, and it contains a metal element forming the metal oxide. Its thickness is between 5 and 100 nm, preferably 20 nm. For example, if the antifuse material is chromium oxide grown at a high temperature, the base film needs to be a chromium (Cr) film.
反熔丝膜 24含有一层或多层膜, 在这些膜 24a、 24b…中, 至少有一 层含有保护性陶瓷材料, 其 Pilling-Bedworth比应大于 1, 最好小于 2, 这 些保护性陶瓷材料的例子包括 Be, Cu, Al, Si, Cr, Mn, Co, Ni, Pd, Pb和 Ce 的氧化物。 反熔丝膜 24的厚度在 3 ~ 300nm之间, 这可以保证编程电压在 5 ~ 20伏之间。  The anti-fuse film 24 contains one or more films. Among these films 24a, 24b, at least one layer contains a protective ceramic material, and its Pilling-Bedworth ratio should be greater than 1, preferably less than 2, these protective ceramic materials. Examples include Be, Cu, Al, Si, Cr, Mn, Co, Ni, Pd, Pb, and Ce oxides. The thickness of the anti-fuse film 24 is between 3 and 300 nm, which can ensure that the programming voltage is between 5 and 20 volts.
保护性陶瓷可以通过生长法或沉积法形成。 生长法是指将五种非金 属元素碳、 氮、 氧、 磷、 硫中的至少一种结合到底电极 20的表面之中。 生长法包括高温氧化、 等离子体氧化、 阳极氧化、 离子注入等方法。 而 沉积法在底电极 20外面形成陶瓷材料, 沉积法包括直接溅射、 反应溅 射、 CVD等方法。 下面以氧化铬作为例子, 将这些方法作一筒单介绍。  The protective ceramic can be formed by a growth method or a deposition method. The growth method refers to combining at least one of the five non-metal elements carbon, nitrogen, oxygen, phosphorus, and sulfur into the surface of the bottom electrode 20. The growth method includes methods such as high temperature oxidation, plasma oxidation, anodization, and ion implantation. The deposition method forms a ceramic material outside the bottom electrode 20. The deposition method includes a direct sputtering method, a reactive sputtering method, a CVD method, or the like. The following uses chromium oxide as an example to introduce these methods.
( 1 ) 高温氧化法: 在高温下有氧环境里形成氧化铬, 这类似于硅 的高温氧化。 氧化铬的厚度可以通过改变温度和氧化时间来控制。 有关 Introduction to Materials Science for Engineers, 2nd ed. pp.607-608, 1998。 (1) High temperature oxidation method: Chromium oxide is formed in an aerobic environment at high temperature, which is similar to the high temperature oxidation of silicon. The thickness of chromium oxide can be controlled by changing the temperature and oxidation time. related Introduction to Materials Science for Engineers, 2nd ed. Pp.607-608, 1998.
( 2 ) 等离子氧化法: 在室温或高温下在氧等离子体中形成氧化 铬。 在等离子体氧化过程中, 等离子体中的氧离子有更多机会和铬反 应, 因此, 氧化过程所需时间更少。 关于等离子氧化的参考文献有(2) Plasma oxidation method: Chromium oxide is formed in an oxygen plasma at room temperature or high temperature. During the plasma oxidation process, oxygen ions in the plasma have more opportunities to react with chromium. Therefore, the oxidation process takes less time. References on plasma oxidation are
Masui, et al "Plasma oxidation of Cu, Ti and Ni and photoelectrochemical properties of the oxide layers formed" , Materials Chemistry and Physics, 43_no.3, pp.283-6, 1996。 Masui, et al "Plasma oxidation of Cu, Ti and Ni and photoelectrochemical properties of the oxide layers formed", Materials Chemistry and Physics, 43_no.3, pp.283-6, 1996.
( 3 ) 阳极氧化法: 阳极氧化可以有以下几种办法: a.气态阳极^ 化法; b.液态阳极氧化法; c.固态阳极氧化法。 下面用气态阳极氧化作为 一个例子。 开始使氧进行辉光放电, 然后在铬的表面相对于电离的氧加 一负电压, 从而使氧离子朝铬的表面加速。 因为氧离子速度比较快, 它 可以比较容易地穿透已形成的氧化铬并和其下面的铬发生反应, 相应 地, 氧化铬的生长速度比较快。 有关阳极氧化的参考文献包括 (3) Anodizing method: There are several methods for anodizing: a. Gaseous anodizing method; b. Liquid anodizing method; c. Solid anodizing method. The following uses gaseous anodization as an example. The glow discharge of oxygen was started, and then a negative voltage was applied to the surface of chromium with respect to the ionized oxygen, so that the oxygen ions were accelerated toward the surface of chromium. Because the oxygen ion is relatively fast, it can penetrate the formed chromium oxide relatively easily and react with the chromium below it. Accordingly, the growth rate of chromium oxide is relatively fast. References on anodizing include
Schabowska, et al "Electrical conduction in MIM sandwich structures with AI203 Insulating layers", Thin Solid Films, 75, pp.177-180, 1981。 Schabowska, et al "Electrical conduction in MIM sandwich structures with AI 2 0 3 Insulating layers", Thin Solid Films, 75, pp.177-180, 1981.
( 4 ) 离子注入法: 将氧注入到铬的表面, 然后高温退火, 使注入 的氧和铬发生反应, 以形成氧化铬。 一个可行的方法是使用等离子体浸 入离子注入法(ΡΠΙ ) 。 此过程和制造 SIMOX的过程类似。 但是它的离 子注入能量小得多, 可以参考 Yu, et al "Trench doping conformity by plasma immersion ion implantation (PHI)", IEEE Electron Device Letters, 15, no. 6, pp.196-8, 1994。  (4) Ion implantation method: oxygen is implanted on the surface of chromium, and then annealed at high temperature, so that the injected oxygen reacts with chromium to form chromium oxide. One possible method is to use plasma immersion ion implantation (PIII). This process is similar to the process of manufacturing SIMOX. But its ion implantation energy is much smaller, see Yu, et al "Trench doping conformity by plasma immersion ion implantation (PHI)", IEEE Electron Device Letters, 15, no. 6, pp.196-8, 1994.
( 5 ) 直接溅射法: 氧化铬通过使用氧化铬靶在氩气环境中被溅射 而形成, 在溅射过程中氢也可同时引入沉积室中, 这可以减少悬浮键的 密度。  (5) Direct sputtering method: Chromium oxide is formed by sputtering a chromium oxide target in an argon atmosphere. During the sputtering process, hydrogen can also be introduced into the deposition chamber at the same time, which can reduce the density of dangling bonds.
( 6 ) 反应溅射法: 在溅射中使用铬靶而非氧化铬靶, 溅射环境是 混合氩和氧离子 (也可以包括氢离子) 。 铬在从靶溅射到衬底的过程中 与氧反应, 并形成氧化铬。  (6) Reactive sputtering method: A chromium target is used instead of a chromium oxide target in sputtering. The sputtering environment is a mixture of argon and oxygen ions (including hydrogen ions). Chromium reacts with oxygen during sputtering from the target to the substrate and forms chromium oxide.
( 7 ) CVD法: 氧化铬可以使用类似于形成氧化硅的 CVD方法形 成。 将反应气体引入沉积室, 然后不同的离子反应形成氧化铬。  (7) CVD method: Chromium oxide can be formed using a CVD method similar to that for forming silicon oxide. The reaction gas is introduced into the deposition chamber, and different ions react to form chromium oxide.
( 8 ) 以上两种或两种以上办法的综合: 通过不同方法所形成的氧 化铬可能有不同的结构, 将用不同方法形成的氧化铬结合起来可以改善 氧化铬的均匀性, 同时减少它的缺陷密度, 譬如说, 第一层氧化铬膜可 以通过高温氧化形成, 第二层氧化铬膜可通过 CVD方法形成。 这样, 第 一层氧化铬膜中的微孔和第二层氧化铬膜中的微孔重合的可能性很小, 从而可有效地减少其缺陷密度。 (8) The combination of the above two or more methods: The chromium oxide formed by different methods may have different structures. Combining the chromium oxide formed by different methods can improve the uniformity of chromium oxide and reduce its uniformity. The defect density, for example, the first layer of chromium oxide film can be formed by high temperature oxidation, and the second layer of chromium oxide film can be formed by CVD method. This way It is very unlikely that the micropores in one layer of chromium oxide film overlap with the micropores in the second layer of chromium oxide film, thereby effectively reducing the defect density.
上述几种保护性陶瓷材料的形成方法均为半导体体集成电路及超导 电路制造工艺中常规的方法。 也就是说, 本发明的似电容元件的制造工 艺与集成电路的制造工艺兼容。 因此, 由于使用了本发明的似电容 件, 用标准的半导体生产流程即可以生产出成品率高且耐久性好的场编 程门阵列、 可编程只读存储器、 动态存储器以及超导电路。  The formation methods of the above-mentioned several protective ceramic materials are all conventional methods in the manufacturing process of semiconductor integrated circuits and superconducting circuits. That is, the manufacturing process of the capacitor-like element of the present invention is compatible with the manufacturing process of the integrated circuit. Therefore, due to the use of the capacitor-like device of the present invention, a field-programmable gate array, a programmable read-only memory, a dynamic memory, and a superconducting circuit with high yield and good durability can be produced by using a standard semiconductor production process.
熟悉本领域的普通技术人员应意识到, 绝缘材料 24并不一定要只含 有一种陶瓷, 可以使用一个混合多层结构来形成, 以便利用不同陶瓷材 料的不同特性, 例如, 可以将一层氧化铬和一层氧化硅叠在一起以减少 缺陷密度。  Those of ordinary skill in the art should realize that the insulating material 24 does not necessarily contain only one ceramic, and may be formed using a mixed multilayer structure in order to take advantage of different characteristics of different ceramic materials, for example, a layer may be oxidized Chromium is stacked with a layer of silicon oxide to reduce defect density.
为了改善成品率, 除了使用保护性陶瓷材料外, 底电极 20应保持没 有外来微尘, 溅射膜可能含有大量外来微尘, 这些微尘可能会损伤反熔 丝膜 24, 因此, 会降低成品率。 另一方面, 蒸发是一个比较干净的工艺 方法, 它引入的微尘较小。 所以可以使用蒸发法来形成一部分底电极 20, 至少是底电极 20的基膜。  In order to improve the yield, in addition to using a protective ceramic material, the bottom electrode 20 should be kept free of foreign particles. The sputtered film may contain a large amount of foreign particles. These particles may damage the anti-fuse film 24. Therefore, the finished product will be reduced. rate. Evaporation, on the other hand, is a relatively clean process that introduces less dust. Therefore, an evaporation method can be used to form a portion of the bottom electrode 20, at least a base film of the bottom electrode 20.
在形成反熔丝膜 24之后, 沉积一层金属材料, 然后顶电极 22通过图 形转换形成, 它含有阻挡膜和导通膜, 其材料和厚度与底电极 20类似。  After the antifuse film 24 is formed, a layer of metal material is deposited, and then the top electrode 22 is formed by pattern conversion. It contains a barrier film and a conductive film, and its material and thickness are similar to those of the bottom electrode 20.
图 2为将保护性陶瓷材料应用在 DRAM中的存储电容中的例子。 此 存储电容有一底电极 30、 顶电极 32以及绝缘膜 34。 适合的耐熔金属包括 钨( W ) 和铂 ( Pt ) 等。 底电极 30也可以含有多层金属材料膜, 譬如 说, 第一层是粘连膜, 它由氮化钛(TiN ) 、 铬(Cr ) 、 钛 (Ti)等物质組 成。 第二层含有高导电率的材料, 譬如说, 铜或铝, 其厚度在 100nm ~ 1.5μπι之间, 最好是 600nm。 这一层膜为电信号提供一个低电阻的通路。 在导通膜上面可以有一阻挡膜, 这阻挡膜含有钛钨合金( TiW ) 、 氮化 钛(TiN ) 和钨( W ) 等。 如果说绝缘材料 34是通过氧化底电极 30的上 表面来形成, 那么, 还需要一个基膜。 基膜在底电极 30的最上层, 它含 有用来形成金属氧化物的金属元素, 其厚度在 5 ~ lOOnm之间, 最好是 20nm。 譬如说, 当绝缘膜 34是高温生成的氧化铬时, 那么, 基膜需要由 铬构成, 整个底电极 30的厚度在 0.2 ~ 2μιη之间, 最好是 0,6μιη。 绝缘膜 34可以有多层结构, 在图 2中的 34a、 34b…中至少有一层是 保护性陶瓷。 保护性陶瓷的 Pilling-Bedworth比应大于 1, 最好是小于 2。 一些例子是 Be, Cu, AI, Cr, Mn, Fe, Co, Ni, Pd, Pb, Zn和 Ce的氧化物, 它 们可以用前面所说的方法制造, 其厚度在 2 ~ 300nm之间, 最好是 10nm。 对 DRAM来说, 我们希望绝缘材料 34有高的介电常数£。 表 4给出 了一些保护性金属氧化物的介电常数£。 很明显, 对 DRAM来说, NiO CoO ( 50%摩尔比) 是绝缘材料的一个好选择。 FIG. 2 is an example in which a protective ceramic material is applied to a storage capacitor in a DRAM. The storage capacitor has a bottom electrode 30, a top electrode 32, and an insulating film 34. Suitable refractory metals include tungsten (W) and platinum (Pt). The bottom electrode 30 may also include a multilayer metal material film. For example, the first layer is an adhesion film, which is composed of titanium nitride (TiN), chromium (Cr), titanium (Ti), and the like. The second layer contains a highly conductive material, such as copper or aluminum, and its thickness is between 100 nm and 1.5 μm, preferably 600 nm. This film provides a low-resistance path for electrical signals. A blocking film may be provided on the conductive film, and the blocking film contains titanium tungsten alloy (TiW), titanium nitride (TiN), tungsten (W), and the like. If the insulating material 34 is formed by oxidizing the upper surface of the bottom electrode 30, a base film is also required. The base film is the uppermost layer of the bottom electrode 30. It contains a metal element for forming a metal oxide, and its thickness is between 5 and 100 nm, preferably 20 nm. For example, when the insulating film 34 is chromium oxide generated at a high temperature, then the base film needs to be composed of chromium, and the thickness of the entire bottom electrode 30 is between 0.2 and 2 μm, and preferably 0, 6 μm. Insulating film 34 may have a multilayer structure, in FIG. 2 3 4a, 34b ... there is at least one layer of protective ceramic. The Pilling-Bedworth ratio of protective ceramics should be greater than 1, preferably less than 2. Some examples are the oxides of Be, Cu, AI, Cr, Mn, Fe, Co, Ni, Pd, Pb, Zn and Ce. They can be manufactured by the method described above, and their thickness is between 2 ~ 300nm. Fortunately, it is 10nm. For DRAM, we hope insulating material 34 has a high dielectric constant £. Table 4 gives some protection of the metal oxide dielectric constant £. Obviously, for DRAM, NiO CoO (50% molar ratio) is a good choice for insulating materials.
在形成绝缘膜 34之后, 顶电极 32也通过图形转换形成, 它含有阻挡 膜和导通膜, 其材料和厚度与底电极 30类似。  After the insulating film 34 is formed, the top electrode 32 is also formed by pattern conversion. It contains a barrier film and a conductive film, and its material and thickness are similar to those of the bottom electrode 30.
图 3表示保护性陶瓷材料在超导电路中的 Josephson结中的应用。 如 图所示, Josephson结有一底电极 40、 顶电极 42以及绝缘膜 44。 底电极 40 含有超导膜, 还可以含有基膜。 超导膜含有铌或其它超导材料。 其厚度 在 50ηιη~1μιη之间, 最好是 300nm。 基膜含有形成保护性陶瓷材料的金 属。 它的組成和厚度与图 2中的基膜类似。 绝缘膜 44被用作隧道膜, 它含 有至少一层保护性陶瓷材料, 其厚度在 2 ~ 30nm之间, 最好是 7nm。 此 保护性陶瓷材料可以用以上讨论的方法制造。 顶电极 42含有超导材料, 它的組成和厚度与底电极 40类似。 Figure 3 shows the application of a protective ceramic material to the Josephson junction in a superconducting circuit. As shown, Josephson junction has a bottom electrode 40, a top electrode 42, and an insulating film 44. The bottom electrode 40 includes a superconducting film, and may further include a base film. Superconducting films contain niobium or other superconducting materials. Its thickness is between 50 ηη and 1 μιη, preferably 300 nm. The base film contains a metal forming a protective ceramic material. Its composition and thickness are similar to those of the base film in FIG. 2. The insulating film 44 is used as a tunnel film, and it contains at least one layer of protective ceramic material with a thickness between 2 and 30 nm, preferably 7 nm. This protective ceramic material can be manufactured by the methods discussed above. The top electrode 42 contains a superconducting material, and its composition and thickness are similar to those of the bottom electrode 40.
虽然以上具体描述了本发明的一些实施例, 但这些实施例并不意味 着对本发明的限制。 本领域的普通技术人员应该了解, 在不远离本发明 的精神和范围的前提下, 可以对本发明的形式和细节进行改动。 除了根 据附加的权利要求书的精神, 本发明不应受到任何限制。 表 4几种保护性金属氧化物的介电常 ¾ (数据来自 "Dielectric data and loss data" Although some embodiments of the present invention have been specifically described above, these embodiments are not meant to limit the present invention. Those of ordinary skill in the art should understand that the form and details of the present invention can be modified without departing from the spirit and scope of the present invention. Except in accordance with the spirit of the appended claims, the invention should not be limited in any way. Table 4 Dielectric constants of several protective metal oxides (data from "Dielectric data and loss data"

Claims

权 利 要 求 Rights request
1. 一种集成电.路中的似电容元件, 包括: 一具有一上表面的第 ' 一底电极、 一第二顶电极, 以及一位于所述第一底电极和第二顶电 极之间的绝缘膜, 其特征在于: 所述绝缘膜含有至少一层保护性陶 瓷材料, 该陶瓷材料含有至少一种金属元素与碳、 氮、 氧、 磷和硫 中的至少一种非金属元素之间的化合凇。 1. A capacitor-like element in an integrated circuit, comprising: a first bottom electrode having a top surface, a second top electrode, and a first bottom electrode and a second top electrode The insulating film is characterized in that: the insulating film contains at least one protective ceramic material, the ceramic material contains at least one metal element and at least one non-metal element among carbon, nitrogen, oxygen, phosphorus, and sulfur的 合 合 凇.
2. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料的 Pilling-Bedworth比大于 1。  2. The capacitor-like element according to claim 1, wherein a Pilling-Bedworth ratio of the protective ceramic material is greater than one.
3. 根据权利要求 2所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料的 Pilling-Bedworth比小于 2。  3. The capacitor-like element according to claim 2, wherein a Pilling-Bedworth ratio of the protective ceramic material is less than 2.
4. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料是金属氧化物。  4. The capacitor-like element according to claim 1, wherein the protective ceramic material is a metal oxide.
5. 根据权利要求 4所述的似电容元件, 其特征在于: 所述金属 氧化物是 Be、 Cu、 AL Cr、 Mn、 Fe、 Co、 Ni、 Pd、 Pb、 Ce、 Sc、 Zn、 Zr、 La、 Y、 Nb、 Rh和 Pt中至少一种元素的氧化物。  5. The capacitance-like element according to claim 4, wherein the metal oxide is Be, Cu, AL Cr, Mn, Fe, Co, Ni, Pd, Pb, Ce, Sc, Zn, Zr, An oxide of at least one of La, Y, Nb, Rh and Pt.
6. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料是金属氮化物。  6. The capacitor-like element according to claim 1, wherein the protective ceramic material is a metal nitride.
7. 根据权利要求 6所述的似电容元件, 其特征在于: 所述金属 氮化物是 Ti、 V、 Cr、 Fe、 Cu、 Zn、 Zr、 Nb、 Ta、 Al和 Ge中的至 少一种元素的氮化物。  7. The capacitance-like element according to claim 6, wherein the metal nitride is at least one element of Ti, V, Cr, Fe, Cu, Zn, Zr, Nb, Ta, Al, and Ge Of nitride.
8. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料是金属碳化物。  8. The capacitor-like element according to claim 1, wherein the protective ceramic material is a metal carbide.
9. 根据权利要求 8所述的似电容元件, 其特征在于: 所述金属 碳化物是 Ti、 Si、 V、 Cr、 Mn、 Fe、 Ni、 Y、 Zr、 Nb、 Mo、 La、 Hf、 Ta、 \V和 Al中的至少一种元素的碳化物。  9. The capacitance-like element according to claim 8, wherein the metal carbide is Ti, Si, V, Cr, Mn, Fe, Ni, Y, Zr, Nb, Mo, La, Hf, Ta Carbide of at least one of the elements \ V and Al.
10. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料是金属嶙化物。  10. The capacitor-like element according to claim 1, wherein the protective ceramic material is a metal halide.
11. 根据权利要求 10所述的似电容元件, 其特征在于: 所述金 属磷化物是 Ti、 Fe、 Co. Ni、 Cu、 Cd和 Sn中至少一种元素的磷化 物。 11. The capacitor-like element according to claim 10, wherein: the gold The metal phosphide is a phosphide of at least one element of Ti, Fe, Co. Ni, Cu, Cd, and Sn.
12. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 ' 性陶瓷材料是金属硫化物。  12. The capacitor-like element according to claim 1, wherein the protective ceramic material is a metal sulfide.
13. 根据权利要求 12所述的似电容元件, 其特征在于: 所述金 属硫化物是 Cu、 Ag、 In, Sn、 Tl、 Pb和 Bi中的至少一种元素的硫 化物。  13. The capacitance-like element according to claim 12, wherein the metal sulfide is a sulfide of at least one element of Cu, Ag, In, Sn, Tl, Pb, and Bi.
14. 根据权利要求 1所述的似电容元件, 其特征在于: 所述第一 底电极的上表面至少包括一种金属元素, 所述金属元素是組成所述 保护性陶瓷材料的一种元素, 此保护性陶瓷材料中至少一部分用生 长法形成, 以及, 在生长过程中, 碳、 氮、 氧、 磷、 硫中至少一种 元素被结合到所述第一底电极的上表面。 '  14. The capacitor-like element according to claim 1, wherein: the upper surface of the first bottom electrode includes at least one metal element, and the metal element is an element constituting the protective ceramic material, At least a portion of the protective ceramic material is formed by a growth method, and during the growth process, at least one element of carbon, nitrogen, oxygen, phosphorus, and sulfur is bonded to the upper surface of the first bottom electrode. '
15. 根据权利要求 14所述的似电容元件, 其特征在于: 所述保 护性陶瓷材料是金属氧化物; 以及所述第一底电极的上表面含有 Be, Cu、 Al、 Cr、 Mn、 Fe、 Co、 Ni、 Pd、 Pb、 Ce、 Sc、 Zn、 Zr、 La、 Y、 Nb、 Rh和 Pt中的至少一种金属元素。  15. The capacitor-like element according to claim 14, wherein: the protective ceramic material is a metal oxide; and the upper surface of the first bottom electrode contains Be, Cu, Al, Cr, Mn, Fe , Co, Ni, Pd, Pb, Ce, Sc, Zn, Zr, La, Y, Nb, Rh, and Pt.
16. 根据权利要求 14所述的似电容元件, 其特征在于: 所述保 护性陶瓷材料是金属氮化物; 所迷第一底电极的上表面含有 Ti、 V、 Cr、 Fe、 Cu、 Zn、 Zr、 Nb、 Ta、 Al和 Ge中的至少一种金属元素。 16. The capacitor-like element according to claim 14, wherein: the protective ceramic material is a metal nitride; and an upper surface of the first bottom electrode contains Ti, V, Cr, Fe, Cu, Zn, At least one metal element of Zr, Nb, Ta, Al, and Ge.
17. 根据权利要求 14所述的似电容元件, 其特征在于所述生长 法包括: 高温氧化、 高温氮化、 等离子氧化、 等离子氮化、 阳极氧 化和离子注入法。 17. The capacitor-like element according to claim 14, wherein the growth method comprises: high-temperature oxidation, high-temperature nitridation, plasma oxidation, plasma nitridation, anodic oxidation, and ion implantation.
18. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料至少有一部分是由沉积法形成的, 以及, 在沉积过程中, 所述保护性陶瓷材料形成在第一底电极上。  18. The capacitor-like element according to claim 1, wherein: at least a portion of the protective ceramic material is formed by a deposition method, and during the deposition process, the protective ceramic material is formed on a first On the bottom electrode.
19. 根据权利要求 18所述的似电容元件, 其特征在于: 所述沉 积法包括: 直接溅射、 反应溅射和 CVD法。  19. The capacitance-like element according to claim 18, wherein the deposition method comprises a direct sputtering method, a reactive sputtering method, and a CVD method.
20. 根据权利要求 1所述的似电容元件, 其特征在于: 所述第一 电极至少有一部分是由蒸发法形成的。 20. The capacitor-like element according to claim 1, wherein at least a part of the first electrode is formed by an evaporation method.
21. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料具有多晶结构。 21. The capacitor-like element according to claim 1, wherein the protective ceramic material has a polycrystalline structure.
22. 根据权利要求 1所述的似电容元件, 其特征在于: 所述保护 性陶瓷材料具有无定形结构。  22. The capacitor-like element according to claim 1, wherein the protective ceramic material has an amorphous structure.
23. 一种半导体集成电路, 其特征在于: 所述集成电路中的场编 程门阵列或可编程只读存储器中的反熔丝为权利要求 1所述的似电 容元件。  23. A semiconductor integrated circuit, characterized in that: a field-programmable gate array or an anti-fuse in a programmable read-only memory in the integrated circuit is the capacitor-like element according to claim 1.
24. —种半导体集成电路, 其特征在于: 其动态随机存取存储器 中的存储电容为权利要求 1所述的似电容元件。  24. A semiconductor integrated circuit, characterized in that the storage capacitor in the dynamic random access memory is the capacitor-like element according to claim 1.
25. 一种半导体集成电路, 其特征在于: 所述集成电路中的电容 为权利要求 1的似电容元件。  25. A semiconductor integrated circuit, characterized in that the capacitance in the integrated circuit is the capacitance-like element of claim 1.
26. 一种超导电路, 其特征在于: 所述超导电路中的约瑟夫逊结 为权利要求 1的似电容元件。  26. A superconducting circuit, characterized in that: the Josephson junction in the superconducting circuit is the capacitance-like element of claim 1.
27. —种集成电路中的似电容元件, 包括: 一由导体构成的第一 底电极; 一由导体构成的第二顶电极; 以及一位于第一底电极和第 二顶电极之间的介廣膜, 其特征在于: 所述介质膜含有至少一层保 护性陶瓷材料, 该陶瓷材料包括至少一种金属元素与碳、 氮、 氧、 磷和硫中的至少一非金属元素之间的化合物; 所述介质膜的缺陷密 度小于 1/mm2. 27. A capacitor-like element in an integrated circuit, comprising: a first bottom electrode composed of a conductor; a second top electrode composed of a conductor; and a dielectric between the first bottom electrode and the second top electrode Wide film, characterized in that: the dielectric film contains at least one layer of protective ceramic material, the ceramic material includes a compound between at least one metal element and at least one non-metal element among carbon, nitrogen, oxygen, phosphorus and sulfur ; The dielectric film has a defect density of less than 1 / mm 2 .
28. —种集成电路中的似电容元件, 包括: 一由导体构成的第一 底电极; 一由导体构成的第二顶电极; 以及一位于第一底电极和第 二顶电极之间的介质膜, 其特征在于: 所述介质膜含有至少一层保 护性陶瓷材料, 该陶瓷材料包括至少一种金属元素与碳、 氮、 氧、 磷和硫中的至少一非金属元素之间的化合物; 所述介质膜的厚度小 于 180mm.  28. A capacitor-like element in an integrated circuit, comprising: a first bottom electrode composed of a conductor; a second top electrode composed of a conductor; and a dielectric between the first bottom electrode and the second top electrode The film is characterized in that: the dielectric film contains at least one protective ceramic material, the ceramic material includes a compound between at least one metal element and at least one non-metal element among carbon, nitrogen, oxygen, phosphorus and sulfur; The thickness of the dielectric film is less than 180mm.
29. 一种集成电路中的似电容元件, 包括: 一由导体构成的第一 底电极; 一由导体构成的第二顶电极; 以及一位于第一底电极和第 二顶电极之间的介质膜, 其特征在于: 所述介质膜含有至少一层保 护性陶瓷材料, 该陶瓷材料包括至少一种金属元素与碳、 氮、 氧、 磷和硫中的至少一非金属元素之间的化合物; 所述介质膜的缺陷密 度小于 1/mm2以及所述保护性陶瓷材料的厚度小于 300nm。 29. A capacitor-like element in an integrated circuit, comprising: a first bottom electrode composed of a conductor; a second top electrode composed of a conductor; and a dielectric between the first bottom electrode and the second top electrode The film is characterized in that: the dielectric film contains at least one protective ceramic material, the ceramic material includes at least one metal element and carbon, nitrogen, oxygen, A compound between at least one non-metal element in phosphorus and sulfur; a defect density of the dielectric film is less than 1 / mm 2 and a thickness of the protective ceramic material is less than 300 nm.
30. 根据权利要求 27、 28、 29中任一项所述的似电容元件, 其特 征在于: 所述保护性陶瓷材料 Pilling- Bedworth比大于 1。  30. The capacitive-like element according to any one of claims 27, 28, and 29, wherein the protective ceramic material has a Pilling-Bedworth ratio greater than one.
31. 根据权利要求 30所述的似电容元件, 其特征在于: 所述保 护性陶瓷材料 Pilling- Bedworth比小于 2。  31. The capacitor-like element according to claim 30, wherein a Pilling-Bedworth ratio of the protective ceramic material is less than two.
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