WO2000013335A1

WO2000013335A1 - Scaled impedance replica for echo attenuation in digital transmission systems

Info

Publication number: WO2000013335A1
Application number: PCT/EP1999/006210
Authority: WO
Inventors: Thomas Blon; Martin GRÖPL; Michael Moyal; Daniel M. Joffe
Original assignee: Infineon Technologies Ag; Adtran Inc.
Priority date: 1998-08-31
Filing date: 1999-08-24
Publication date: 2000-03-09
Also published as: JP4340012B2; KR100429673B1; EP1110332B1; JP2002524910A; ATE262755T1; DE69915844T2; CN1174560C; US6542604B1; DE69915844D1; CN1317173A; EP1110332A1; KR20010099635A

Abstract

A device for echo attenuation in a digital transmission system comprises an impedance replica of the transmission path, wherein the impedance replica consists of a terminating resistor replica, a transformer replica and a transmission line replica. Further the device can comprise an additional bridged tap replica. The transformer replica and the bridged tap replica are located on chip and the main transformer inductance replica and all components of the bridged tap replica are made variable so that a software setting is possible.

Description

Scaled Impedance Replica For Echo Attenuation In Digital Transmission Systems

BACKGROUND OF THE INVENTION

In semiconductor based digital transmission systems like ISDN or XDSL, transmit and receive signals are being carried on the same pair of wire from location A to B. As long as no special precautions have been made the received signal, m the following named far end signal, is overlaid by the signal of the own transmitter, called echo. This has two disadvantages :

a) The receive path input has to be designed for high input levels. Therefore the possible signal to noise ratio (S/N) is limited.

b) In conventional ISDN and XDSL transmission systems you can find digital linear echo compensators after the analog receive path. This echo compensator is not able to subtract nonlinear distortion components from the echo. Thus the signal to distortion ratio (S/D) has to be kept very low.

To overcome the above mentioned problems a scaled impedance replica of the transmission path consisting of resistors, capacitors and inductors has been provided outside a transmission/receiver chip. The impedance replica delivers a signal which is nearly identical to the echo of the real tx- path. Since the signal of the real transmission line contains the echo plus the far end signal, the far end signal can be isolated by subtracting the replica signal from the signal on the real transmission line (=echo attenuation) . An important prerequisite for high echo attenuation is to provide an exact impedance replica. Since different loops are used to set up a transmission channel a possibility has to be provided to trim the impedance replica. This would always need a few pins at the semiconductor chip to hook in or hook out some of the passive components in the replica network. The increased pin count is one major disadvantage beside the necessity of external passive components attached to the chip. Up to now the external impedance replica is a compromise solution which provides reasonable echo attenuation only at a few test loops .

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a method and a device which can provide reasonable echo at- tenuation

This object is attained by means of the features in the independent claims. Preferred embodiments are subject of the dependent claims.

Pursuant to this object, and others which will become apparent hereafter, one aspect of the invention resides in a device for echo attenuation in a digital transmission system using an impedance replica of the transmission path, wherein the impedance replica consists of a terminating resistor replica, a transformer replica and a transmission line replica.

Further the device can comprise an additional bridged tap replica. The bridged tap replica is connected in parallel be- tween the replica tip and ring lines. Further the bridged tap replica comprises an inductance, a capacitance and a resistance connected in series, wherein preferably the inductance, the capacitance as well as the resistance are adjustable. Preferably the transformer replica comprises a primary wind^¬ ing resistance replica, a secondary winding resistance replica, a transformer main inductance replica and a transformer stray inductance replica, wherein the transformer main induc- tance replica is preferably variable. Further the transformer main inductance replica is connected in parallel between the replica tap and ring lines whereas the primary winding resistance replica, the secondary winding resistance replica, and the transformer stray inductance replica are serial compo- nents of the replica loop.

Further the invention resides in a receiver/transmitter device of a digital transmission system comprising a device for echo attenuation just described, wherein the signal of the transmission loop and the signal of the replica loop are fed into a subtractor of the receiver/transmitter device to remove the echo signal. The pure echo signal is established by connecting the device for echo attenuation, i.e. the replica loop, to the tip and ring terminals of the receiver/trans- mitter device in front of the terminating resistors.

Preferably the transformer replica is an on chip component of the receiver/transmitter chip. Further the bridged tap replica can be an on chip component of the receiver/transmitter chip. Thus the values of the components of the bridged tap replica and the main transformer inductance replica, which are adjustable, can be set by programming the receiver/transmitter chip.

Further it is possible to integrate the terminating resistor replica and the transmission line replica on the receiver/transmitter chip.

BRIEF DESCRIPTION OF THE DRAWINGS A preferred embodiment of the invention is described below with reference to the accompanying drawing. The drawing show:

Fig. 1 A schematic circuit diagram of the receiver/trans- mitter chip comprising the device for echo attenuation.

DETAILED DESCRIPTION OF THE INVENTION

The receiver/transmitter chip (surrounded by the bold line) comprises a line driver LD for driving the tip and ring signal lines TTIP and TRING. The digital transmission system comprises the terminating resistor R and R, a transformer T, and a loop L. Signals are sent to the loop L via the tip and ring signal lines TTIP and TRING. A signal received from the loop by the receiver/transmitter chip RTC is fed into the chip by signal lines RTIP and RRING connected to the tip and ring lines TTIP, TRING in front of the terminating resistors R, R. The received signals are fed into an element AGC of the chip RTC functioning as a subtractor.

Because the received far end signals are superimposed by echo signals generated by the transmission of signals by the line driver LD, it is necessary to remove the echo signal. This is accomplished by generating artificial or replica echo signals and subtract them from the received sum of far end signals and echo signals. The impedance replica comprises a replica transmit tip line RTTIP and a replica transmit ring line RTRING connected to a transformer replica, a bridged tap replica and a signal loop replica (cable replica) .

The characteristics of the transformer T are reproduced by the transformer replica consisting of a primary winding resistance replica RW1, a secondary winding resistance replica RW2, a transformer main inductance replica LXF and a trans- former stray inductance replica LS, wherein the transformer main inductance replica LXF is adjustable.

The bridged tap replica consists of an inductance replica LBT, a capacitance replica CBT and a resistance replica YBT in series. Each component of the bridged tap replica is adjustable .

The cable replica or transmission line replica consists of a plurality of RC-components RTLl, CTLl, RTL2, CTL2, RTL3, CTL3 and RTL4. The off chip RC-ladder hooked to the Pins HYB3 and

HYB4 is a replica for the input impedance of 15 ft AWG26 cable .

Further the circuit comprises terminating resistor replicas RT, RT.

The replica echo signal is fed via lines RRTIP and RRRING to the subtractor AGC. After subtracting the replica echo signal from the received signal of the real transmission, formed by the sum of the echo signal and the far end signal, the far end signal is provided.

The on chip part of the impedance replica consists of the transformer replica and bridged tap replica components wherein the adjustable parts of the transformer and bridged tap replicas can be set by software.

The attached example shows a realization of the „Scaled Iirt- pedance Replica for Echo Attenuation in Digital Transmission Systems" which is optimized to work at ANSI-ISDN test loops. If the bridged tap replica is disabled the impedance replica consisting of the remaining on and off chip components matches very well the impedance of ANSI-ISDN loops without bridged taps near to the line input. For loops with bridged taps near to the line input adequate adjusting of LBT, YBT and CBT provides good impedance matching also for this case.

All integrated inductors are realized as gyrators. LXF can be trimmed to match varying main inductances of the transformer in the transmission path.

As summary the external compromise impedance replica has been replaced by a nearly fully integrated impedance replica taking each component of the transmission system detailed into account. With the integration of the most important impedance components it is possible to trim the impedance replica in a way that it can match various transmission loops providing very good echo attenuation.

Claims

1. Device for echo attenuation in a digital transmission system using an impedance replica of the transmission path, characterized in that the impedance replica consists of a terminating resistor replica (RT, RT) , a transformer replica (RW1, RW2, LS, LXF) and a transmission line replica (RTLl, CTLl, RTL2, CTL2, RTL3, CTL3, RTL4, CTL4) .

2. Device according to claim 1 comprising an additional bridged tap replica (LBT, YBT, CBT) .

3. Device according to claim 2, characterized in that the bridged tap replica is connected in parallel between the replica tap and ring lines (RTTIP, RTRING) .

4 Device according to claim 3, characterized in that the bridged tap replica comprises an inductance (LBT; a capacitance (CBT) and a resistance (YBT) in series.

5. Device according to claim 4, characterized in that the inductance (LBT), the capacitance (CBT) and the resistance (YBT) are adjustable.

6. Device according to one of the preceding claims, characterized in that the transformer replica comprises a primary winding resistance replica (RW1), a secondary winding resistance replica (RW2), a transformer main inductance replica (LXF) and a transformer stray inductance replica (LS) .

7. Device according to claim 6, characterized in that the transformer main inductance replica (LXF) is variable.

8. Device according to claim 6 or 7, characterized in that the transformer main inductance replica (LXF) is connected in parallel between the replica tap and ring lines (RTTIP, RTRING) whereas the primary winding resistance replica (RW1), the secondary winding resistance replica

(RW2), and the transformer stray inductance replica (LS) are serial components of the replica loop.

9. Receiver/transmitter device (RTC) of a digital transmission system comprising a device for echo attenuation according to one of the claims 1 - 8 wherein the signal of the transmission loop and the replica signal are fed into a subtractor (AGC) of the receiver/transmitter device (RTC) .

10. Device according to claim 9, characterized in that the transformer replica (RW1, RW2, LS, LXF) is an on chip component of the receiver/transmitter chip (MDSL-A) .

11. Device according to one of the claims 9 or 10, characterized in that the bridged tap replica (LBT, YBT, CBT) is an on chip component of the receiver/transmitter chip.

12. Device according to one of the claims 9 to 11, characterized in that the terminating resistor replica (RT, RT) and the transmission line replica (RTLl, CTLl, RTL2, CTL2, RTL3, CTL3, RTL4 ) are on chip components of the receiver/transmitter chip.