WO2000013197A1 - Ensemble source a emission de champ, son procede de production, et son utilisation - Google Patents
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- WO2000013197A1 WO2000013197A1 PCT/JP1999/004613 JP9904613W WO0013197A1 WO 2000013197 A1 WO2000013197 A1 WO 2000013197A1 JP 9904613 W JP9904613 W JP 9904613W WO 0013197 A1 WO0013197 A1 WO 0013197A1
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- electric field
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- strong electric
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J31/00—Cathode ray tubes; Electron beam tubes
- H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
- H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
- H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
- H01J1/02—Main electrodes
- H01J1/30—Cold cathodes, e.g. field-emissive cathode
- H01J1/312—Cold cathodes, e.g. field-emissive cathode having an electric field perpendicular to the surface, e.g. tunnel-effect cathodes of metal-insulator-metal [MIM] type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J31/00—Cathode ray tubes; Electron beam tubes
- H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
- H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
- H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
- H01J31/123—Flat display tubes
- H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
- H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2201/00—Electrodes common to discharge tubes
- H01J2201/30—Cold cathodes
- H01J2201/312—Cold cathodes having an electric field perpendicular to the surface thereof
- H01J2201/3125—Metal-insulator-Metal [MIM] emission type cathodes
Definitions
- the present invention relates to a field emission type electron source in which a semiconductor material is used to emit an electron beam by intense field emission, a method for manufacturing the same, and a use thereof, and US Patent Application No. 09/140, The present invention relates to the improvement of No. 647 [Field emission type electron source and its manufacturing method and its use], the contents of which are the contents of the present invention. Background art
- the inventors have developed a planar type in which a thermally oxidized porous polycrystalline silicon layer is formed on a conductive substrate, and a surface electrode made of a metal thin film is formed on the thermally oxidized porous polycrystalline silicon layer.
- Proposed a field emission type electron source Japanese Patent Application No. 10-65592.
- This field-emission electron source uses a front electrode as a positive electrode with respect to a conductive substrate, applies a direct current ma between the front electrode and the conductive substrate, and uses a front electrode as a cathode and a collector electrode disposed opposite to the front electrode.
- a DC voltage is applied between the electrodes to emit electrons from the surface of the surface electrode.
- a display device using this type of field emission electron source includes a glass substrate 33 opposed to the surface electrode 7 of the field emission electron source 10 ′ as shown in FIG.
- a collector electrode 31 is formed in a stripe shape on the surface facing the electric field emission
- the field emission electron source 10 is formed by forming a thermally oxidized porous polycrystalline silicon layer 6 on an n-type silicon substrate 1, which is a conductive substrate.
- the surface electrode 7 is formed in a stripe shape.
- An ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1 '.
- the surface electrode 7 is formed in a stripe shape as described above, and the collector electrode 31 is formed in a stripe shape orthogonal to the surface electrode 7 to form the collector electrode 31 and the surface electrode.
- SJEE strong electric field
- the Iff of the phosphor layer 32 is applied by applying a voltage B to the specific surface electrode 7 and the specific collector electrode 31.
- the portion corresponding to the area where the two electrodes 7, 31 intersect can be illuminated.
- images, characters, and the like can be displayed.
- a high voltage is applied to the collector electrode 31 to accelerate the electrons in order to illuminate the phosphor of the phosphor layer 32 with the electrons emitted from the field emission electron source 10.
- a high 1 JE of several hundreds to several kV is usually applied to the collector electrode 31. Disclosure of the invention
- the present invention has been made in view of the above circumstances, and a first object of the present invention is to selectively emit electrons from a desired region of a surface electrode without switching a collector electrode to which a high voltage is applied. n in subjecting Hisage the field emission electron source and a manufacturing method capable
- the present invention provides a conductive substrate having a lower electrode made of a conductive layer on at least one main surface, and a strong electric field formed on the conductive layer of the conductive substrate.
- a field emission type electron source which drifts electrons from the conductive substrate to the strong electric field drift layer and is emitted through the conductive thin film,
- the conductive layer on the conductive substrate is formed to have a plurality of stripes extending in parallel at a predetermined interval, while the conductive thin film is formed on the conductive layer in a stripe form by the strong electric field drift layer. Are formed in a plurality of stripes extending in parallel at a predetermined interval so as to intersect and intersect with each other,
- the strong electric field drift layer is a porous polycrystalline semiconductor layer oxidized or nitrided, and at least at each position where the stripes of the conductive layer and the stripes of the conductive thin film face each other and intersect each other.
- a field emission type electron source array characterized in that a conductive thin film constitutes a plurality of electron sources arranged at predetermined intervals on the conductive substrate with the strong electric field drift layer interposed therebetween. is there.
- Electrons are emitted only from the region of the surface electrode to which the voltage is applied, which crosses the lower electrode to which the voltage is applied. Electrons can be emitted from a desired area, and a high voltage of several hundred V to several kV applied to the collector electrode when a display device is constructed by arranging a collector electrode facing the surface electrode. No switching circuit is required. Therefore, a field emission type electron source array capable of selectively emitting electrons from a desired region of the surface electrode is reduced in cost and size. Have the advantage that you can.
- the conductive substrate is a substrate having a conductive layer functioning as a negative electrode of a field emission electron source on its main surface, and has a strength supporting a polycrystalline semiconductor layer laminated thereon in a vacuum.
- a substrate in which a conductor layer doped with an n-type impurity is formed in a predetermined region of a p-type semiconductor layer forming one main surface is referred to as a contact substrate.
- it means a substrate on which a metal layer is formed.
- a metal layer forming a conductor layer or a conductor layer doped with n-type impurities is formed on the substrate in a stripe pattern at a predetermined interval. Is done.
- a semiconductor layer having a conductor layer formed of an impurity diffusion layer may be provided on an insulating substrate.
- the conductor layer is an n-type impurity layer
- the layer separating the n-type impurity layer is a p-type impurity layer.
- an insulating material such as glass, and to form a conductor layer as a metal film by vapor deposition or the like.
- the conductor layers have a stripe width of several 10 ⁇ m to several thousand ⁇ m, and are arranged in parallel at intervals of several hundred ⁇ m. In the case of metal, the thickness is several hundreds of m / s / m, and several ⁇ for the diffusion layer.
- the polycrystalline semiconductor layer is composed of a polycrystal such as a group IV element S i, G e, or C, a group IV—IV compound S i C, a group V—V compound G a As, G a N, or In.
- a polycrystal such as a group IV element S i, G e, or C, a group IV—IV compound S i C, a group V—V compound G a As, G a N, or In.
- Various polycrystalline semiconductors such as P-VI group compounds ZnSe and the like can be mentioned, but polycrystalline silicon can be made porous by anodic oxidation and then oxidized or nitrided. It is preferable because an insulating film is easily formed on the crystal surface and a strong electric field drift layer is formed.
- the strong electric field drift layer see the aforementioned US patent application Ser. No. 09 / 140,647, Japanese Patent Application No. 10-27,324, and Japanese Patent Application No. 11-115. It
- a P-type impurity is doped between the strong electric field drift layers to prevent current leakage between the drift layers, and an insulating layer is preferably provided above the P-type impurities. It is good to shut off the leak.
- the strong electric field drift layer may be removed by etching, and an insulating layer may be formed on the inner surface of the groove, or the etching space may be completely filled.
- the strong electric field drift layer is formed by forming a polycrystalline semiconductor layer on a conductive substrate and performing anodic oxidation treatment to make the upper part or the entirety of the portion of the polycrystalline semiconductor layer on the conductor layer porous.
- a strong electric field drift layer can be formed by oxidizing or nitrifying the oxidized portion.
- the portion where the strong electric field drift layer is to be formed is masked and the other portion is removed by etching, and then anodized, the whole becomes easily porous.
- the forming conditions, anodizing and oxidizing or nitriding conditions on the conductive substrate when the polycrystalline semiconductor is polycrystalline silicon are described in detail in U.S. Application No. 09 / "140,647".
- a portion between the adjacent strong electric field drift layers is removed by etching to expose the main surface of the semiconductor substrate, and at least the exposed main surface of the semiconductor substrate.
- the insulation between the adjacent strong electric field drift layers can be improved
- the conductive layer is an n-type diffusion layer
- the insulating layer is silicon oxide.
- a silicon nitride film is formed in a stripe shape on the main surface of the p-type silicon substrate, and the silicon nitride film is formed on the main surface of the p-type silicon substrate.
- a silicon oxide layer is formed by selectively oxidizing an uncovered portion, and after removing the silicon nitride film, an n-type layer is formed between adjacent silicon oxide layers on the main surface side of the p-type silicon substrate ⁇ .
- a region Forming a region, forming a polycrystalline semiconductor layer on the n-type region, performing anodic oxidation treatment to make the polycrystalline semiconductor layer porous, and oxidizing the polycrystalline semiconductor layer.
- a strong electric field drift layer is formed, and a surface electrode made of a metal thin film crossing the n-type region is formed on the strong electric field drift layer. If the layer (eg, n-type region) and the strong electric field drift layer are formed in a stripe shape, a leakage current may flow between the conductor layers or the strong electric field drift layer.
- a second object of the present invention is to provide a field-emission electron source array capable of reducing the cost and size in the above-described manner, by preventing leakage current and achieving a desired area of the surface electrode.
- An object of the present invention is to provide a field emission type electron source capable of selectively emitting electrons from a region.
- the present invention in order to achieve the second object, first, in the field emission type electron source array, when the conductive substrate is formed from a semiconductor layer, a conductive layer formed on a main surface side thereof is formed. A high impurity concentration diffusion layer is provided between the body layers (impurity diffusion layers). A high impurity concentration diffusion layer is provided between the diffusion layers to prevent leakage current from flowing between the diffusion layers.
- a p-type impurity is doped into the polycrystalline semiconductor layer between the strong electric field drifts to form a p-type region, thereby preventing a leakage current from flowing between the strong electric field driven layers.
- a current leaks from the conductive substrate through the polycrystalline semiconductor layer to the surface electrode through the layer. It is better to prevent.
- a portion of the portion between the surface electrodes and / or a portion of the portion between the conductor layers is etched by etching.
- a separation groove penetrating in the thickness direction may be provided.
- the current from the semiconductor substrate and the semiconductor layer to the surface electrode or the adjacent strong electric field drift layer through the polycrystalline semiconductor layer can be increased. Leak can be prevented.
- the conductor layer is formed as an impurity diffusion layer on the main surface side of conductor substrate
- high-concentration impurity layers are preferably provided on both sides of the impurity diffusion region in the width direction.
- the impurity diffusion layer is preferably provided as an n-type region on a p-type semiconductor substrate, an n + layer having a higher impurity concentration than the n-type region is provided adjacent thereto.
- the impurity concentration of the n-type region is reduced, the resistance value of the n-type portion can be reduced because the n-type region and the n + layer are adjacent to each other.
- the ⁇ ++ layer having a higher impurity concentration is provided in the n + layer, the concentration of a strong electric field can be prevented, and the withstand voltage can be improved.
- the straightness of electrons emitted from the strong electric field drift layer via the surface electrode may be impaired.
- a third object of the present invention is to provide a field emission type electron source having an improved ability to selectively emit electrons from a desired surface electrode region while maintaining the straightness of electrons.
- the polycrystalline semiconductor layer located between the strong electric field drift layers is removed, or a ⁇ -type impurity is doped at a high concentration to prevent a strong electric field drift between the eyebrows.
- the degree of insulation has been improved.
- the surface electrode is formed smaller than the width of the part on the drift layer, and improves the straightness of the emitted electrons as compared with the case where the width of the surface electrode is constant over the entire area in the length direction.
- the surface electrode is formed thicker in the thickness direction at a portion that does not overlap the strong electric field drift layer than at a portion that overlaps the strong electric field drift layer, it prevents electrons from passing through and prevents electrons from passing through. Straightness of the vehicle can be improved.
- the upper fiber edge layer causes a step with the portion of the polycrystalline semiconductor layer located between the strong electric field drift layers.
- the surface electrode needs to pass through the electrons that have been driven through the strong electric field drift layer, and is made of a metal thin film. Therefore, a metal thin film formed at a step is easily broken. Therefore, the insulating layer was provided by reducing the step between the surface of the polycrystalline semiconductor layer and the surface of the strong electric field drift layer by gradually decreasing the thickness as the both ends in the width direction of the insulating layer approached the end. It is better to prevent the surface electrode from being broken by the above.
- the upper I53 ⁇ 43 ⁇ 4 It can be formed by the COS method.
- the above-mentioned insulating layer can be formed relatively easily by the LOCOS method used in the manufacturing process of a MOS device or the like, and the shape of the insulating layer can be stably formed. Can be.
- the surface electrode made of a conductive thin film can further prevent disconnection of the surface electrode and further suppress an increase in electric resistance. it can.
- the surface electrode is thin and has a high resistance, it generates heat due to Joule heat due to the flowing current and also due to Joule heat due to the current flowing inside the strong electric field drift layer.
- a wiring electrode that is electrically and thermally coupled separately from the surface electrode.
- the ss electrode thicker than the surface electrode, the resistance of the surface electrode can be reduced and the operating characteristics can be stabilized.
- the material for the electrode is different from that of the surface electrode, and that the material for the function is optimally selected.
- an insulating layer is preferably provided below the wiring electrode to prevent reactive current from directly jumping into the wiring layer.
- a preferred embodiment for producing the field emission type electron source having the above configuration is as follows. A description will be given based on the drawing using a semiconductor substrate. When an insulating substrate is used, a substrate is used! An electron source is formed using the same method except that a metal film is formed as a conductive layer on a conductive substrate. be able to.
- the method for manufacturing an electron source array according to the present invention comprises:
- (E) a step of forming a plurality of striped conductive thin films arranged in parallel at predetermined intervals on a polycrystalline semiconductor layer partially porous and oxidized or nitrided so as to face and cross the conductor layer; Is provided.
- a method of selectively anodizing a part of the polycrystalline semiconductor layer of (B) to make it porous may include a step of forming a mask material layer in which a predetermined region for anodic oxidation is opened on the polycrystalline semiconductor layer.
- the plurality of the case forming a stripe-shaped conductive layer is a substrate semiconductor (a _l) p-type semiconductor layer doping of the substrate or p-type semiconductor base plate provided on the main surface of the (A) And (a-2) doping the above-mentioned predetermined region with an n-type impurity to form an n-type impurity diffusion layer.
- the step (A) of forming a plurality of stripe-shaped conductor layers further comprises: (a-3) forming an insulating layer on the P- type conductive substrate on which the n-type impurity diffusion layer is formed;
- the method may include a step of opening an insulating layer in a predetermined region of the impurity diffusion layer.
- the step (B) of selectively anodizing a part of the polycrystalline semiconductor layer to make it porous is a step of anodizing the electrode provided on the back surface of the semiconductor substrate as one electrode. .
- the method of the present invention is characterized in that (F) an impurity having a conductivity type opposite to that of the diffusion layer forming the conductor layer is introduced into an adjacent porous polycrystalline semiconductor layer to thereby form a polycrystalline semiconductor layer having a conductivity type opposite to that of the conductive layer. Forming a crystalline semiconductor layer; and (G) forming an insulating film on the polycrystalline semiconductor layer having a conductivity type opposite to that of the conductor layer.
- the step of etching away part or all of the adjacent conductive layers and the semiconductor layer where the conductive thin film is not formed may be performed after the anodic oxidation step or before the anodic oxidation step.
- the method further includes a step of forming a plurality of stripe-shaped layers arranged at predetermined intervals on the polycrystalline semiconductor layer so as to face and cross the conductor layer, In some cases, porosity is formed at predetermined intervals along the conductive layer by the oxidation process.
- the conditions in the above steps may be performed based on the content of US Patent Application No. 09 / 140,647.
- the first manufacturing method is as shown in Figs. 1A to 1G.
- a p-type conductive semiconductor substrate 1 is prepared (FIG. 1A), a predetermined mask 9 is formed, and an opening 8 is doped with an n-type impurity to form a conductive layer 8 functioning as a lower electrode. They are formed in stripes at regular intervals (Fig. 1B).
- the polycrystalline semiconductor layer 3 is laminated (Fig. 1C).
- the portion other than the portion to be made porous is covered with the first mask 16-1 (Fig. 1D)
- the electrode layer 2 is formed on the back surface of the substrate 1, and the electrode layer 2 is used as an anode,
- the crystal in the porous region is oxidized or nitrided to form the strong electric field drift layer 6.
- the figure shows that the entire strong electric field drift layer 6 is a porous polycrystalline semiconductor oxidized or nitrided. The upper part is oxidized or nitrided due to the electrolysis conditions. Sometimes it is.
- a metal thin film 7 functioning as a surface electrode is formed on the polycrystalline semiconductor layer 3 including the strong electric field drift layer 6 (Pig.l F).
- the insulating film 16-2 of the two masks is formed to ensure the straightness of the emitted electrons (Fig. 1G).
- the second manufacturing method is a method that branches from Fig. IB of the first method and is shown in the steps following Fig. 2A to Fig. 4D and 4G.
- the mask 9 is temporarily removed (Fig. 2A), and then the polycrystalline semiconductor layer 3 is laminated (Fig. 2B). .
- the portion other than the portion to be made porous is covered with the first mask 16-1 (Fig. 2C), and after forming the electrode layer 2 on the back surface of the substrate 1, the electrode layer 2 is used as an anode and an electrolytic solution bath is used. When it is immersed in it and electrolyzed at a constant current and anodized in a given area, it becomes porous as shown in Fig. 6 (Fig. 2D).
- the crystal in the porous region is oxidized or nitrided to form the strong electric field drift layer 6.
- the third electric field drive layer 6 of the polycrystalline semiconductor layer 3 is covered with a third yoke 16-3 (FIG. 2E), and the polycrystalline semiconductor layers other than the strong electric field drift layer are removed by etching.
- Layer 9 is deposited on the six strong electric field drift layers (Fig. 2F), and the third mask on the strong electric field drift layer 6) is removed (Fig. 4D).
- a metal thin film 7 functioning as a surface electrode is formed thereon (Fig. 4E), and an electron source is formed.
- the third manufacturing method is a method that branches from Fig. 1C of the first method and is shown in the steps following Fig. 3A to Fig. 3F.
- a polycrystalline semiconductor layer 3 is laminated (Fig. 1C).
- a third mask 16- 3 (Fig.3 a)
- the strength of the polycrystalline semiconductor layer other than the electric field drift layer is removed by etching (Fig. 3B), followed by the third mask on the strong electric field drift layer 6 ⁇ After removing 16-3 (Fig.
- this electrode layer 2 is used as an anode, immersed in an electrolytic solution bath, and electrolyzed at a constant current.
- this region is anodized, it becomes porous as shown in Fig. 6 (Fig. 3D).
- the crystal in the porous region is oxidized or nitrided to form a strong electric field drift layer 6.
- a metal thin film 7 functioning as a surface electrode is formed on the strong electric field drift layer 6 of the polycrystalline semiconductor layer 3 (FIG. 3E), and a portion other than the strong electric field drift layer 6 of the thin metal film 7 is further formed.
- the third alternative is a method that branches off from Fig. 2B of the second method and shows the steps following Fig. 2G ⁇ Fig. 2 C ⁇ Fig. 2 D- ⁇ Fig. 2H ⁇ Fig. 2 I .
- a conductive layer 8 is formed on the semiconductor substrate 1 by doping n-type impurities and then temporarily masked.
- a polycrystalline semiconductor layer 3 was laminated (Fig.2B), wherein, other than the portion of the multi-porosifying is covered with a third mask 16- 3 (Fig.2G), wherein Then, a P-type impurity is doped in a portion other than the portion to be made porous, the mask 16-3 is removed, and a portion other than the portion to be made porous is covered by the first mask 16-1 (Fig. 2C).
- this electrode layer 2 is used as an anode, immersed in an electrolytic solution bath, electrolysis is performed at a constant current, and a predetermined area is anodized. (Fig. 2 D). Further, the crystal in the porous region is oxidized or nitrided to form a strong electric field drift layer 6.
- the intense electric field Doributo layer 6 thin metal film 7 that acts as a surface electrode on the polycrystalline semiconductor layer 3 is formed containing (Fig.2H), further second strength portions other than electric field drift layer 6 of the metal thin film 7
- a mask insulating film 16-2 is formed to ensure the straightness of emitted electrons (Fig. 21).
- the fourth manufacturing method is a method shown in the steps from Fig. 4A to Fig. 4E that branch off from Fig. 1E of the first method.
- the first mask 16-1 on the polycrystalline semiconductor layer 3 on which the strong electric field drift layer 6 was formed by being anodized and oxidized or nitrided in Fig. 1E was removed (Fig. 4A).
- a third mask 16-3 covers the strong electric field drift layer 6 of the polycrystalline semiconductor layer 3 (Fig. 4B), and the polycrystalline semiconductor layer other than the strong electric field drift layer is removed by etching (Fig. 4C). Then, the third mask on the strong electric field drift layer 6 was removed and the butterfly 16-3 was removed (Fig. 4A).
- a metal thin film 7 functioning as a surface electrode is formed thereon (Fig. 4E), and an electron source is formed.
- a preliminary mask 14 formed in stripes is formed on the main surface side of the p-type silicon substrate 1 (Fig. 5B).
- a system fe ⁇ layer 15 consisting of a silicon oxide film is formed using the LOCOS method (Fig. 5C), and n-type impurities are added to the main surface side of the p-type silicon substrate using the insulating layer 15 as a mask.
- the ⁇ -type region 8 is formed in the form of a stripe by introducing GaN (Fig. 5D), and then the polycrystalline semiconductor layer 3 is formed on the n-type region and on the insulating layer (Fig. 5E). The part except for the anodization is covered with the first mask 16-1 (Fig.
- the part of the polycrystalline semiconductor layer 3 on the n-type region is anodized using the n-type region 8 as an electrode.
- the porous polycrystalline semiconductor layer is oxidized to form a strong electric field drift layer 6 (Fig. 5G), and then the polycrystalline semiconductor layer is formed on the strong electric field drift layer.
- a surface electrode consisting of a striped conductive thin film is formed over the layer (Fig. 5H).
- an insulating film 16-2 of the second mask is further formed on the metal thin film 7 in a portion other than the strong electric field drift layer 6 to secure the straightness of the emitted electrons (Fig. 51).
- n-type impurities are introduced into the main surface side of the p-type silicon substrate using the insulating layer made of silicon oxide film formed using the LOCOS method as a mask. Can be formed, eliminating the need for a separate step of forming a mask for forming the n-type region, and improving the accuracy of the relative position between the n-type region and the insulating layer. .
- n-type region as an electrode, a portion of the polycrystalline semiconductor layer on the n-type region is made porous by anodizing, and the porous polycrystalline semiconductor layer is oxidized or nitrided. As a result, a strong electric field drift layer can be formed. As a result, it is possible to provide a field emission type electron source capable of emitting electrons only from a desired region of the surface electrode and insulating between adjacent strong electric field drift layers. it can.
- the sixth method is a method that branches off from Fig. 1B of the first method, leads from Fig. 6A to Fig. 6F, and is shown in the steps following Fig. 4D and 4E.
- the first mask 16-1 is temporarily removed (FIG. 6A), and the conductive layer 8 is formed between the adjacent conductive brows 8 A high-concentration layer 17 doped with high-concentration impurities is formed and separated, and double layers 18 and 19 are formed at both ends of the conductor layer, which are heavily doped with n-type impurities. Lower the resistance of the conductor layer. Otherwise, as in Fig. 2, the polycrystalline semiconductor layer 3 is then laminated (Fig. 6B). Here, the portion other than the portion to be made porous is covered with the first mask 16-1 (Fig.
- this electrode 2 is used as an anode and an electrolytic solution bath is used.
- an electrolytic solution bath is used.
- the crystal in the porous region is oxidized or nitrided to form the strong electric field drift layer 6.
- the high electric field drift layer 6 of the polycrystalline semiconductor layer 3 is covered with a third mask 16-3 (Fig. 6E), and the polycrystalline semiconductor layers other than the strong electric field drift layer are removed by etching (Fig. 6F), the insulating film 16-3 of the third mask on the strong electric field drift layer 6 is removed (Fig. 4D), and a metal thin film 7 functioning as a surface electrode is formed thereon (Fig. 4E). ), To form an electron source. BRIEF DESCRIPTION OF THE FIGURES
- FIGS. 1A to 1G are process explanatory diagrams of the first method of the present invention.
- 2A to 2I are process explanatory diagrams of another method of the second method and the third method of the present invention.
- 3A to 3F are process explanatory diagrams of the third method of the present invention.
- FIGS. 4A to 4E are process explanatory diagrams of the fourth method of the present invention.
- 5A to 5I are process explanatory diagrams of the fifth method of the present invention.
- 6A to 6F are explanatory diagrams of the steps of the sixth method of the present invention.
- FIG. 7 is a schematic configuration diagram of the first embodiment.
- Fig. 8 is a perspective view of the main part of Fig. 7.
- Fig. 9 is a cross-sectional side view of Fig. 7.
- FIGS. 10A to 10F are main process explanatory diagrams of Embodiment 1.
- FIG. 10A to 10F are main process explanatory diagrams of Embodiment 1.
- Fig. 11 is a schematic configuration diagram of Embodiment 2.
- Fig. 12 is a perspective view of the main part of Fig. 11.
- Fig. 13 is a cross-sectional side view of Fig. 11.
- FIGS. 14A to 14D are explanatory diagrams of main steps of the second embodiment.
- Fig. 15 is a schematic configuration diagram of Embodiment 3.
- Fig. 16 is a cross-sectional side view of Fig. 15.
- FIG. 17A to 17F are explanatory diagrams of main steps of Embodiment 3.
- FIG. 17A to 17F are explanatory diagrams of main steps of Embodiment 3.
- FIG. 18 is a schematic configuration diagram of the fourth embodiment.
- Fig. 19 is a sectional side view of Fig. 18.
- 20A to 20E are explanatory diagrams of main steps of the fourth embodiment.
- FIGS. 21A to 21D are explanatory diagrams of main steps of Embodiment 4 following FIG. Fig. 22 is a schematic configuration diagram of a conventionally proposed display device.
- FIG. 23 is a schematic configuration diagram of the fifth embodiment.
- FIG. 24 is a schematic configuration diagram of the sixth embodiment.
- 25A to 25C are a plan view, a cross-sectional side view, and a C-C line cross-sectional view showing a part of the field emission electron source according to the seventh embodiment.
- FIGS. 26A to 26C are a plan view, a cross-sectional side view, and a cross-sectional view taken along line CC, respectively, showing a part of the field emission electron source according to the eighth embodiment.
- FIGS. 27A and 27B are a plan view, a cross-sectional side view, and a cross-sectional view taken along line CC, respectively, showing a part of the field emission electron source according to the ninth embodiment.
- FIGS. 28A and 28B are enlarged plan views of essential parts of the field emission electron source according to Embodiment 9 and a cross-sectional view taken along line BB.
- FIGS. 29A and 29B are enlarged plan views of essential parts of a modification of the field emission electron source according to the ninth embodiment, and are sectional views taken along line BB.
- FIGS. 30A to 30C are a plan view, a cross-sectional side view, and a cross-sectional view taken along line CC, respectively, showing a part of the field emission electron source according to Embodiment 10.
- 31A to 31C are a plan view, a cross-sectional side view, and a C-C line cross-sectional view showing a part of the field emission electron source according to the eleventh embodiment.
- FIGS. 32A to 32F are explanatory diagrams of main steps of Embodiment 12.
- Fig. 33 is a schematic configuration diagram of Embodiment 13.
- FIG. 3 is a schematic configuration diagram of Embodiment 14.
- FIGS. 35A to 35D are explanatory diagrams of main steps of Embodiment 15.
- FIGS. 36A to 36D are explanatory diagrams of main steps of Embodiment 16.
- FIG. 37 is a schematic configuration diagram of Embodiment 7].
- FIG. 7 is a perspective view showing a schematic configuration of a display device using the field emission type electron source 10 of the present embodiment, in which a glass substrate 33 is disposed so as to face the field emission type electron source 10. Is established. Glass substrate 3 3! A collector electrode 31 is formed on the surface opposite to the field emission electron source 10, and the collector electrode 31 has a fluorescent light that emits visible light by electrons emitted from the field emission electron source 10. Body layer 32 is applied. The glass substrate 33 is integrated with the field emission type frost source 10 using a glass spacer or the like (not shown), and the glass substrate 33, the spacer, and the field emission type electron source 10 are combined. The internal space surrounded by is set to a predetermined degree of vacuum.
- the electric field f-type electron source 10 includes a p-type silicon substrate 1 and a polycrystalline silicon layer 3 formed on the p-type silicon substrate 1 as a polycrystalline semiconductor layer. And an n-type region 8 formed in a strip shape on the main surface side in the p-type silicon substrate 1; and an oxidized porous multi-layer formed in a portion of the polycrystalline silicon layer 3 on the n-type region 8. It comprises a strong electric field drift layer 6 made of crystalline silicon, and a surface electrode 7 made of a metal thin film formed in a strip shape on the polycrystalline silicon layer 3 and orthogonal (intersecting) to the n-type region 8. In the present embodiment, gold is used as the surface electrode 7.
- the material of the surface electrode 7 is not limited to gold, but may be a metal having a small work function. , Chromium, tungsten, nickel, platinum, and alloys of these metals can be used. In the present embodiment, the surface JP / 03
- the thickness of the pole 7 was set to 10 nm, the thickness is not particularly limited.
- the carrier concentration of the shaped region 8 is set to 1 ⁇ 1018 cm 3 to 5 ⁇ 10 19 cm 3 .
- a matrix is formed by the n-type regions 8 formed in a stripe and the surface electrodes 7 formed in a stripe orthogonal to the n-type region 8. Therefore, by appropriately selecting the n-type region 8 to which a voltage is applied and the surface electrode 7, electrons are emitted only from the region of the surface electrode 7 to which the voltage is applied, which crosses the shape region 8 to which the voltage is applied. Electrons can be emitted from a desired region of the surface electrode 7 from the emitted force.
- the contact to the n-type region 8 is formed by etching a part of the strong electric field drive layer 6 to expose a part of the surface of the n-type region 8 as shown in FIG. Connected.
- the collector electrode 31 does not need to be formed in a stripe shape as in the display device shown in Fig. 22, and several hundred volts applied to the collector electrode 31 are required. A circuit for switching a high voltage of several kV or less is not required, and cost reduction and size reduction can be achieved.
- the voltage applied between the n-type region 8 and the surface electrode 7 is 10 V to 30 V @ ⁇ .
- a mask for thermal diffusion or ion implantation is provided on the main surface of the p-type silicon substrate 1, and phosphorus (P) or the like is formed on the main surface side of the p-type silicon substrate 1 by the thermal diffusion technology or the ion implantation technology.
- phosphorus (P) or the like is formed on the main surface side of the p-type silicon substrate 1 by the thermal diffusion technology or the ion implantation technology.
- a non-doped polycrystalline silicon layer 3 having a thickness of 1.5 // m is formed on the main surface of the p-type silicon substrate 1 having the n-type region 8 formed thereon by LPCVD.
- the structure shown in Fig. 10B is obtained.
- the film forming conditions of the LPCVD method were as follows: the substrate ⁇ was 610, the flow rate of the SiH 4 gas was 600 sccm, and the degree of vacuum was 20 Pa.
- the method of forming the polycrystalline silicon layer 3 is limited to the LPCVD method. After forming an amorphous silicon layer by, for example, a sputtering method or a plasma CVD method, the amorphous silicon layer is crystallized by performing an annealing process to form a polycrystalline silicon layer 3. Use the method.
- a photoresist is applied on the polycrystalline silicon layer 3 and a resist layer 9 patterned in a stripe is formed by opening a portion above the n-type region 8 by a photolithographic technique, The structure shown in Fig. 10C is obtained.
- a 55 wt% aqueous hydrogen fluoride solution and ethanol were mixed in a ratio of 1: 1, and an electrolytic solution cooled to 0 ° C was used.
- a platinum electrode (not shown) was used as a negative electrode, and a p-type silicon substrate 1 (p An ohmic electrode (not shown) is formed on the back surface of the shaped silicon substrate 1), and the exposed portion of the polycrystalline silicon layer 3 is irradiated with light using the resist layer 9 as a mask for anodizing treatment.
- anodic oxidation treatment at a constant current while performing, the porous polycrystalline silicon layer 5 is partially formed (in the form of stripes), and then the resist layer 9 is removed.
- the current density was set to 20 mAZ cm 2
- the anodizing time was set to 15 seconds
- a 50 OW tungsten lamp was used during the anodizing treatment.
- the porosity of the porous polycrystalline silicon layer 5 is made substantially uniform while the current density during the anodic oxidation treatment is constant, but the porosity can be reduced by changing the current density during the anodic oxidation treatment.
- a structure in which high polycrystalline silicon layers and polycrystalline silicon layers with low porosity are alternately laminated may be employed, or a structure in which porosity continuously changes in the thickness direction may be employed.
- the polycrystalline silicon layer 3 is made porous until it reaches a depth reaching the p-type silicon substrate 1 in the thickness direction and the polycrystalline silicon layer 3 is made porous halfway in the thickness direction. You may do so.
- the porous polycrystalline silicon layer 5 is subjected to rapid thermal oxidation (RTO) in a dry oxygen atmosphere, so that a strong electric field drift layer 6 made of thermally oxidized porous polycrystalline silicon is obtained. Is formed, and the structure shown in Fig. 10E is obtained.
- RTO rapid thermal oxidation
- conditions for the rapid thermal oxidation were an oxidation temperature of 90 ° C. and an oxidation time of 1 hour.
- a stripe is formed on the polycrystalline silicon layer 3 on which the strong electric field drift layer 6 is formed.
- a metal thin film gold thin film
- a striped surface electrode 7 made of a metal thin film is formed.
- An electric field emission source having the structure shown in FIG.
- the patterning method of the surface electrode 7 a photolithography technique and an etching technique may be used, or a photolithography technique and a lift-off method may be used.
- the method for manufacturing a field emission electron source of the present embodiment can provide a field emission electron source 10 capable of emitting electrons only from a desired region of the surface electrode 7.
- a silicon oxide film / silicon nitride film formed in a stripe shape may be used as a mask, or a silicon oxide film / silicon nitride film may be used. In this case, the step of removing the mask after the anodic oxidation treatment is unnecessary.
- FIG. 11 is a perspective view showing a schematic configuration of a display device using the field emission type electron source 10 of the present embodiment.
- a glass substrate 33 is provided so as to face the field emission type electron source 10. Is done.
- a collector electrode 31 is formed on the surface of the glass substrate 33 opposite to the field emission electron source 10, and visible light is generated on the collector electrode 31 by electrons emitted from the field emission electron source 10.
- a phosphor layer 32 that emits light is applied. Note that the same components as those in the first embodiment are denoted by the same reference numerals.
- the field emission electron source 10 of the present embodiment has a configuration for preventing the occurrence of this kind of problem.
- the field-emission electron source 10 of the present embodiment is formed in a p-type silicon substrate 1 and in a stripe shape on the main surface side in the p-type silicon substrate 1.
- N-type region 8 and the oxidation formed on n-type region 8 Electric field drift layer 6 made of porous polycrystalline silicon, polycrystalline silicon layer 3 formed on the side wall of strong electric field drift layer 6, and p-type polycrystalline silicon layer 3 formed between three polycrystalline silicon layers.
- the polycrystalline semiconductor layer is composed of the strong electric field drift layer 6, the polycrystalline silicon layer 3, and the p-type polycrystalline silicon layer 3.
- a stripe is formed on the polycrystalline semiconductor layer.
- a surface electrode 7 made of a metal thin film orthogonal (intersecting) to the n-type region 8 is formed. It should be noted that the force formed by the polycrystalline silicon layer 3 on the side wall of the strong electric field drift layer 6, and that the polycrystalline silicon layer 3 does not necessarily need to be provided. And the p-type polycrystalline silicon layer 3 ′ alone.
- the p-type polycrystalline silicon layer is a p-type polycrystalline silicon layer
- the p-type polycrystalline silicon layer 3 Since a reverse bias Iff is applied between the p-type polycrystalline silicon layer 3 ′ and the n-type region 8, the p-type polycrystalline silicon layer 3, It can prevent electrons from being injected into the substrate, and can electrically insulate the adjacent strong electric field drift layers 6 from each other. Therefore, current can be prevented from leaking to the strong electric field drift layer 6 on the n-type region 8 next to the n-type region 8 to which the voltage has been applied. When a voltage is applied, current can be reliably passed only to the region where the n-type region 8 and the surface electrode 7 intersect.
- a matrix is formed by the n-type region 8 formed in a stripe shape and the surface electrode 7 formed in a stripe shape orthogonal to the n-type region 8. Therefore, by appropriately selecting the n-type region 8 to which a voltage is applied and the surface electrode 7, the region of the surface electrode 7 to which E is applied, which intersects the n-type region 8 to which 3 ⁇ 4ff is applied Since electrons are emitted only from the desired region, electrons can be emitted from a desired region of the surface electrode 7.
- the contact to the n-type region 8 is formed by etching a part of the strong electric field drift layer 6 to expose a part of the surface of the n-type region 8 as shown in Fig. 12, and is connected by Is done.
- the collector electrode 31 does not need to be formed in a stripe shape as in the display device shown in Fig. 22.
- a circuit for switching a high voltage of several hundred V to several kV applied to 1 becomes unnecessary, and cost reduction and miniaturization can be achieved.
- a method for manufacturing the field emission electron source 10 of the present embodiment will be described with reference to FIGS.
- a dopant such as phosphorus (P) is introduced into the main surface side of the P-type silicon substrate 1 by a thermal diffusion technique or an ion implantation technique to form an n-type region in a stripe shape.
- a non-doped polycrystalline silicon layer 3 having a thickness of 1.5 / zm is formed on the main surface of the p-type silicon substrate 1 on which the n -type region 8 is formed by LPCVD.
- the part on the ri-shaped region 8 is made porous by anodizing treatment, and the strong electric field drift layer 6 made of thermally oxidized porous polycrystalline silicon is formed by rapid thermal oxidation, as shown in Fig. 8A.
- the structure is obtained.
- FIG. 8B a structure shown in FIG. 8B is obtained by applying a photoresist and patterning it so that the resist layer 12 remains on the strong electric field drift layer 6. That is, the resist layer 12 is formed in a stripe shape.
- ions such as boron B are implanted into the polycrystalline silicon layer 3 between the strong electric field drift layers 6 by an ion implantation technique, so that the p-type polycrystalline silicon layers 3 and Then, the structure shown in FIG. 8C is obtained by removing the resist layer 12.
- the sidewall layer composed of the polysilicon layer 3 remains on the sidewall of the strong electric field drift layer 6, the strong electric field drift layer 6, the polysilicon layer 3, and the p-type polysilicon layer 3 form a polycrystalline silicon layer. It constitutes a semiconductor layer.
- the strong electric field drift layer 6 and the p-type polycrystalline A polycrystalline semiconductor layer can be formed with the silicon layer 3 ′.
- a 0.5 ⁇ -thick insulating layer 16 made of silicon oxide is formed on the polycrystalline semiconductor layer by the PCVD method, and a part of the insulating layer 16 on the strong electric field drift layer 6 is removed by etching. I do.
- a strip-shaped surface electrode 7 made of a metal thin film is formed on the semiconductor polycrystalline layer by using a metal mask having a striped opening pattern by a swallowing method.
- a field emission electron source 10 having the structure shown in 14D is obtained.
- a photolithography technique and an etching technique may be used, and a photolithography technique may be used. And a lift-off method may be used.
- FIG. 15 is a perspective view showing a schematic configuration of a display device using the field emission type electron source 10 of the present embodiment.
- a glass substrate 33 is provided so as to face the field emission type electron source 10. Is done.
- a collector electrode 31 is formed on the surface of the glass substrate 33 opposite to the field emission electron source 10, and visible light is generated on the collector electrode 31 by electrons emitted from the field emission electron source 10.
- a phosphor layer 32 that emits light is applied. Note that the same components as those in the first embodiment are denoted by the same reference numerals.
- the field emission type electron source 10 of the present embodiment has a configuration for preventing occurrence of this kind of trouble.
- the field emission electron source 10 of the present embodiment is shown in FIGS.
- Electric field drift layer 6 made of porous polycrystalline silicon
- insulating film 13 made of a silicon oxide film formed on p-type silicon substrate 1 between adjacent strong electric field drift layers 6, and strong electric field drift layer
- a surface electrode 7 formed of a metal thin film and formed in a stripe shape on the substrate 6 and crossing the n-type region 8. Note that the surface electrode 7 is also formed on the insulating film 13.
- the insulating film 13 is formed between the strong electric field drift layers 6, the adjacent strong electric field drift layers 6 are electrically connected by the insulating film 13 interposed therebetween. Because of the separation, it is possible to prevent the current from leaking to the adjacent strong electric field drift layer 6.
- a matrix is constituted by the n-type region 8 formed in a stripe shape and the surface electrode 7 formed in a stripe shape orthogonal to the n-type region 8.
- the n-type region 8 and the surface electrode 7 As a result, electrons are emitted only from a region of the surface electrode 7 to which the SJE is applied, which crosses the n-type region 8 to which the voltage is applied, and a desired region of the surface electrode 7 Can emit electrons.
- the collector electrode 31 does not need to be formed in a stripe shape as in the display device shown in Fig. 22.
- a circuit for switching the applied ⁇ voltage of several hundred V to several kV is not required, and cost and size can be reduced.
- a method for manufacturing the field emission electron source 10 of the present embodiment will be described with reference to FIGS. 17A to 17F.
- a dopant such as phosphorus (P) is introduced into the main surface side of the p-type silicon substrate 1 by a thermal diffusion technique or an ion implantation technique to form an n-type region in a stripe shape.
- a non-doped polycrystalline silicon layer 3 having a thickness of 1.5; xm is formed on the main surface of the p-type silicon substrate 1 on which the n-type region 8 has been formed by LPCVD.
- the part on the n-type region 8 was made porous by anodizing treatment, and a rapid thermal oxidation was performed to form a strong electric field drift layer 6 composed of thermally oxidized porous polycrystalline silicon. The structure shown is obtained.
- FIG. 17B a structure shown in FIG. 17B is obtained by applying a photoresist and patterning the resist so that the resist layer 12 remains on the strong electric field drift layer 6. That is, the resist layer 12 is formed in a stripe shape.
- the polycrystalline silicon layer 3 of the six strong electric field drift layers is removed by reactive ion etching technology.
- the width of the resist layer 12 is larger than the width of the strong electric field drift layer 6, a part of the polysilicon layer 3 is formed on the side wall of the strong electric field drift layer 6. Remains.
- the conditions for the etching by the reactive ion etching technique 0 2 gas flow 4 sccm, flow rate of 1 6 sccm of CHF 3 gas, the degree of vacuum 8.
- the power was set to 10 OW (discharge power density was 0.3 WZ cm 2 ).
- the structure shown in Fig. 17C is obtained by removing the resist layer 12.
- the method of etching the polycrystalline silicon layer 3 is not limited to the reactive ion etching technique, but may be, for example, an ion etching technique using argon gas or the like. You may adopt such.
- an insulating film 13 made of a silicon oxide film is formed by a method such as a plasma CVD method so as to cover the entire surface on the main surface side of the p-type silicon substrate 1, so that the # structure shown in FIG. Is obtained.
- the conditions for forming the silicon oxide film are as follows: the substrate temperature is 22 ° C., the flow rate of the SiH 4 gas is 50 scc rn, the flow rate of the N 20 gas is 87 75 seem, and the degree of vacuum is 133 Pa, the discharge power was 15 OW (discharge power density was 0.05 W / cm 2 ).
- the structure shown in Fig. 17E is obtained by etching away the insulating film 13 on the strong electric field drift layer 6.
- FIG. 18 is a perspective view showing a schematic configuration of a display device using the field emission type electron source 10 of the present embodiment.
- a glass substrate 33 is provided facing the field emission type electron source 10. Is done.
- a collector electrode 31 is formed on the surface of the glass substrate 33 opposite to the field emission electron source 10, and visible light is generated on the collector electrode 31 by electrons emitted from the field emission electron source 10.
- a phosphor layer 32 that emits light is applied. Note that the same components as those in the first embodiment are denoted by the same reference numerals.
- the field emission type electron source 10 of the present embodiment has a configuration for preventing occurrence of this kind of trouble.
- the field emission electron source 10 of the present embodiment is formed in a p-type silicon substrate 1 and a stripe shape on the main surface side in the p-type silicon substrate 1.
- the strong electric field drift layer 6 formed of the oxidized porous polycrystalline semiconductor formed on the n-type region 8, and the adjacent ⁇ -type region 8.
- the semiconductor device includes a formed silicon oxide layer 15 and a surface electrode 7 formed of a metal thin film which is formed in a stripe on the strong electric field driven layer 6 and which is orthogonal to (intersects) the n-type region 8. That is, in the present embodiment, since the silicon oxide layer 15 is interposed between the strong electric field drift layers 6, current can be prevented from leaking to the adjacent strong electric field drift layers 6.
- a matrix is constituted by the n-type region 8 formed in a stripe shape and the surface electrode 7 formed in a stripe shape orthogonal to the n-type region 8. Therefore, by appropriately selecting the n-type region 8 to which mjE is applied and the surface electrode 7, only the region of the surface electrode 7 to which 3 ⁇ 4ff is applied, which intersects the ⁇ -type region 8 to which voltage is applied, is selected. Since electrons are emitted, electrons can be emitted from a desired region of the surface electrode 7.
- the collector electrode 31 does not need to be formed in a stripe shape as in the display device shown in Fig. 22.
- a circuit for switching a high voltage of several hundred V to several kV applied to 1 becomes unnecessary, and cost reduction and miniaturization can be achieved.
- a method for manufacturing the field emission electron source 10 of the present embodiment will be described with reference to FIGS.
- the silicon nitride film 14 is patterned in a stripe shape using photolithography and etching techniques.
- the film formation conditions of the silicon nitride film 14 were as follows: substrate temperature: 300 ° C., flow rate of SiH 4 gas: 30 sccm, flow rate of N 2 gas: 450 sccm, NH
- the flow rate of the three gases was 30 sccm, the degree of vacuum was 67 Pa, and the discharge power was 500 W (discharge power density was 0.17 WZ cm 2 ).
- the p-type silicon substrate 1 on which the striped silicon nitride film 14 is formed is wet-oxidized in water vapor, so that the main surface of the p-type silicon substrate 1 is not covered with the silicon nitride film 14.
- a silicon oxide layer 15 is formed, and the structure shown in Fig. 20B is obtained.
- the silicon nitride film 14 is removed by etching, as shown in Fig. 20C.
- the structure is obtained.
- the structure shown in FIG. 20E is obtained by forming a polysilicon layer 3 on the n-type region 8 and the silicon oxide layer 15 by the LPC VD method.
- the film formed on the n-type region 8 is polycrystalline silicon
- the film formed on the silicon oxide layer 15 is amorphous silicon.
- the structure shown in Fig. 21A is obtained by etching away only the amorphous silicon on the silicon oxide layer 15.
- a 55 wt% aqueous solution of hydrogen fluoride and ethanol were mixed in a ratio of 1: 1 to 0.
- a cooled electrolytic solution for C light irradiation using a platinum electrode (not shown) as a negative electrode and a p-type silicon substrate 1 (an ohmic electrode (not shown) formed on the back of the P-type silicon substrate 1) as a positive electrode
- the polycrystalline silicon eyebrow 3 is made porous and the porous polycrystalline silicon layer 5 is formed, and the structure shown in FIG. 21B is obtained.
- the silicon oxide layer 15 is also etched by the above electrolytic solution during the anodizing treatment, but the etching rate of the silicon oxide layer 15 by the above electrolytic solution is about 0.14 / im per minute.
- the anodic oxidation time is 10 to 30 seconds, if the thickness of the silicon oxide layer 15 is set to about 0.5 // m, it actually functions as a mask.
- a strong electric field drift layer 6 made of thermally oxidized porous polycrystalline silicon is formed by subjecting the porous polycrystalline silicon layer 5 to 31 thermal oxidation (RTO) in a dry oxygen atmosphere using a lamp annealing apparatus. As a result, the structure shown in Fig. 21C is obtained.
- the conditions of the thermal oxidation were as follows: the oxidation temperature was 900 ° C., and the oxidation time was 1 hour. After that, a metal thin film was formed as a surface electrode 7 on the main surface side of the P-type silicon substrate 1 in a stripe shape perpendicular to the ⁇ -type region 8 by vapor deposition, and the electric field ⁇ type shown in Fig. 21D was obtained. An electron source 10 is obtained.
- the basic configuration of the field emission electron source 10 of the present embodiment is substantially the same as the configuration shown in the above embodiment, and as shown in FIG. 23, a p-type silicon substrate 1 as a conductive substrate is used.
- An n-type region 8 (diffusion layer) formed in a stripe shape on the main surface side in the p-type silicon substrate 1 and an oxidation formed on the n-type region 8 and drifting electrons injected from the n-type region 8
- Electric field drift layer 6 made of porous polycrystalline silicon formed, polycrystalline silicon layer 3 formed between strong electric field drift layers 6, and strong electric field drift formed in stripes in a direction intersecting n-type region 8.
- the strong electric field drift layer 6 is formed by forming the polycrystalline silicon layer 3 over the entire main surface of the p-type silicon substrate 1 and then forming
- Cr ZAu is used as the surface electrode 7, but the surface electrode 7 can be formed by making it porous by the anodizing treatment.
- the material is not limited to Cr / Au, but may be any metal having a small work function or a conductive film (for example, ITO film). Other metals include aluminum, chromium, tungsten, nickel, and platinum.
- the thickness of the surface electrode 7 is set to 10 nm, but the thickness is not particularly limited.
- the striped n-type region 8 and the surface electrode 7 formed in a stripe orthogonal to the n-type region 8 are formed.
- the surface electrode 7 to which the MJE is applied is appropriately selected so that, of the surface electrode 7 to which the voltage is applied, the ⁇ -type region 8 to which the voltage is applied Since electrons are emitted only from the region that intersects with the region, electrons can be emitted from a desired region of the surface electrode 7.
- a collector electrode 31 is formed on a surface of the glass substrate 33 facing the field emission electron source 10, and electrons emitted from the field emission electron source 10 are formed on the collector electrode 31.
- the phosphor layer 32 that emits visible light may be applied in advance.
- Glass substrate 33 is not shown It may be integrated with the field emission type electron source 10 using a glass spacer or the like, and the internal space surrounded by the glass substrate 33, the spacer and the field emission type electron source 10 is predetermined. Vacuum should be kept.
- the voltage applied between the n-type region 8 and the surface electrode 7 is 10 V to 30 V3 ⁇ 43 ⁇ 4.
- the p + -type region 17 which is a p-type region with a high impurity concentration, Is provided. Therefore, the provision of the P ++ -type region 17 can prevent leakage current from flowing through eight n-type regions.
- the ⁇ + diffusion layer which is an ⁇ + layer adjacent to the ⁇ -type region 8 and having a higher impurity concentration than the ⁇ -type region 8 is provided.
- an ⁇ + + diffusion layer 19 which is an ⁇ + + layer having a higher impurity concentration than the ⁇ + diffusion layer 18, is provided in the ⁇ + diffusion layer 18. Therefore, even if the impurity concentration of the ⁇ -type region 8 is reduced, the resistance value of the ⁇ -type portion can be reduced because the ⁇ -type region 8 and the ⁇ + diffusion layer 18 are adjacent to each other.
- the ⁇ + diffusion layer 19 having a higher impurity concentration than the ⁇ + diffusion layer 18 is provided in the ⁇ + diffusion layer 18, the strong electric field on the main surface side of the ⁇ -type silicon substrate 1 Concentration can be prevented, and the withstand voltage can be improved.
- the ohmic electrode 2 serving as the back electrode is provided on the back surface of the ⁇ -type silicon substrate 1, controlling the potential of the ⁇ -type silicon substrate 1 using the ohmic electrode 2 allows the ⁇ -type region to have eight questions. Thus, it is possible to more reliably prevent the leakage current from flowing.
- a part of the portion between the surface electrodes 7 is provided with a separation groove 3a penetrating in the thickness direction.
- the opening shape of the separation groove 3a is a strip shape, It is formed so that the longitudinal direction coincides with the surface pole 7 and the width direction coincides with the longitudinal direction of the strong electric field drift layer 6. For this reason, it is possible to suppress the leakage current from flowing between the strong electric field drift layers 6 and between the surface electrodes 7.
- a layer 15 formed by the LOCOS method is provided between the p-type silicon substrate 1 and the polycrystalline silicon layer 3. That is, the insulating layer 15 is formed such that a part thereof is buried in the p-type silicon substrate 1 in the thickness direction, and the thickness gradually becomes thinner as both ends in the width direction approach the ends. . Therefore, even if the insulating layer 15 is provided between the p-type silicon substrate 1 and the polycrystalline silicon layer 3, the step between the surface of the polycrystalline silicon layer 3 and the surface of the strong electric field drift layer 6 is reduced. Therefore, disconnection of the surface electrode 7 due to the provision of the insulating layer 15 can be prevented.
- the 0.03 method is a well-known element isolation technique used in the manufacturing process of 1 ⁇ 0 S devices and the like.
- the insulating layer 15 By forming the insulating layer 15 by the LOCOS method, Variations in the shape of fe ⁇ l5 can be reduced relatively easily.
- the polycrystalline silicon layer 3 is formed on the entire surface on the main surface side of the p-type silicon substrate 1 and a part of the polycrystalline silicon layer 3 is made porous by anodizing to form the electric field drift layer 6.
- the n-type region 8 can be used as an electrode (positive electrode) for the negative electrode composed of a platinum electrode, and a protective film is provided on the polycrystalline silicon layer 3 when performing anodization. There is no need to make it easier to manufacture.
- the surface electrode 7 has a narrow portion 7 a having a smaller width on the polycrystalline silicon layer 3 than a portion on the strong electric field drift layer 6. That is, since the width of the portion (narrow portion 7a) on the polycrystalline silicon layer 3 is formed to be smaller than the width of the portion on the strong electric field drift layer 6, when used for a display device or the like, the surface electrode 7 In comparison with the case where the width of the electrode is constant over the entire area in the length direction, electrons are less likely to be emitted from the surface electrode 7 above the n-type region 8 where no voltage is applied, and The crosstalk can be reduced because the straightness of the vehicle can be improved.
- the silicon nitride film is patterned into stripes using photolithography and etching techniques to form a striped silicon nitride film.
- an insulating layer 15 made of a silicon oxide film is formed. That is, the insulating layer 15 is formed by using the LOCOS method.
- a polycrystalline silicon layer 3 is formed on the insulating layer 15 on the ⁇ -type region 8 by an LPCVD method or the like, and then a 55 wt% aqueous solution of hydrogen fluoride and ethanol are mixed in a ratio of 1: Using an electrolytic solution mixed in 1 and cooled to 0 ° C, using a platinum electrode (not shown) as the negative electrode and using the n-type region 8 as the positive electrode, performing anodizing at a constant current while irradiating light.
- the polycrystalline silicon layer 3 on the n-type region 8 is made porous and a porous polycrystalline silicon layer is formed, and the porous polycrystalline silicon layer is dried in a dry oxygen atmosphere using a lamp arc apparatus.
- RTO thermal oxidation
- a metal thin film is formed as a surface electrode 7 on the main surface side of the p-type silicon substrate 1 in a stripe shape in a direction orthogonal to the n-type region 8 by a vapor deposition method.
- the p-type silicon substrate 1 is used as the conductive substrate, and the n-type region 8 is used as the diffusion layer.
- the conductive substrate is not limited to the p-type silicon substrate.
- the layer is not limited to the n-type region 8, but it is sufficient that the diffusion layers formed in a stripe shape are electrically separated from each other and electrically separated from the conductive plate.
- the basic configuration of the field emission electron source 10 of the present embodiment is substantially the same as the configuration shown in FIG. 23, and as shown in FIG. All over It is characterized in that the insulating film 21 is provided on a portion which does not overlap the electron drift layer 6 in the thickness direction. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
- the insulating film 21 is provided on a portion that does not overlap with the electron drift layer 6 in the thickness direction of the surface electrode 7.
- electrons are less likely to be emitted from the surface electrode 7 above the n-type region 8 to which no voltage is applied, and the straightness of electrons can be improved. Talk can be reduced.
- the thickness of the surface electrode 7 is made thicker in a portion that does not overlap with the electron drift layer 6 than in a portion that does overlap with the electron drift layer 6, so that the surface electrode 7 can be used for display devices and the like.
- electrons are less likely to be emitted from the upper surface electrode 7 above the n-type region 8 to which no voltage is applied, and the straightness of the electrons can be improved, so that crosstalk can be reduced. it can.
- the electron source according to the present embodiment includes a strong electric field drift layer 6 made of porous polycrystalline silicon formed on one side of the n-type silicon substrate 1 and a strong electric field drift layer 6.
- Both the rooster electrode 7 2 and the terminal electrode 71 are made of 1.5 ⁇ m-thick aluminum, and the wiring electrode 72 is installed so as to be electrically connected to the surface electrode 7.
- An insulating layer 16 made of silicon oxide having a thickness of 0.5 m is formed between 2 and the strong electric field drift layer 6.
- the thickness is thicker than the surface electrode 7 and therefore the resistance is low. Also, since the wiring electrode 72 is separately provided, the electron emission efficiency is improved or the operating voltage is reduced, the heat generation is reduced, and the operating speed is reduced. Improvement, reduction of in-plane variation of electron emission efficiency and emission current density, reduction of operation failure due to disconnection of surface electrode 3, and improvement of performance, quality and manufacturing yield when used for displays and the like.
- a 0.5 ⁇ m-thick oxide silicon is placed between the S3 ⁇ electrode 72 and the strong electric field drift layer 6. Since the layer 16 made of a reconca is formed, it is possible to eliminate a reactive current caused by electrons jumping directly into the mm from the strong electric field drift layer 6, thereby further improving the electron emission efficiency by providing the SBM electrode 72. Improvement can be achieved.
- both the electrode 72 and the terminal electrode 71 are made of the same thickness and the same material, the wiring electrode 72 can be formed at the same time as the terminal electrode 71 is formed. Even if it is provided, the number of manufacturing steps does not increase.
- the structure in which the periphery of the surface electrode 7 is surrounded by the thick wiring electrode 72 enhances heat dissipation, and further improves the temporal stability of the electron source.
- the electron source of this embodiment includes a strong electric field drift layer 6 made of porous polycrystalline silicon formed on one side of the p-type silicon substrate 1 and a strong electric field drift layer 6.
- a 10-nm thick gold surface electrode 7 with low work function and high oxidation resistance provided to cover a part of the silicon substrate 1, and a thickness of 0.5 ⁇ m formed on the back surface of the silicon substrate 1
- the gam electrode 72 and the terminal electrode 71 are both formed of aluminum having a thickness of 1.
- the electrode 72 is installed so as to be electrically connected to the surface electrode 7.
- porous polycrystalline silicon which is the material of the strong electric field drift layer 6, has been removed except for a part of the lower part of the electrode 72 for the rooster fi ⁇ , and most of the electrode 72 for the rooster has a smooth silicon substrate. It is sandwiched between ⁇ mi 6 made of silicon oxide with a thickness of 0 ⁇ 5 ⁇ m formed on 1.
- the porous polycrystalline silicon which is the material of the strong electric field drift layer 6, is removed except for a part of the lower part of the electrode 72.
- the wiring electrodes 72 can be formed on the surface of the smooth silicon substrate 1 rather than on polycrystalline silicon having large surface irregularities, thereby preventing disconnection and increase in resistance, and further improving the electron emission efficiency as compared with the seventh embodiment.
- Operating voltage, heat generation, and operating speed This improves the in-plane variation of the electron emission efficiency and the emission current density, and further reduces the operation failure due to the disconnection of the surface electrode 7, thereby improving the performance, quality, and production yield when used for a display or the like.
- a strong electric field drift layer 6 made of porous polycrystalline silicon is formed in a matrix on a substrate, for example, a silicon substrate 1, and each strong electric field drift layer 6
- a surface electrode 7 made of gold having the same thickness as that of Embodiments 7 and 8 is formed on the surface, and the la electrodes 72 are arranged in parallel with each row in correspondence with each surface electrode 7 in the same row. Is formed.
- the rooster electrode 72 is made of aluminum having the same thickness as that of the seventh and eighth embodiments.
- the surface electrode 7 is connected to the rooster electrode 72 by the coupling electrode 73.
- the wiring electrode 72 is formed so as to surround the surface electrode 7 as shown in Fig. 29 A and B. Then, the surface electrode 7 and the electrode 72 for Ei ⁇ may be electrically connected, and in this case, the heat radiation effect by the electrode 72 for wiring can be further expected.
- the strong field emission electron source of the present embodiment will be described with reference to FIGS.
- This field emission electron source is formed on a P-type silicon substrate 1, an n- type region (diffusion layer) 8 formed in a stripe shape on the main surface of the p-type silicon substrate 1, and a back surface of the p-type silicon substrate 1.
- a back electrode 2 (anomous electrode) 2 made of an anoredium with a thickness of about 0.5 / zm, and a polycrystalline silicon layer formed on the surface of the p-type silicon substrate 1 using, for example, LPCVD.
- the semiconductor crystal layer) 3 and a portion of the polycrystalline silicon layer 3 are partially porous by anodizing while irradiating light, and then are formed by rapid thermal oxidation.
- the surface electrode 7 is a metal thin film 7 a made of gold having a thickness of about 10 nm and formed on the surfaces of the polycrystalline silicon layer 3 and the porous polycrystalline silicon layer 6 by, for example, a vapor deposition method.
- the porous polycrystalline silicon layer 6 forms a porous polycrystalline semiconductor layer.
- a gap mi 16 is formed between the polycrystalline silicon layer 3 in a portion other than the porous polycrystalline silicon layer 6 and the surface electrode 7.
- a conductive substrate formed by forming a conductive layer by an n + diffusion layer on a p-type silicon substrate 1 is used, but the conductive substrate constitutes a negative electrode of a field emission electron source, This supports the porous polycrystalline silicon layer 6 in a vacuum and injects electrons into the porous polycrystalline silicon layer 6. Therefore, the conductive substrate is only required to constitute the negative electrode of the field emission type electron source and support the porous polycrystalline silicon layer 6, and is not limited to the p-type silicon substrate 1, and is not limited to the p-type silicon substrate 1.
- a conductive film may be formed on the surface of an insulating substrate.
- the porous polycrystalline silicon layer 6 as a strong electric field drift layer is formed by making a part of the polycrystalline silicon layer 3 porous and further performing rapid thermal oxidation. And the surface of the porous polycrystalline silicon layer 6 are formed substantially flush.
- the surface electrode 7a is formed by a portion other than the porous polycrystalline silicon layer 6 on the surface of the n-type silicon 1 where the porous polycrystalline silicon layer 6 constituting the strong electric field drift layer is formed and the porous polycrystalline silicon. It is formed so as to straddle the silicon layer 6, and the portion other than the porous polycrystalline silicon layer 6 and the porous polycrystalline silicon layer 6 are formed flush with each other. Since the metal thin film 7a can be formed in a region where there is no disconnection, disconnection is less likely to occur than in the case where the metal thin film 7a is formed in a stepped portion, and an increase in electric resistance can be suppressed.
- the metal thin film 7a formed on the surface of the porous polycrystalline silicon layer 6 prevents electrons reaching the surface of the porous polycrystalline silicon layer 6 from being scattered in the metal thin film 7a.
- the thickness of the metal thin film 7b formed in the region other than the porous polycrystalline silicon layer 6 does not need to be reduced.
- the thickness of the metal thin film 7a is made thicker than that of the metal thin film 7a, and the thickness of the metal thin film 7b is made larger than the thickness of the metal thin film 7a to further prevent disconnection of the metal thin film 7b. And an increase in electrical resistance can be further suppressed.
- the straightness of electrons is improved. This has the effect of reducing crosstalk.
- the surface electrode 7 constitutes the positive electrode of the field emission electron source.By applying ffi with the surface electrode 7 as the positive electrode and the n-type region 8 as the negative electrode, electrons injected from the n-type region 8 are applied.
- the electrons drifting in the porous polycrystalline silicon layer 6 and reaching the surface of the porous polycrystalline silicon layer 6 are emitted from the surface of the metal thin film 7a by a tunnel effect. Therefore, the ideal energy of the emitted electrons is obtained by subtracting the work function of the metal thin film 7a from the energy of the electrons obtained by the direct current S / ⁇ applied between the n-type region 8 and the metal thin film 7a. Therefore, the smaller the work function of the metal thin film 7a is, desirable. Further, when the metal thin film 7a is oxidized and an oxide film is formed on the surface of the metal thin film 7a, the electron emission efficiency of electrons emitted through the metal thin film 7a deteriorates.
- a metal having good oxidation resistance is desirable.
- gold is used as the metal thin film 7a.
- platinum, iridium, rhodium, ruthenium, and alloys of these metals can be used.
- the metal thin film 7b formed in a region other than the porous polycrystalline silicon layer 6 on the surface of the metal thin film 7a a material having a low resistivity is preferable.
- aluminum is used as the metal thin film 7b.
- the metal thin film 7b is not intended to be limited to aluminum, but may be a metal having a low resistivity.
- the film thicknesses of the metal thin films 7a and 7b and the electrodes 71 and 2 are not limited to the above values.
- the material of the surface electrode 7b and the terminal electrode 71 formed on the surface of the polycrystalline silicon layer 3 is the same, and the thickness of both electrodes 7b and 71 is substantially the same. Both electrodes 7 b and 7 1- ⁇ 3 can be formed.
- the surface electrode 7 is formed of a metal thin film 7 a made of, for example, gold formed on the surfaces of the polycrystalline silicon layer 3 and the porous polycrystalline silicon layer 6, and a metal thin film. 7a, a metal thin film 7b made of, for example, aluminum, formed in the region of the polycrystalline silicon layer 3 in FIG. 7a.
- the surface electrode 7 is made of a porous material.
- the metal thin films 7a and 7b are formed in a region having no step. As compared with the case where the metal thin films 7a and 7b are formed in the stepped portion, disconnection is less likely to occur and an increase in electric resistance can be suppressed.
- the surface electrode 7 constitutes the positive electrode of the field emission electron source.
- n Electrons injected from the mold region 8 1 drift the porous polycrystalline silicon layer 6, and the electrons reaching the surface of the porous polycrystalline silicon layer 6 are emitted from the surface of the metal thin film 7 a by the tunneling effect . Therefore, the ideal energy of the emitted electrons is obtained by subtracting the work function of the metal thin film 7a from the energy of the electrons obtained by the DC voltage applied between the n-type region 8 and the metal thin film 7a. Therefore, the work function of the metal thin film 7a is smaller and more desirable.
- the metal thin film 7a When the metal thin film 7a is oxidized and an oxide film is formed on the surface of the metal thin film 7a, the electron emission efficiency of electrons emitted through the metal thin film 7a deteriorates.
- Is preferably a metal having good oxidation resistance.
- gold is used as the metal thin film 7a.
- Any metal having a small work function and high oxidation resistance may be used.
- platinum, ijidium, rhodium, ruthenium, and alloys of these metals can be used.
- the metal thin film 4 b formed in the region other than the porous polycrystalline silicon layer 3 a material having a low resistivity is desirable.
- metal thin film 4 b aluminum is used as the metal thin film 4 b. It is not intended to be limited to aluminum, but may be any metal having a low resistivity. Further, the film thicknesses of the metal thin films 7a and 7b and the electrodes 71 and 2 are not limited to the above values.
- a method for manufacturing the field emission electron source according to the present embodiment will be described with reference to FIGS. 32A to 32F.
- a p-type silicon substrate 1 (a (100) substrate having a resistivity of 0.1 ⁇ cm) is used as the conductive substrate.
- a striped n-type region (n + conductive layer) 8 is formed on the main surface of the n-type silicon substrate 1, an ohmic electrode 2 is formed on the back surface, and LPCVD is performed so as to cover the n-type region 8.
- a non-doped polycrystalline silicon layer 3 having a thickness of 1.5 / im, the structure shown in FIG. 32A is obtained.
- the film formation conditions of the LPCVD method, the substrate temperature 6 1 0, S i H 4 gas flow rate of 6 0 0 sccm, a vacuum degree was 2 0 P a.
- the method of forming the polycrystalline silicon layer 3 is LPCVD.
- the polycrystalline silicon layer is formed by forming an amorphous silicon layer by, for example, a sputtering method or a plasma CVD method, and then performing an annealing process on the amorphous silicon layer to crystallize the amorphous silicon layer. May be used. The same method may be applied to other semiconductors.
- a silicon oxide layer 4 having a thickness of 1 ⁇ is formed on the polycrystalline silicon layer 3 by a plasma CVD method to obtain a structure shown in Fig. 36B.
- the conditions for forming the silicon oxide layer 4 were a substrate temperature of 225. C, and S i H 4 gas flow rate 50 sccm, N 2 0 gas flow rate 875 sc cm, a vacuum degree of 133 P a, and the discharge power of 1 5 OW (discharge power density 0. 05WZcm 2).
- the method of forming the silicon oxide layer 4 is not limited to the plasma CVD method, and a method such as a thermal oxidation method may be used.
- the structure shown in Fig. 32C is obtained by patterning the polycrystalline silicon layer 3 using photolithography and etching techniques.
- the current density was set to 2 OmAZcm 2
- the anodizing time was set to 15 seconds
- the film thickness was increased by performing light irradiation with a 50 OW tungsten lamp during the anodizing treatment.
- a porous polycrystalline silicon layer 5 having a thickness of 1 ⁇ m was formed.
- the polycrystalline silicon layer 3 is made porous halfway in the thickness direction.
- the polycrystalline silicon layer 3 may be made porous to a depth that is compatible with the n-type silicon substrate 1.
- the current density during the anodic oxidation treatment is kept constant and the number of porous polycrystalline silicon layers 5 is increased.
- L ⁇ ⁇ is almost uniform, a structure in which high-porosity polycrystalline silicon layers and low-porosity polycrystalline silicon layers are alternately stacked by changing the current density during anodization may be used. Alternatively, a structure in which the porosity continuously changes in the thickness direction may be adopted.
- the silicon oxide layer 4 was also etched by the above electrolytic solution. However, while the thickness of the silicon oxide layer 4 is 1 / zm, the etching rate of the silicon oxide by the strong electric field solution is 0.14 / x m3 ⁇ 43 ⁇ 4 / min and the anodic oxidation time is 15 Seconds, the silicon oxide layer 4 reliably serves as a mask.
- the rapid thermal oxidation (RTO) method oxidizes the porous polycrystalline silicon 5 to a certain point (that is, oxidizes a part of the porous polycrystalline silicon layer 5).
- the structure shown in E is obtained. As the conditions for the rapid thermal oxidation, the oxidation was set to 900 and the oxidation time was set to 1 hour. In the present embodiment, a part of the porous polycrystalline silicon layer 5 is oxidized, but the whole may be oxidized.
- a gold thin film is formed on the porous polycrystalline silicon layer 6 and the polycrystalline silicon layer 3 by a vapor deposition method in a stripe shape crossing the n-type region 8 using a metal mask.
- a metal thin film 7 (metal electrode) is formed, and a field emission electron source 10 having the structure shown in Fig. 36F is obtained.
- gold is used as the metal thin film 7.
- the metal thin film 7 is not limited to gold, but may be any metal having a small work function.
- aluminum, chromium, tungsten, and nickel are used. Kel, platinum, and alloys of these metals can be used.
- the thickness of the gold thin film is 10 nm, but this thickness is not particularly limited.
- the above-mentioned field emission electron source 10 is introduced into a vacuum chamber (not shown), and a collector electrode (not shown) is arranged at a position facing the metal thin film 7. as X 1 0- 5 P a, bipolar thin metal film 7 positive electrode, while applying a DC ®J £ of 2 0 V to the n-type region 8 between the electrodes as a negative electrode, a collector electrode positive, a thin metal film 7 as negative electrode.
- a DC voltage of 100 V during the period it can be observed that electrons are emitted from the surface of the metal thin film 7 toward the collector electrode.
- the back electrode 2 has a negative potential than the n-type region.
- anodization is performed using the silicon oxide layer 4 patterned by photolithography and etching, as a mask.
- the porous polycrystalline silicon layer 5 is formed, so that the pattern accuracy of the porous polycrystalline silicon layer 5 is improved, and the contact area between the oxidized porous polycrystalline silicon layer 6 and the metal thin film 7 is oxidized.
- Silicon layer 4 pattern The accuracy of the electron emission area can be improved at a low cost because it is determined by the electron accuracy.
- a p-type silicon substrate 1 ((100) substrate having a resistivity of 1 OQ cm) is used as the conductive substrate, but the conductive substrate is limited to p-type silicon 3 ⁇ 43 ⁇ 41.
- a substrate in which a conductive thin film (for example, a chromium thin film or an ITO thin film) is formed on a glass substrate or the like may be used, as compared with a case where a semiconductor substrate such as a p-type silicon substrate 1 is used. Large area and low cost can be realized.
- Fig. 33 shows a schematic configuration diagram of a planar light emitting device using the field emission electron source 10 of the embodiment 12. Note that the same components as those in the embodiment 12 are denoted by the same reference numerals, and description thereof will be omitted.
- the planar light emitting device of the present embodiment includes an electric field emission electron source 10 and a transparent electrode 31 disposed opposite to the metal thin film 7 of the electric field emission electron source 10, and the transparent electrode 31 has an electric field emission type.
- a phosphor 32 that emits visible light by an electron beam emitted from the electron source 10 is applied.
- the transparent electrode 31 is made of a transparent conductive film, and is formed on a transparent plate 33 made of a glass substrate.
- the transparent plate 33 on which the transparent electrode 31 and the phosphor 32 are formed is integrated with the field emission electron source 10 via the spacer 34, and the transparent plate 33 and the transparent plate 33 are connected together.
- the internal space surrounded by the antenna 34 and the field emission electron source 10 is set to a predetermined degree of vacuum.
- the phosphor 32 can emit light, and the emission of the phosphor 32 can be displayed outside through the transparent electrode 31 and the transparent plate 33. it can.
- the transparent electrode 3 1 together upon application of a DC ®EV c of 1 k V between the positive electrode and the transparent electrode 3 1 and the thin metal film 7 to the metal thin film 7, the field emission
- a DC mBEV ps of 20 V to the metal thin film 7 selectively with the metal thin film 7 of the pattern electron source 10 as a positive electrode, a light emission pattern corresponding to the selected intersection can be obtained. That is, in the present embodiment, an electron source including the strong electric field drift layer 6 obtained by oxidizing the porous polycrystalline semiconductor layer is used!
- the electron is a thin metal film 7
- the force radiated almost uniformly in the vertical direction within the plane eliminates the need to provide a focusing electrode used in the conventional flat light emitting device, which simplifies the structure and enables cost reduction.
- the pattern accuracy of the electron emission area of the field emission type electron source 10 is high, it is possible to realize a flat light emitting device with less uneven light emission.
- the ohmic electrode 2 is more negative than the n + conductor layer 8, so that leakage current between the conductor layers can be prevented, which is more preferable.
- Fig. 34 shows a schematic configuration when the field emission electron source 1 ° of Embodiment 12 is applied to a display device.
- the porous polycrystalline silicon layer 6 thermally oxidized on the stripe-shaped n + conductor layer 8 and the stripe pattern of the n + conductor layer 8 intersect with each other.
- Each of the metal thin films 7 is formed in a stripe shape.
- a transparent electrode 31 is provided facing the metal thin film 7 of the field emission electron source 10, and the transparent electrode 31 is exposed to visible light by an electron beam emitted from the field emission M electron source 10.
- a phosphor 32 that emits light is applied.
- the transparent electrode 31 is made of a transparent conductive film, and is formed on a transparent plate 33 made of a glass substrate.
- a matrix is formed by arranging the n + region 8 and the gold thin film 7 so as to be orthogonal to each other. That is, the region where the n + region 8 intersects with the metal thin film 7 corresponds to each pixel. Therefore, only a specific pixel can be illuminated by the combination of the metal electrode 7 for applying a voltage and the n + region 8 for applying a voltage.
- a pattern definition of the electron emission area of the field emission electron source is high, and a high-definition display device can be realized.
- the film thickness is reduced by LPCVD so as to cover the lower electrode 12 over the entire main surface side of the insulating substrate 11.
- a Tfl structure is obtained as shown in Fig. 4A. ⁇ It is flattened.
- the film forming conditions of the LPC VD method were as follows: the substrate temperature was 610 ° C., the flow rate of the SiH 4 gas was 600 sqcm, and the degree of vacuum was 20 Pa.
- the method of forming the polycrystalline silicon layer 3 is not limited to the LPCVD method.
- Another method is to form a polycrystalline silicon layer by forming an amorphous silicon layer by a plasma CVD method and then performing an annealing process on the amorphous silicon layer to crystallize the amorphous silicon layer. Good.
- a silicon oxide layer 4 having a thickness of 1 ⁇ m is formed on the polycrystalline silicon layer 3 by a plasma CVD method.
- Conditions for forming the silicon oxide layer 4 S ⁇ temperature 225, S i H 4 gas flow rate 50 sccm, N 2 0 gas flow rate of 875 sccm, a vacuum degree of 133 P a, discharge Pawa scratch 1 5 OW ( The discharge power density was 0.05 WZcm 2 ).
- the method of forming the silicon oxide layer 4 is not limited to the plasma CVD method, and a method such as a thermal oxidation method may be used.
- the silicon oxide layer 4 is patterned into a stripe shape orthogonal to the lower electrode 12 by using photolithography and etching techniques to obtain a structure shown in Fig. 35B. Is obtained.
- a 55 wt% aqueous hydrogen fluoride solution and ethanol were mixed in a ratio of 1: 1 and cooled to 0, and an electrolytic solution was used.
- a platinum electrode (not shown) was used as a negative electrode, and a lower electrode 12 was used as a positive electrode.
- the porous polycrystalline silicon layer 5 is formed in a stripe shape.
- the current density was set to 20 mAZcm2
- the anodizing time was set to 15 seconds
- the film thickness was increased by performing light irradiation with a 500 W tungsten lamp during the anodizing treatment.
- a 1 ⁇ m porous polycrystalline silicon was formed.
- the silicon oxide layer 4 is also etched by the strong electric field solution.
- the silicon oxide layer 4 has a thickness of 1 ⁇ , whereas the silicon oxide layer 4 is Since the etching rate is 0.14 ⁇ m per minute and the anodic oxidation time is 15 seconds, the silicon oxide layer 4 reliably functions as a mask.
- the porous polycrystalline silicon 5 is thermally oxidized by oxidizing the porous polycrystalline silicon 5 to a predetermined depth (that is, oxidizing a part of the porous polycrystalline silicon layer 5) by a rapid thermal oxidation (RTO) method.
- a porous polycrystalline silicon layer 6 was formed, as shown in Fig. 3.
- the structure shown in 5C is obtained.
- the oxidation was set to 900 and the oxidation time was set to 1 hour.
- the negative part of the porous polycrystalline silicon layer 5 is oxidized, but the entire part may be oxidized.
- a thin metal film 7 made of a thin gold film is formed on the main surface side of the insulating substrate 11 by forming a thin gold film in a stripe shape perpendicular to the stripe pattern of the lower electrode 12 by a vapor deposition method using a metal mask.
- an electric field emission electron source 10 having the structure shown in Fig. 4D is obtained.
- gold was used as the metal thin film 7.
- the metal thin film 7 is not limited to gold, and may be a metal having a small work function. In addition to gold, aluminum, chromium, tungsten, Nickel, platinum, and alloys of these metals can be used. Further, in the present embodiment, the thickness of the metal thin film 7 is set to 10 nm, but this thickness is not particularly limited. In the present embodiment, the metal thin film 7 forms the upper electrode.
- the porous polycrystalline silicon layer 5 is formed by performing anodic oxidation using the patterned silicon oxide layer 4 as a mask using photolithography technology and etching technology.
- the pattern accuracy of the crystalline silicon layer 5 is improved, and the contact area between the oxidized porous polycrystalline silicon layer 6 and the metal thin film 7 is determined by the pattern accuracy of the silicon oxide layer 4, so that the cost is low.
- the pattern accuracy of the electron emission area can be improved.
- the field emission electron source 10 of the present embodiment by selecting the lower electrode 12 and the upper electrode 7 and applying a voltage, electrons can be emitted only from the fixed voxels. is there.
- a method for manufacturing the field emission electron source according to the present embodiment will be described with reference to FIGS.
- the manufacturing method of the present embodiment is almost the same as that of the embodiment 15 and is characterized by a pattern-shaped shape of the silicon oxide layer 4. Therefore, the same points as those of the embodiment 15 will be briefly described.
- the LPCV D method is performed so as to cover the lower electrode 12 over the entire main surface of the conductive substrate 11.
- a non-doped polycrystalline silicon layer 3 with ⁇ : 1.5 / X m Gives the structure shown in Fig. 36A.
- the silicon oxide layer 4 is formed on the lower electrode 12 using photolithography and etching techniques.
- the pattern shown in FIG. 4 OB is obtained by patterning above the lower electrode 12 in a lattice shape opened at predetermined intervals along the longitudinal direction of the lower electrode 12.
- the porous polycrystalline silicon layer 5 is formed by performing anodizing treatment with a constant current while irradiating the exposed portion of the polycrystalline silicon layer 3 with light. Next, the porous polycrystalline silicon 5 is oxidized to a certain point by rapid thermal oxidation (RTO) to form a thermally oxidized porous polycrystalline silicon layer 6, and the structure shown in Fig. 4 OC is obtained. can get.
- RTO rapid thermal oxidation
- a metal thin film 7 made of a gold thin film is formed on the main surface side of the insulating substrate 11 by forming a gold thin film in a stripe shape perpendicular to the stripe pattern of the lower electrode 12 by a swallowing method using a metal mask.
- a field emission electron source 10 having the structure shown in Fig. 36D is obtained.
- gold is used as the metal thin film 7.
- the metal thin film 7 is not limited to gold, and may be any metal having a small work function. In addition to gold, aluminum, chromium, tungsten, nickel , Platinum, and alloys of these metals can be used.
- the thickness of the metal thin film 7 is set to 10 nm, but the thickness is not particularly limited. Note that, in the present embodiment, the metal thin film 7 constitutes the upper electrode.
- the porous polycrystalline silicon layer 5 is formed by performing anodic oxidation using the patterned silicon oxide layer 4 as a mask using a photolithography technique and an etching technique.
- the pattern accuracy of the polycrystalline silicon layer 5 is improved, and the contact area between the oxidized porous polycrystalline silicon layer 6 and the metal thin film 7 is determined by the pattern accuracy of the silicon oxide layer 4, so that the cost is low.
- the pattern accuracy of the electron emission area can be improved.
- the lower electrode 12 and the upper surface electrode By selecting each of 7 and applying a voltage, it is possible to emit electrons only from a specific pixel. Further, since the insulating layer 4 is provided below the metal thin film 7 other than the porous polycrystalline silicon layer 6, crosstalk and the 3 ⁇ 4Gi property of electrons are also improved, which is a preferable mode.
- Fig. 37 shows a schematic configuration when the field emission electron source 10 of the fifth embodiment is applied to a display device.
- a field emission electron source 10 is provided with a transparent electrode 31 opposed to a metal thin film 7 of the field emission electron source 10, and the field emission electron source 1 is provided on the transparent electrode 31.
- a phosphor 32 that emits visible light by an electron beam emitted from 0 is applied.
- the transparent electrode 31 is made of a transparent conductive film, and is formed on a transparent plate 33 made of a glass substrate.
- the transparent electrodes 31 are formed in an array in the same plane, and each of the transparent electrodes 31 is formed on the thermally oxidized porous polycrystalline silicon layer 6 of the gold electrode 7.
- the transparent plate 33 on which the transparent electrode 31 and the phosphor 32 are formed is converted into a field emission type electron source 10 through a spacer (not shown).
- a partial space surrounded by the spacer and the field emission electron source 10 is set to a predetermined degree of vacuum. Therefore, the combination of the metal electrode 7 (hereinafter referred to as the upper electrode 7) to which Iff is applied and the lower electrode 12 enables the frost wire to be emitted only from a specific pixel, and is arranged to face the pixel. Only the phosphor 32 that has been emitted can emit light, and the light emission of the phosphor 32 can be displayed outside through the transparent electrode 31 and the transparent plate 33.
- the transparent electrode 31 is used as a positive electrode with respect to the upper electrode 7, a DC voltage of 1 kV is applied between the transparent electrode 31 and the upper electrode 7, and the upper electrode 7 is used as a positive electrode.
- a DC voltage of 2 OV between the city electrode 7 and the lower electrode 12 only the phosphor 32 corresponding to a specific electron source pixel can be illuminated.
- the pattern accuracy of the electron emission area of the field emission electron source 10 is determined by the pattern accuracy of the silicon oxide layer 4, the pattern accuracy of the electron emission area is high, and a high-definition display can be realized. .
- electrons can be emitted from a desired region of the surface electrode, and the force can be reduced.
- a circuit for switching the voltage of several hundred V to several kV applied to the collector electrode becomes unnecessary. Therefore, a high-precision field emission It® electron source array capable of selectively emitting electrons from a desired region of the surface electrode can be reduced in cost and size.
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Cold Cathode And The Manufacture (AREA)
- Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99940499A EP1026721B1 (en) | 1998-08-26 | 1999-08-26 | Array of field emission electron sources and method of producing the same |
DK99940499.9T DK1026721T3 (da) | 1998-08-26 | 1999-08-26 | Array af feltemissionselektronkilder og fremgangsmåde til fremstilling deraf |
AT99940499T ATE517427T1 (de) | 1998-08-26 | 1999-08-26 | Feldemissionselektronenquellenmatrix und deren herstellungsverfahren |
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23960698 | 1998-08-26 | ||
JP10/239606 | 1998-08-26 | ||
JP10/272334 | 1998-09-25 | ||
JP27233498 | 1998-09-25 | ||
JP10/363965 | 1998-12-22 | ||
JP10/363970 | 1998-12-22 | ||
JP36396598A JP2000188057A (ja) | 1998-12-22 | 1998-12-22 | 電子源 |
JP36397098A JP3084272B2 (ja) | 1998-12-22 | 1998-12-22 | 電界放射型電子源 |
JP14673999A JP3076561B1 (ja) | 1999-05-26 | 1999-05-26 | 電界放射型電子源およびその製造方法 |
JP11/146739 | 1999-05-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000013197A1 true WO2000013197A1 (fr) | 2000-03-09 |
Family
ID=27527774
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1999/004613 WO2000013197A1 (fr) | 1998-08-26 | 1999-08-26 | Ensemble source a emission de champ, son procede de production, et son utilisation |
Country Status (9)
Country | Link |
---|---|
US (1) | US6794805B1 (ja) |
EP (1) | EP1026721B1 (ja) |
KR (1) | KR100366805B1 (ja) |
CN (1) | CN1216393C (ja) |
AT (1) | ATE517427T1 (ja) |
DK (1) | DK1026721T3 (ja) |
ES (1) | ES2372168T3 (ja) |
TW (1) | TW442813B (ja) |
WO (1) | WO2000013197A1 (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE261611T1 (de) * | 1994-09-22 | 2004-03-15 | Canon Kk | Verfahren zur herstellung einer elektronen- emittierenden einrichtung sowie einer elektronenquelle und eines bilderzeugungsgerätes mit derartigen elektronen-emittierenden einrichtungen |
GB0025634D0 (en) * | 2000-10-18 | 2000-12-06 | Smiths Industries Plc | Light-emitting devices and displays |
TWI286773B (en) * | 2000-10-26 | 2007-09-11 | Matsushita Electric Works Ltd | Field emission type electron source |
JP3687522B2 (ja) * | 2000-10-26 | 2005-08-24 | 松下電工株式会社 | 電界放射型電子源 |
US6771010B2 (en) | 2001-04-30 | 2004-08-03 | Hewlett-Packard Development Company, L.P. | Silicon emitter with low porosity heavily doped contact layer |
US20060012304A1 (en) * | 2004-07-13 | 2006-01-19 | Seung-Hyun Son | Plasma display panel and flat lamp using oxidized porous silicon |
KR100670351B1 (ko) * | 2005-08-24 | 2007-01-16 | 삼성에스디아이 주식회사 | 플라즈마 디스플레이 패널 |
KR100659099B1 (ko) * | 2005-10-11 | 2006-12-19 | 삼성에스디아이 주식회사 | 표시 장치 |
KR100659100B1 (ko) * | 2005-10-12 | 2006-12-21 | 삼성에스디아이 주식회사 | 디스플레이 장치와 이의 제조 방법 |
JP2007294126A (ja) * | 2006-04-21 | 2007-11-08 | Canon Inc | 電子放出素子、電子源、画像表示装置、及び、電子放出素子の製造方法 |
JP2007311329A (ja) | 2006-05-19 | 2007-11-29 | Samsung Sdi Co Ltd | 発光装置、発光装置の電子放出ユニット製造方法、及び表示装置 |
CN101609778B (zh) * | 2009-07-20 | 2011-11-09 | 浙江师范大学 | 多孔硅场发射发光二极管阵列及其制作技术 |
US8642371B2 (en) * | 2011-04-06 | 2014-02-04 | Shamsoddin Mohajerzadeh | Method and system for fabricating ion-selective field-effect transistor (ISFET) |
CN102360999A (zh) * | 2011-11-08 | 2012-02-22 | 福州大学 | 柔性可控有机pn结场发射电子源 |
US10032870B2 (en) * | 2015-03-12 | 2018-07-24 | Globalfoundries Inc. | Low defect III-V semiconductor template on porous silicon |
CN109285740B (zh) * | 2018-11-12 | 2024-02-09 | 北京大学 | 一种片上微型电子源及其制造方法 |
DE102020113351A1 (de) * | 2020-05-18 | 2021-11-18 | Dbt Gmbh | Elektronenemitterstruktur, Äußerer-Photoeffekt-Emitter, Partikelsammelvorrichtung Tunnel- Flächenemitter halbleiterbasierter Direktemitter, und Flüssigkeitsionisator mit derselben, Verfahren zum Erzeugen von freien Elektronen und Verfahren zum Sammeln von Partikeln |
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JPH06140502A (ja) * | 1992-10-26 | 1994-05-20 | Nec Corp | 半導体装置の製造方法 |
JPH08111166A (ja) * | 1994-10-12 | 1996-04-30 | Matsushita Electron Corp | 電子パルス放出装置および表示装置 |
JPH0992130A (ja) * | 1995-09-25 | 1997-04-04 | Olympus Optical Co Ltd | 電荷発生器及びその製造方法 |
JPH09259795A (ja) * | 1996-03-26 | 1997-10-03 | Pioneer Electron Corp | 冷電子放出表示装置 |
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JPH05342995A (ja) * | 1992-06-08 | 1993-12-24 | Olympus Optical Co Ltd | Mis型冷陰極電子放出装置 |
TW391022B (en) * | 1997-10-29 | 2000-05-21 | Mitsubishi Rayon Co | Field emission electron source, method of producing the same, and use of the same |
KR100338140B1 (ko) | 1998-09-25 | 2002-05-24 | 이마이 기요스케 | 전계 방사형 전자원 |
TW436837B (en) | 1998-11-16 | 2001-05-28 | Matsushita Electric Works Ltd | Field emission-type electron source and manufacturing method thereof and display using the electron source |
US6498426B1 (en) | 1999-04-23 | 2002-12-24 | Matsushita Electric Works, Ltd. | Field emission-type electron source and manufacturing method thereof |
SG90182A1 (en) | 1999-10-18 | 2002-07-23 | Matsushita Electric Works Ltd | Field emission-type electron source and manufacturing method thereof |
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1999
- 1999-08-25 US US09/382,956 patent/US6794805B1/en not_active Expired - Fee Related
- 1999-08-26 EP EP99940499A patent/EP1026721B1/en not_active Expired - Lifetime
- 1999-08-26 KR KR10-2000-7004437A patent/KR100366805B1/ko not_active IP Right Cessation
- 1999-08-26 DK DK99940499.9T patent/DK1026721T3/da active
- 1999-08-26 TW TW088114664A patent/TW442813B/zh not_active IP Right Cessation
- 1999-08-26 CN CN998019259A patent/CN1216393C/zh not_active Expired - Fee Related
- 1999-08-26 ES ES99940499T patent/ES2372168T3/es not_active Expired - Lifetime
- 1999-08-26 AT AT99940499T patent/ATE517427T1/de active
- 1999-08-26 WO PCT/JP1999/004613 patent/WO2000013197A1/ja active IP Right Grant
Patent Citations (4)
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JPH06140502A (ja) * | 1992-10-26 | 1994-05-20 | Nec Corp | 半導体装置の製造方法 |
JPH08111166A (ja) * | 1994-10-12 | 1996-04-30 | Matsushita Electron Corp | 電子パルス放出装置および表示装置 |
JPH0992130A (ja) * | 1995-09-25 | 1997-04-04 | Olympus Optical Co Ltd | 電荷発生器及びその製造方法 |
JPH09259795A (ja) * | 1996-03-26 | 1997-10-03 | Pioneer Electron Corp | 冷電子放出表示装置 |
Also Published As
Publication number | Publication date |
---|---|
EP1026721A4 (en) | 2006-12-06 |
US6794805B1 (en) | 2004-09-21 |
EP1026721A1 (en) | 2000-08-09 |
KR20010031414A (ko) | 2001-04-16 |
ATE517427T1 (de) | 2011-08-15 |
ES2372168T3 (es) | 2012-01-16 |
CN1287678A (zh) | 2001-03-14 |
CN1216393C (zh) | 2005-08-24 |
EP1026721B1 (en) | 2011-07-20 |
DK1026721T3 (da) | 2011-10-10 |
TW442813B (en) | 2001-06-23 |
KR100366805B1 (ko) | 2003-01-09 |
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