WO2000011819A1

WO2000011819A1 - Device for word period regeneration during data transmission by means of pulse position modulation

Info

Publication number: WO2000011819A1
Application number: PCT/DE1999/002614
Authority: WO
Inventors: Volker Jungnickel; Adnan Can; Clemens Von Helmolt
Original assignee: HEINRICH-HERTZ-INSTITUT FüR NACHRICHTENTECHNIK BERLIN GMBH
Priority date: 1998-08-18
Filing date: 1999-08-18
Publication date: 2000-03-02
Also published as: DE19837324A1

Abstract

The invention relates to a device for word period regeneration during data transmission by means of pulse position modulation. Said device comprises a word period regeneration unit (5) which allows for retrieval of a word period from input pulse position modulated data. Said unit (5) comprises a shift register module which is clocked by a slot period and contains at least one shift register (16, 18, 20). The memory elements of the (each) shift register (16, 18, 20) whose number corresponds to the number of time windows within a word frame determined by the word period, are each connected to inputs of a logic exclusive-OR gate (17, 19, 20), the number of said inputs corresponding to the number of memory elements. In case the word frame corresponds to the limits of the (each) shift register (16, 18, 20), an output signal containing the frequency and phase of the word period safely appears on the output of the (each) exclusive-OR gate (17, 19, 20) when, according to the coding specification during pulse position modulation, a data pulse is present precisely in the (each) allocated shift register (16, 18, 20).

Description

Device for word clock regeneration in data transmission using pulse position modulation

The invention relates to a device for word clock regeneration in data transmission by means of pulse position modulation with a word clock regeneration unit having a shift register module clocked by a slot clock, with which a word clock can be recovered from incoming pulse position modulated data.

Such a device is from the article "Word Timing Recovery in Direct Detection Optical PPM Communication Systems with Avalanche Photodiodes Using a Phase Lock Loop" by X. Sun and FM Davidson, published in IEEE Transactions on Communications, Vol. 38, No. 5, May 1990, pages 666 to 673. The known device has a word clock regeneration unit with a shift register module which is equipped with a single shift register with a depth of 2 bits. Received pulse position modulated data in the form of data pulses can be fed to the shift register in a clocked manner via a slot clock used in pulse position modulation. The two memory elements of the shift register are each connected to an input of a logic AND gate, the output of which is connected to a frequency and phase control module in the form of a so-called phase lock loop, abbreviated PLL. An output signal occurs at the output of the AND gate if and only if two data pulses form two consecutive word frames as so-called back-to-back pulses. This natural synchronization pattern occurs with a frequency and phase correlated to the word clock, but the occurrence is subject to statistical laws. In particular, back-to-back pulses occur less frequently on average over time, the more time windows per word frame are used for pulse position modulation. In the known device, a natural synchronization pattern for the word is thus used at a maximum data transmission rate. clock regeneration is used, but here the disadvantage arises that the power density of the signal to be used is relatively low, especially at high bit numbers per data word.

To avoid this disadvantage, for example, in the article "Acquisition Sequences in PPM Communications" by R. Gagliardi, J. Robbins and H. Taylor, published in IEEE Transactions on Information Theory, Vol. IT-33, No. 5, September 1987, pages 738 ff., Proposed to insert specific PPM-compliant word sequences used for recognition as an artificial synchronization pattern in a data transmission by means of pulse position modulation into the sequence of data pulses in order to regenerate the word clock on the receiver side. Furthermore, for example in the article "Spectral Characterization and Frame Synchronization of Optical Fiber Digital PPM" by J. Elmirghani, R. Cryan and M. Clayton, published in Electronics Letters, Vol. 28, No. 16 on July 30, 1992, pages 1482, 1483 in a data transmission using pulse position modulation, in order to avoid overlaps at the end of each word frame, to insert a protection interval from which the word clock can be regenerated. However, these proposals have the disadvantage that the usable bandwidth of the data transmission is reduced.

The invention has for its object to provide a device of the type mentioned, which provides a signal for regeneration of the word clock with a relatively high power density with a relatively low circuit complexity using the maximum possible bandwidth in data transmission.

This object is achieved according to the invention with a device of the type mentioned at the outset in that the shift register module has at least one shift register, the number of memory elements of the or each shift register of the number of time windows within a given by the word clock Word frame corresponds, and that the memory elements of the or each shift register are each connected to inputs in a number of a logical exclusive-OR gate corresponding to the number of memory elements.

Through the use of logic components, the device according to the invention can be constructed relatively simply in terms of circuitry, the unit comprising a shift register and an exclusive-OR gate with a view to reducing the errors in word clock detection even with data to be transmitted with a high number of bits can cascade per data word in a simple manner. The maximum possible bandwidth can be used, since the transmitted word sequences are evaluated without additional information on the word clock regeneration. By utilizing the coding rule on which the pulse position modulation is based, that, as can be detected by the or each exclusive-or gate, there is exactly one data pulse in each word frame, each word transmitted can be exploited for word clock regeneration with the result that the power density of an associated one Signal is relatively high.

In a particularly expedient development, the device according to the invention has at least two units, each consisting of a shift register and an exclusive-OR gate, the word clock regeneration unit comprising a logical AND gate with a number of inputs corresponding to the number of exclusive-OR gates and the Output of each exclusive-OR gate is connected to an input of the AND gate. An output signal therefore occurs at the output of the AND gate precisely when exactly one data pulse is detected per exclusive-OR gate in accordance with the coding regulation in pulse position modulation. Expressed in a descriptive way, the shift registers are thus exactly in the word cycle. This cascading of units from shift registers with assigned exclusive-OR gates can significantly improve the detection of the word frame with an acceptable circuit outlay. For a further stabilization of the output signal of the AND gate of the aforementioned development, it is expedient that the output of the AND gate is connected to a frequency and phase control module, for example in the form of a so-called phase lock loop, abbreviated PLL. In this way, occasional errors in the recognition of the word clock by the shift register module are effectively suppressed.

The device according to the invention expediently has a data decoding unit which can be acted upon by the pulse position modulated data, the word clock and the slot clock and by means of which the pulse position modulated data can be converted into serial output data.

In an expedient embodiment of the data decoding unit, a decoding shift register which can be acted upon by the pulse position-modulated data and has a number of memory elements corresponding to the number of time windows within a word frame, a buffer which is arranged downstream of the decoding shift register and can be loaded with the word clock, a decoding module which is arranged after the buffer and a decoding module which is arranged downstream of the decoding module provided, the converter module being connected to a bit clock generator which can be acted upon by the slot clock and the word clock and by means of which the bit clock of the serial output data can be generated.

It is also expedient in the device according to the invention that a coding regeneration unit is provided, with which the slot clock of the pulse position modulated data can be regenerated.

Further expedient refinements are the subject of the subclaims and the following description of a preferred exemplary embodiment of the invention with reference to the figures of the drawing. Show it: 1 is a block diagram of a preferred embodiment of the invention with a coding regeneration unit, a word clock regeneration unit and a data decoding unit,

2 in a block diagram the structure of the coding regeneration unit according to FIG. 1,

3 shows a block diagram of the structure of the word clock regeneration unit according to FIGS. 1 and

FIG. 4 shows the structure of the data decoding unit according to FIG. 1 in a block diagram.

1 shows a preferred embodiment of the invention in a block diagram. Data can be fed via an input data line 1 to a coding regeneration unit 2 from a transmission unit not shown in FIG Slot clock predetermined time window exactly one data pulse is set. The temporal position of each data pulse within the assigned word frame is therefore unique for a specific word to be transmitted. For example, a word composed of four bits is uniquely encoded in a so-called 16 PPM coding with 16 time windows within a word frame. With the coding regeneration unit 2, the slot clock can be regenerated from the supplied data pulses and the received data pulses, which may be noisy, can be converted into standard data pulses with predetermined characteristics.

Via a first pulse line 3 connected on the output side to the coding regeneration unit 2 and a first slot clock line 4, the standard data impulses or the slot clock can be fed into a downstream word clock regeneration unit 5. With the word clock regeneration unit 5, which has a shift register module with at least one shift register, the word clock of the pulse position modulation used in the data transmission can be regenerated from the standard data pulses in a manner explained in more detail below.

1 has a data decoding unit 6 which is connected to the output of the word clock regeneration unit 5 via a second pulse line 7, a second slot clock line 8 and a word clock line 9. With the data decoding unit 6, the transmitted pulse-position-modulated data can be converted into serial output data using the standard data pulses, the slot clock and the word clock. The serial output data or a bit clock of the serial output data can be output from the data decoding unit 6 for further processing via a data output line 10 and a bit clock output line 11.

FIG. 2 shows the structure of the coding regeneration unit 2 according to FIG. 1 in a block diagram. The coding regeneration unit 2 according to FIG. 2 has a pulse regeneration module 12 designed as a D flip-flop, to whose D input 13 the input data line 1 is connected. The input data line 1 is also routed to an input of a slot clock regeneration module 14, with which a slot clock on which the pulse position modulation used is based can be regenerated in a manner known per se from the transmitted data pulses. The slot clock recovered from the data pulses by means of the slot clock regeneration module 14 can be fed into a clock input 15 of the pulse regeneration module 12 and into the first slot clock line 4. With the pulse regeneration module 12, the transmitted data pulses fed in via the input data line 1 can thus be converted in time and in terms of their signal level into similar standard data pulses. which can be fed into the first pulse line 3 via a data output of the pulse regeneration module 12.

FIG. 3 shows in a block diagram the structure of the word clock regeneration unit 5 according to FIG. 1, which is arranged downstream of the coding regeneration unit 2 according to FIG. 2, with a shift register module having a plurality of shift registers. The word clock regeneration unit 5 has a first regeneration shift register 16, to which the standard data pulses running in the first pulse line 3 can be fed from the slot clock supplied via the first slot clock line 4. The number of storage elements of the first regeneration shift register 16 corresponds to the number of time windows within a word frame. With 16-PPM coding, for example, these are 16 memory elements. The memory elements of the first regeneration shift register 16 are each connected to an input of a first exclusive-OR gate, abbreviated to XOR gate 17, the number of inputs corresponding to the number of memory elements of the first regeneration shift register 16. An output signal only occurs at the output of the XOR gate 17 if exactly one standard data pulse is present in the first regeneration shift register 16.

In this exemplary embodiment, the second regeneration shift register 16 is followed by a second regeneration shift register 18 with a number of memory elements corresponding to the number of time windows within a word frame, to which the standard data pulses can also be fed in a controlled manner via the passed slot clock. The memory elements of the second regeneration shift register 18 are correspondingly connected to the inputs of a second exclusive-OR gate, abbreviated to XOR gate 19, at the output of which an output signal is also present when a single standard data pulse is present in the second regeneration shift register 18. Expediently, the second regeneration shift register 19 is followed by further regeneration shift registers with exclusive-OR gates, abbreviated to XOR gates, connected to the memory elements, with corresponding interconnection, of which only the last regeneration shift register 20 in the direction of the standard data pulses and the slot cycle with the last exclusive-or- Gate, abbreviated last XOR gate 21, is shown. After leaving the last regeneration shift register 20, the standard data pulses are fed into the second pulse line 7 and the slot clock into the second slot clock line 8.

The outputs of the number of XOR gates 17, 19, 21 are each connected to an input of a logic AND gate 22, so that an output signal only occurs at the output of the AND gate 22 if all regeneration shift registers 16, 18, 20 exactly one standard data pulse is present. This output signal contains a frequency component, the so-called word clock line, which corresponds in frequency and phase to the word clock. With regard to a suitable stabilization of the word clock line, the output signal of the AND gate 22 can be fed to a frequency and phase control module 23 designed as a so-called phase lock loop, abbreviated PLL. The frequency and phase control module 23 is followed by a limiting amplifier 24 for generating a digitized word clock to amplify the stabilized word clock, to whose output the word clock line 9 is connected.

For a design without frequency and phase control module 23, the number of regeneration shift registers 16, 18, 20 and of XOR gates 17, 19, 20 is determined according to a predetermined permissible maximum word error rate and has, for example, with 16 PPM coding and a word error rate of better than 10 ^"9 a value of about 320. FIG. 4 shows in a block diagram the structure of the data decoding unit 6 according to FIG. 1. The data decoding unit 6 according to FIG. 4 has a decoding shift register 25 with a number of memory elements corresponding to the number of time windows within a word frame, which is different from that in the second slot clock line 8 applied slot clock controlled is fed with the standard data pulses running in the second pulse line 7. The individual memory elements of the decoding shift register 25 are each assigned to assigned memory elements of a buffer memory 26 which is clocked by the word clock applied in the word clock line 9, so that when the correct word clock is present, exactly one standard data pulse is contained in the buffer memory 26, the memory content of which is then synchronous with that Word clock parallel to a decoding module 27 can be fed. The decoding module 27 can be used, for example, to convert the standard data pulses into serial output data into a four-valued binary code, for example as shown in FIG.

4 has a bit clock generator 28 which is connected to the second slot clock line 8 and the word clock line 9. The bit clock of the transmitted data can be calculated with the bit clock generator 28 on the basis of the word clock and the slot clock and a converter module 29 and the bit clock output line 11 can be fed.

The binary codes determined by means of the decoding module 27 can be fed to the converter module 29 clocked by the bit clock generated by the bit clock generator 28, with which the binary codes can be converted into serial output data. The serial output data can be fed into the data output line 10 for further processing.

Claims

PATENT CLAIMS

1. Device for word clock regeneration during data transmission by means of pulse position modulation with one on one

Word clock regeneration unit having a slot-clocked shift register module, with which a word clock can be retrieved from incoming pulse position-modulated data, characterized in that the shift register module has at least one shift register (16, 18, 20), the number of memory elements of the or each shift register (16, 18, 20 ) corresponds to the number of time windows within a word frame specified by the word clock, and that the memory elements of the or each shift register (16, 18, 20) each have inputs in one of the

Number of memory elements corresponding number of a logical exclusive-OR gate (17, 19, 21) are connected.

2. Device according to claim 1, characterized in that the shift register module has at least two units each consisting of a shift register (16, 18, 20) and an exclusive-OR gate (17, 19, 21) and that the word clock regeneration unit (5) a logical AND gate (22) with one of the number of exclusive OR gates (17, 19,

21) comprises a corresponding number of inputs, the output of each exclusive-OR gate (17, 19, 21) being connected to an input of the AND gate (22).

3. Apparatus according to claim 2, characterized in that the output of the AND gate (22) is connected to a frequency and phase control module (23).

4. Device according to one of claims 1 to 3, characterized in that one of the pulse position modulated Data, the word clock and the slot clock actable data decoding unit (6) is provided, with which the pulse position modulated data can be converted into serial output data.

5. The device according to claim 4, characterized in that the data decoding unit (6) has a decoding shift register (25) which can be acted upon by the pulse-position modulated data and has a number of memory elements corresponding to the number of time windows within a word frame, and a decoder shift register (25) arranged downstream of it. The buffer (26) which can be loaded with the word clock, a decoding module (27) downstream of the buffer (26) and a converter module (29) downstream of the decoding module (27), the converter module (29) being connected to a bit clock generator which can be loaded by the slot clock and the word clock (28), with which the bit clock of the serial output data can be generated, is connected.

6. Device according to one of claims 1 to 5, characterized in that a coding regeneration unit (2) is provided with which the slot clock of the pulse position modulated data can be regenerated.