WO1999065070A3 - Method of manufacturing a semiconductor device comprising a mos transistor - Google Patents

Method of manufacturing a semiconductor device comprising a mos transistor Download PDF

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Publication number
WO1999065070A3
WO1999065070A3 PCT/IB1999/001003 IB9901003W WO9965070A3 WO 1999065070 A3 WO1999065070 A3 WO 1999065070A3 IB 9901003 W IB9901003 W IB 9901003W WO 9965070 A3 WO9965070 A3 WO 9965070A3
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric layer
drain
silicon substrate
source
gate electrode
Prior art date
Application number
PCT/IB1999/001003
Other languages
French (fr)
Other versions
WO1999065070A2 (en
Inventor
Jurriaan Schmitz
Pierre H Woerlee
Original Assignee
Koninkl Philips Electronics Nv
Philips Svenska Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Svenska Ab filed Critical Koninkl Philips Electronics Nv
Priority to EP99921071A priority Critical patent/EP1036409A2/en
Priority to JP2000553989A priority patent/JP2002518827A/en
Publication of WO1999065070A2 publication Critical patent/WO1999065070A2/en
Publication of WO1999065070A3 publication Critical patent/WO1999065070A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation

Abstract

The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (1A) is provided with a dielectric layer (1B) at the location where a source (3) and drain (4) are to be formed, which dielectric layer includes a thermal oxide layer (1B) to be formed as the starting layer. The source (3) and/or drain (4) is/are provided with LDD regions (3A, 4A) and the remaining parts (3B, 4B) of the source (3) and drain (4) are provided by an ion implantation (I1) of doping atoms into the silicon substrate (10, 11). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (2), in particular in the case of very short lengths of the gate electrode (2). In a method according to the invention, the LDD regions (3A, 4A) are made as follows: in a first step, suitable doping atoms (D) are implanted into the dielectric layer (1B), in a second ion implantation (I2), and subsequently in a second step, a part of the doping atoms (D) is diffused from the dielectric layer (1B) into the silicon substrate (10, 11), whereby the LDD regions (3A, 4A) are formed. This method enables a MOST with excellent properties to be obtained, for example with a flatter profile of the threshold voltage versus the gate-electrode (2) length (curve 130) than in conventionally made MOSTs (curve 131). This result is obtained in a simple and reproducible manner.
PCT/IB1999/001003 1998-06-11 1999-06-03 Method of manufacturing a semiconductor device comprising a mos transistor WO1999065070A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP99921071A EP1036409A2 (en) 1998-06-11 1999-06-03 Method of manufacturing a semiconductor device comprising a mos transistor
JP2000553989A JP2002518827A (en) 1998-06-11 1999-06-03 Method of manufacturing semiconductor device including MOS transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98201958 1998-06-11
EP98201958.0 1998-06-11

Publications (2)

Publication Number Publication Date
WO1999065070A2 WO1999065070A2 (en) 1999-12-16
WO1999065070A3 true WO1999065070A3 (en) 2000-04-27

Family

ID=8233800

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1999/001003 WO1999065070A2 (en) 1998-06-11 1999-06-03 Method of manufacturing a semiconductor device comprising a mos transistor

Country Status (4)

Country Link
US (1) US6303453B1 (en)
EP (1) EP1036409A2 (en)
JP (1) JP2002518827A (en)
WO (1) WO1999065070A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW506080B (en) * 2001-02-16 2002-10-11 United Microelectronics Corp Manufacture method of deep sub-micro complementary metal oxide semiconductor with ultrashallow junction
EP1808885A1 (en) * 2002-06-26 2007-07-18 Semequip, Inc. A semiconductor device and method of fabricating a semiconductor device
US7723233B2 (en) 2002-06-26 2010-05-25 Semequip, Inc. Semiconductor device and method of fabricating a semiconductor device
KR100480921B1 (en) * 2003-07-24 2005-04-07 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
EP1958245B1 (en) 2005-12-09 2013-10-16 Semequip, Inc. Method for the manufacture of semiconductor devices by the implantation of carbon clusters
US7919402B2 (en) 2006-12-06 2011-04-05 Semequip, Inc. Cluster ion implantation for defect engineering
US9472628B2 (en) 2014-07-14 2016-10-18 International Business Machines Corporation Heterogeneous source drain region and extension region
US11355342B2 (en) * 2019-06-13 2022-06-07 Nanya Technology Corporation Semiconductor device with reduced critical dimensions and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0681321A1 (en) * 1994-05-03 1995-11-08 Siemens Aktiengesellschaft Method of manufacturing LDD-MOSFET's
US5496751A (en) * 1993-05-07 1996-03-05 Vlsi Technology, Inc. Method of forming an ESD and hot carrier resistant integrated circuit structure
US5702986A (en) * 1995-12-05 1997-12-30 Micron Technology, Inc. Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457060A (en) * 1994-06-20 1995-10-10 Winbond Electronics Corporation Process for manufactuirng MOSFET having relatively shallow junction of doped region
US5518945A (en) * 1995-05-05 1996-05-21 International Business Machines Corporation Method of making a diffused lightly doped drain device with built in etch stop
US5998272A (en) * 1996-11-12 1999-12-07 Advanced Micro Devices, Inc. Silicidation and deep source-drain formation prior to source-drain extension formation
KR100226758B1 (en) * 1996-12-14 1999-10-15 구본준 Method of manufacturing cmosfet
US6087234A (en) * 1997-12-19 2000-07-11 Texas Instruments - Acer Incorporated Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5496751A (en) * 1993-05-07 1996-03-05 Vlsi Technology, Inc. Method of forming an ESD and hot carrier resistant integrated circuit structure
EP0681321A1 (en) * 1994-05-03 1995-11-08 Siemens Aktiengesellschaft Method of manufacturing LDD-MOSFET's
US5702986A (en) * 1995-12-05 1997-12-30 Micron Technology, Inc. Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges

Also Published As

Publication number Publication date
EP1036409A2 (en) 2000-09-20
JP2002518827A (en) 2002-06-25
US6303453B1 (en) 2001-10-16
WO1999065070A2 (en) 1999-12-16

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