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WO1999044147A3 - VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.) - Google Patents

VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.)

Info

Publication number
WO1999044147A3
WO1999044147A3 PCT/DE1999/000504 DE9900504W WO9944147A3 WO 1999044147 A3 WO1999044147 A3 WO 1999044147A3 DE 9900504 W DE9900504 W DE 9900504W WO 9944147 A3 WO9944147 A3 WO 9944147A3
Authority
WO
Grant status
Application
Patent type
Prior art keywords
configuration
data
hierarchy
units
level
Prior art date
Application number
PCT/DE1999/000504
Other languages
English (en)
French (fr)
Other versions
WO1999044147A2 (de )
Inventor
Robert Muench
Martin Vorbach
Original Assignee
Robert Muench
Pact Inf Tech Gmbh
Martin Vorbach
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Abstract

Anststt wie bischer eine zentrale und globale Einheit in einen Baustein zu integrieren, welche alle Konfigurations-Anforderungen bearbeitet, existieren nun eine Mehrzahl von hierarchisch angeordneten aktiven Einheiten, welche diese Aufgabe übernehmen können. Dabei wird eine Anfoderung von der tiefesten Ebene nur dann an die nächst höher gelegene Ebene weitergeleitet, wenn die Anforderung nicht bearbeitet werden konnte. Die höchst gelegene Ebene ist an einen internen oder externen übergeordneten Konfigurationspeicher angeschlossen, der alle jemals für diesen Programlauf, benötigten Konfiguraiondaten enthält. Durch die Baumstruktur der Konfigurationseinheiten wird eine Art Cacheing der Konfigurationsdaten erreicht. Zugriffe auf Konfigurationen finden hauptsächlich lokal statt. Im ungünstigsten Fall muss eine Konfiguration aus den übergeordneten Konfigurationsspeicher geladen werden, falls die betreffenden Datan in keiner der hierarchisch angeordneten CTs vorhanden sind.
PCT/DE1999/000504 1998-02-25 1999-02-25 VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.) WO1999044147A3 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE1998107872 DE19807872A1 (de) 1998-02-25 1998-02-25 Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
DE19807872.2 1998-02-25

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US09623052 US6480937B1 (en) 1998-02-25 1999-02-25 Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--
CA 2321877 CA2321877A1 (en) 1998-02-25 1999-02-25 Method for cacheing configuration data of data flow processors and modules with a two- or multidimensional programmable cell structure (fpgas, dpgas or similar) according to a hierarchy
JP2000533829A JP4215394B2 (ja) 1998-02-25 1999-02-25 データフロープロセッサおよび2次元またはそれ以上の次元のプログラミング可能なセル構造をもつコンポーネントにおけるコンフィグレーションデータの階層的キャッシュ方法
DE1999501447 DE59901447D1 (de) 1998-02-25 1999-02-25 VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.)
DE1999180312 DE19980312D2 (de) 1998-02-25 1999-02-25 Verfahren zum hierarchischen Cachen von Konfigurationsdaten von Datenflußprozessoren und Bausteinen mit zwei- oder mehrdimensionaler programmierbarer SZellstruktur (FPGAs, DPGAs, o. dgl.)
EP19990913087 EP1057117B1 (de) 1998-02-25 1999-02-25 VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.)
US13491894 US8468329B2 (en) 1999-02-25 2012-06-08 Pipeline configuration protocol and configuration unit communication
US14465157 US20150033000A1 (en) 1999-02-25 2014-08-21 Parallel Processing Array of Arithmetic Unit having a Barrier Instruction

Related Child Applications (3)

Application Number Title Priority Date Filing Date
US09623052 A-371-Of-International US6480937B1 (en) 1998-02-25 1999-02-25 Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--
US10191926 Continuation US6687788B2 (en) 1998-02-25 2002-07-09 Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
US10191926 Continuation-In-Part US6687788B2 (en) 1998-02-25 2002-07-09 Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)

Publications (2)

Publication Number Publication Date
WO1999044147A2 true WO1999044147A2 (de) 1999-09-02
WO1999044147A3 true true WO1999044147A3 (de) 1999-10-28

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/DE1999/000505 WO1999044120A3 (de) 1998-02-25 1999-02-25 VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.)
PCT/DE1999/000504 WO1999044147A3 (de) 1998-02-25 1999-02-25 VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.)

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/000505 WO1999044120A3 (de) 1998-02-25 1999-02-25 VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.)

Country Status (7)

Country Link
US (3) US6571381B1 (de)
EP (4) EP1057102B1 (de)
JP (2) JP4215394B2 (de)
CN (2) CN1298520A (de)
CA (2) CA2321877A1 (de)
DE (3) DE19807872A1 (de)
WO (2) WO1999044120A3 (de)

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