WO1999034604A2 - Method for reducing the storage and number of computations required for inverse quantization and inverse scan in mpeg video decoding - Google Patents
Method for reducing the storage and number of computations required for inverse quantization and inverse scan in mpeg video decoding Download PDFInfo
- Publication number
- WO1999034604A2 WO1999034604A2 PCT/IB1998/002089 IB9802089W WO9934604A2 WO 1999034604 A2 WO1999034604 A2 WO 1999034604A2 IB 9802089 W IB9802089 W IB 9802089W WO 9934604 A2 WO9934604 A2 WO 9934604A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- level
- run
- matrix
- inverse quantization
- inverse
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/124—Quantisation
- H04N19/126—Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/124—Quantisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
Definitions
- This invention relates in general to video decoding and in particular to a method and device for reducing the storage and number of computations required for inverse quantization and inverse scan operations in an MPEG video decoder.
- the MPEG video decoding process begins with data stored in an input buffer called a rate buffer. From this buffer data is removed in chunks that represent whole video frames. Each video frame is comprised of a substructure of slices, which in turn are made up of macroblocks which in turn are made up of blocks. A block is an 8 x 8 matrix of discrete cosine transform coefficients (DCT).
- DCT discrete cosine transform coefficients
- a decoder 20 which performs the typical processing steps required to decompress a block of video data. These steps include fixed length decoding (FLD) 22, variable length decoding 24 (VLD), run/level decoding 26 (RLD), inverse zig-zag 28 (or inverse alternate scan) (IZZ), inverse differential pulse code modulation and inverse quantization 32 (IDPCM + IQ), inverse discrete cosine transform 34 (IDCT) and motion compensation 36 (MC).
- FLD fixed length decoder 22
- the variable length decoder 24 decodes the remaining information of each macro block into 1 x N vectors, of runs and levels. The run indicates the number of zeros that proceed a non-zero value.
- the level is the non-zero value.
- the inverse quantizer 32 performs inverse quantization on each of the expanded matrix values by multiplying the expanded matrix by another 8 by 8 matrix containing scalar values.
- the inverse discrete cosine transform 34 transforms a block of frequency domain DCT coefficients into a block of spatial pixel values.
- the invention accordingly comprises the several steps and the relation of one or more of such steps with respect to each of the others, and the apparatus embodying features of construction, combinations of elements and arrangement of parts which are adapted to effect such steps, all as exemplified in the following detailed disclosure, and the scope of the invention will be indicated in the claims.
- Fig. 1 shows the processing steps in an MPEG decoder
- Fig. 2 shows the expansion of the run level data into its matrix form
- Fig. 3 shows the multiplication of the run level expanded matrix by the IQ scalar matrix to produce a third dequantized matrix
- Fig. 4 shows the replacement of a run/level pair with a new coordinate/dequantized pair
- Fig. 5 is a flow chart showing the method of the invention.
- Figs. 6A and 6B show the relationships between the prior art video decoders and decoders in accordance with the invention.
- the output of the VLD 24 produces 1 x N vectors each comprised of a variable number of run/level pairs.
- the run value of each pair indicates the number of zeros before the non-zero value is obtained in an 8 by 8 matrix of DCT values. So, for example, a run/level pair could be 10/2.
- Fig. 2 shows an example of an 8 by 8 matrix with a run of 10 zero values and a final level of 2.
- the path that the matrix is scanned is in accordance with the inverse scan operation.
- the inverse scan is a zig zag pattern where 10 zeros are collected until a final value of 2 is found. Thus, it has a run/level of 10/2.
- the run level expanded matrix RLEM is reconstructed from the run level values and then it is multiplied by a scalar inverse quantization matrix SM, to form a resulting matrix RM.
- the fifth position (using a row major count) or the 10th position (using an inverse scan count) of the scalar matrix SM is multiplied by the level 2 (which is in the fifth position row major count, 10th position using an inverse scan count) of the 8 by 8 transform matrix.
- the resulting matrix is RM then subjected to the IDCT operation.
- the zeroes of the transform matrix result in zeroes in the final matrix RM.
- This multiplication is therefore a waste of computation time and storage.
- the run/level values are not expanded into the matrix before inverse quantization. Instead inverse quantization is performed on the levels only.
- Fig. 4 shows the information as it is transformed from its run/level values (shown at A) into its form after inverse scan and inverse quantization (shown at B) in accordance with the invention.
- the run/levels 10/2 have been converted to pointer positions and dequantized levels, e.g. 5/6.
- the pointer value 5 indicates the position in the 8 x 8 matrix where the value 6 should be found. This pointer position is the linear row-major count (as shown in the resulting matrix RM of Fig. 3).
- the value 6 is the result of the level 2 being multiplied by the scalar value 3 which is found in the same location in the scalar matrix SM as the 2 is found in the RLD matrix.
- the efficiency of the decoding process is improved by performing the inverse scan operation during inverse quantization as opposed to during RLD. This is achieved by translating the run value (in-place) to a row-major count that represents the location of the datum in the eventual DCT matrix as a simple offset into the block. At this point the IDCT can be performed after the expansion into the DCT matrix takes place. Accordingly, the RLD, IQ and IZZ do not have to have the large memories to accommodate the expanded matrices. Instead the run level format is carried throughout these processes.
- the method of decoding in accordance with the invention, is shown in Fig. 5, in flow chart form, and described as follows:
- the 1 x N vectors, or run/levels with both zigzag and alternate scan ordering for the intra and non-intra quantization tables, are generated in a step 500.
- N is the number of coefficients in the coded block.
- the RLD-IZZ-IDPCM+IQ sequence of operation is replaced with the IDPCM+IQ, IZZ, RLD sequence by performing the following steps: For each slice (step 502) at the output of the VLD, and for each coded block (step 504) in a non-skipped macroblock, the DC coefficient is dequantized (as per ISO/IEC 13818-2) in a step 506.
- a run-index is set to 1 (step 508) and for each new run/level pair, the run- index is incremented by the size of the new run value in a step 510.
- the quantizer value is found in the appropriate zig-zag/alternate scan, intra/non-intra, matrix using the run-index as the index into the quantization matrix.
- each AC-coefficient is dequantized by multiplying the quantizer value by the level value of the run/level pair.
- the run-index is translated into its inverse scan position using a linear row-major count and the translated value is stored in-place of the run value of the run level pair.
- the slice is transmitted in its now dequantized, run/level form to the subsystem where the RLD expansion is to occur. RLD expansion is performed as a prelude to IDCT, at a point where the full reconstruction buffers are available.
- expansion buffers are not needed until inverse discrete cosine transformation must occur as shown in Figs. 6a and 6b.
- Numeral 61 in fig. 6a shows where the data is expanded in the prior art, at the output 62 of the RLD.
- the 8 x 8 matrix is not constructed until after inverse quantization, and inverse scan, i.e at the output of the RLE, the run level expander. Therefore the expansion buffers are not needed for the IQ or IZZ steps.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53470399A JP2001513311A (en) | 1997-12-23 | 1998-12-21 | Method for reducing the number of storage devices and computations required for inverse quantization and inverse scanning in MPEG video decoding |
EP98959091A EP0962100A2 (en) | 1997-12-23 | 1998-12-21 | Method for reducing the storage and number of computations required for inverse quantization and inverse scan in mpeg video decoding |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US99667097A | 1997-12-23 | 1997-12-23 | |
US08/996,670 | 1997-12-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1999034604A2 true WO1999034604A2 (en) | 1999-07-08 |
WO1999034604A3 WO1999034604A3 (en) | 1999-08-19 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/IB1998/002089 WO1999034604A2 (en) | 1997-12-23 | 1998-12-21 | Method for reducing the storage and number of computations required for inverse quantization and inverse scan in mpeg video decoding |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0962100A2 (en) |
JP (1) | JP2001513311A (en) |
KR (1) | KR20000075527A (en) |
WO (1) | WO1999034604A2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5604540A (en) * | 1995-02-16 | 1997-02-18 | C-Cube Microsystems, Inc. | Structure and method for a multistandard video encoder |
-
1998
- 1998-12-21 EP EP98959091A patent/EP0962100A2/en not_active Withdrawn
- 1998-12-21 JP JP53470399A patent/JP2001513311A/en active Pending
- 1998-12-21 KR KR1019997007586A patent/KR20000075527A/en not_active Application Discontinuation
- 1998-12-21 WO PCT/IB1998/002089 patent/WO1999034604A2/en not_active Application Discontinuation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5604540A (en) * | 1995-02-16 | 1997-02-18 | C-Cube Microsystems, Inc. | Structure and method for a multistandard video encoder |
Also Published As
Publication number | Publication date |
---|---|
EP0962100A2 (en) | 1999-12-08 |
KR20000075527A (en) | 2000-12-15 |
JP2001513311A (en) | 2001-08-28 |
WO1999034604A3 (en) | 1999-08-19 |
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